公开(公告)号：US20120181549A1

公开(公告)日：2012-07-19

申请号：US13009029

申请日：2011-01-19

申请人： Jeffrey B. Johnson ,  Ramachandran Muralidhar ,  Philip J. Oldiges ,  Viorel Ontalus ,  Kai Xiu

发明人： Jeffrey B. Johnson ,  Ramachandran Muralidhar ,  Philip J. Oldiges ,  Viorel Ontalus ,  Kai Xiu

IPC分类号： H01L29/161 ,  H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7848 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78

摘要： A method for forming a stressed channel field effect transistor (FET) with source/drain buffers includes etching cavities in a substrate on either side of a gate stack located on the substrate; depositing source/drain buffer material in the cavities; etching the source/drain buffer material to form vertical source/drain buffers adjacent to a channel region of the FET; and depositing source/drain stressor material in the cavities adjacent to and over the vertical source/drain buffers.

摘要翻译： 用于形成具有源极/漏极缓冲器的应力通道场效应晶体管（FET）的方法包括在位于衬底上的栅极堆叠的任一侧上的衬底中的蚀刻腔; 在空腔中沉积源极/漏极缓冲材料; 蚀刻源极/漏极缓冲材料以形成与FET的沟道区相邻的垂直源极/漏极缓冲器; 以及将源极/漏极应力源材料沉积在与垂直源极/漏极缓冲器相邻并在其上方的空腔中。

公开(公告)号：US08361847B2

公开(公告)日：2013-01-29

申请号：US13009029

申请日：2011-01-19

申请人： Jeffrey B. Johnson ,  Ramachandran Muralidhar ,  Philip J. Oldiges ,  Viorel C. Ontalus ,  Kai Xiu

发明人： Jeffrey B. Johnson ,  Ramachandran Muralidhar ,  Philip J. Oldiges ,  Viorel C. Ontalus ,  Kai Xiu

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78

摘要： A method for forming a stressed channel field effect transistor (FET) with source/drain buffers includes etching cavities in a substrate on either side of a gate stack located on the substrate; depositing source/drain buffer material in the cavities; etching the source/drain buffer material to form vertical source/drain buffers adjacent to a channel region of the FET; and depositing source/drain stressor material in the cavities adjacent to and over the vertical source/drain buffers.

摘要翻译： 用于形成具有源极/漏极缓冲器的应力通道场效应晶体管（FET）的方法包括在位于衬底上的栅极堆叠的任一侧上的衬底中的蚀刻腔; 在空腔中沉积源极/漏极缓冲材料; 蚀刻源极/漏极缓冲材料以形成与FET的沟道区相邻的垂直源极/漏极缓冲器; 以及将源极/漏极应力源材料沉积在与垂直源极/漏极缓冲器相邻并在其上方的空腔中。

公开(公告)号：US20120261672A1

公开(公告)日：2012-10-18

申请号：US13084594

申请日：2011-04-12

申请人： Dureseti Chidambarrao ,  Ramachandran Muralidhar ,  Philip J. Oldiges ,  Viorel Ontalus

发明人： Dureseti Chidambarrao ,  Ramachandran Muralidhar ,  Philip J. Oldiges ,  Viorel Ontalus

IPC分类号： H01L27/092 ,  H01L21/782 ,  H01L21/8238 ,  H01L27/12

CPC分类号： H01L21/823814 ,  H01L21/3086 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823864 ,  H01L21/84

摘要： A semiconductor structure and method for forming dielectric spacers and epitaxial layers for a complementary metal-oxide-semiconductor field effect transistor (CMOS transistor) are disclosed. Specifically, the structure and method involves forming dielectric spacers that are disposed in trenches and are adjacent to the silicon substrate, which minimizes leakage current. Furthermore, epitaxial layers are deposited to form source and drain regions, wherein the source region and drain regions are spaced at a distance from each other. The epitaxial layers are disposed adjacent to the dielectric spacers and the transistor body regions (i.e., portion of substrate below the gates), which can minimize transistor junction capacitance. Minimizing transistor junction capacitance can enhance the switching speed of the CMOS transistor. Accordingly, the application of dielectric spacers and epitaxial layers to minimize leakage current and transistor junction capacitance in CMOS transistors can enhance the utility and performance of the CMOS transistors in low power applications.

摘要翻译： 公开了用于形成用于互补金属氧化物半导体场效应晶体管（CMOS晶体管）的电介质间隔物和外延层的半导体结构和方法。 具体地，该结构和方法包括形成设置在沟槽中并且与硅衬底相邻的电介质间隔物，这使漏电流最小化。 此外，沉积外延层以形成源极和漏极区域，其中源极区域和漏极区域彼此间隔一定距离。 外延层邻近电介质间隔物和晶体管本体区域（即，栅极下方的衬底部分）设置，这可使晶体管结电容最小化。 最小化晶体管结电容可以提高CMOS晶体管的开关速度。 因此，应用介电间隔物和外延层以最小化CMOS晶体管中的漏电流和晶体管结电容可以增强低功率应用中CMOS晶体管的效用和性能。

公开(公告)号：US08288217B2

公开(公告)日：2012-10-16

申请号：US12945026

申请日：2010-11-12

申请人： Dechao Guo ,  Pranita Kulkarni ,  Philip J. Oldiges ,  Alexander Reznicek ,  Keith Kwong Hon Wong

发明人： Dechao Guo ,  Pranita Kulkarni ,  Philip J. Oldiges ,  Alexander Reznicek ,  Keith Kwong Hon Wong

IPC分类号： H01L21/338

CPC分类号： H01L29/66545 ,  H01L29/1054 ,  H01L29/66477 ,  H01L29/66651 ,  H01L29/7843 ,  H01L29/7848

摘要： A field effect transistor device includes a gate stack portion disposed on a substrate, and a channel region in the substrate having a depth partially defined by the gate stack portion and a silicon region of the substrate, the silicon region having a sloped profile such that a distal regions of the channel region have greater depth than a medial region of the channel region.

摘要翻译： 场效应晶体管器件包括设置在衬底上的栅极堆叠部分和衬底中的沟道区域，其具有由栅极堆叠部分和衬底的硅区域部分地限定的深度，所述硅区域具有倾斜轮廓，使得 沟道区域的远侧区域具有比沟道区域的中间区域更深的深度。

公开(公告)号：US07767503B2

公开(公告)日：2010-08-03

申请号：US12132853

申请日：2008-06-04

申请人： Huilong Zhu ,  Philip J. Oldiges ,  Bruce B. Doris ,  Xinlin Wang ,  Oleg Gluschenkov ,  Huajie Chen ,  Ying Zhang

发明人： Huilong Zhu ,  Philip J. Oldiges ,  Bruce B. Doris ,  Xinlin Wang ,  Oleg Gluschenkov ,  Huajie Chen ,  Ying Zhang

IPC分类号： H01L21/84 ,  H01L21/336

CPC分类号： H01L29/7849 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78612 ,  H01L29/78618 ,  H01L29/78687

摘要： Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.

摘要翻译： 场效应晶体管中的沟道深度由包括在半导体材料的层或衬底内形成的不连续膜或层的层内结构限制。 因此，可以以SOI或UT-SOI技术的方式控制通道深度，但是具有较便宜的衬底和更大的通道深度控制的灵活性，同时避免SOI技术的浮体效应特性。 不连续膜的轮廓或横截面形状可以被控制为奥格或阶梯形状，以改善短通道效应，并且在不增加电容的情况下降低源极/漏极和延伸电阻。 也可以选择用于不连续膜的材料以在衬底或层内从晶体管沟道施加应力，并提供增加的这种应力水平以增加载流子迁移率。 携带者的流动性可能会与其他有利的影响相结合。

公开(公告)号：US20080242069A1

公开(公告)日：2008-10-02

申请号：US12132853

申请日：2008-06-04

申请人： Huilong Zhu ,  Philip J. Oldiges ,  Bruce B. Doris ,  Xinlin Wang ,  Oleg Gluschenkov ,  Huajie Chen ,  Ying Zhang

发明人： Huilong Zhu ,  Philip J. Oldiges ,  Bruce B. Doris ,  Xinlin Wang ,  Oleg Gluschenkov ,  Huajie Chen ,  Ying Zhang

IPC分类号： H01L21/3205

CPC分类号： H01L29/7849 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78612 ,  H01L29/78618 ,  H01L29/78687

摘要： Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.

摘要翻译： 场效应晶体管中的沟道深度由包括在半导体材料的层或衬底内形成的不连续膜或层的层内结构限制。 因此，可以以SOI或UT-SOI技术的方式控制通道深度，但是具有较便宜的衬底和更大的通道深度控制的灵活性，同时避免SOI技术的浮体效应特性。 不连续膜的轮廓或横截面形状可以被控制为奥格或阶梯形状，以改善短通道效应，并且在不增加电容的情况下降低源极/漏极和延伸电阻。 也可以选择用于不连续膜的材料以在衬底或层内从晶体管沟道施加应力，并提供增加的这种应力水平以增加载流子迁移率。 携带者的流动性可能会与其他有利的影响相结合。

公开(公告)号：US20080016477A1

公开(公告)日：2008-01-17

申请号：US11457174

申请日：2006-07-13

申请人： AJ Kleinosowski ,  Philip J. Oldiges ,  Paul M. Solomon ,  Richard Q. Williams

发明人： AJ Kleinosowski ,  Philip J. Oldiges ,  Paul M. Solomon ,  Richard Q. Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G01R31/31816 ,  G01R31/318357

摘要： A method of modeling soft errors in a logic circuit uses two separate current sources inserted at the source and drain of a device to simulate a single event upset (SEU) caused by, e.g., an alpha-particle strike. In an nfet implementation the current flows from the source or drain toward the body of the device. Current waveforms having known amplitudes are injected at the current sources while simulating operation of the logic circuit and the state of the logic circuit is determined from the simulated operation. The amplitudes of the current waveforms can be independently adjusted. The simulator monitors the state of device and makes a log entry when a transition occurs. The process may be repeated for other devices in the logic circuit to provide an overall characterization of the susceptibility of the circuit to soft errors.

摘要翻译： 在逻辑电路中对软错误进行建模的方法使用在设备的源极和漏极处插入的两个单独的电流源来模拟由例如α粒子撞击引起的单个事件不正常（SEU）。 在nfet实现中，电流从源极或漏极流向器件的主体。 具有已知幅度的电流波形在电流源处被注入，同时模拟逻辑电路的操作，并且根据模拟操作确定逻辑电路的状态。 可以独立调整电流波形的幅度。 模拟器监视设备的状态，并在转换发生时创建日志条目。 逻辑电路中的其他器件可以重复该过程以提供电路对软错误的敏感性的整体表征。

公开(公告)号：US07315075B2

公开(公告)日：2008-01-01

申请号：US10905906

申请日：2005-01-26

申请人： John M Aitken ,  Ethan H. Cannon ,  Philip J. Oldiges ,  Alvin W. Strong

发明人： John M Aitken ,  Ethan H. Cannon ,  Philip J. Oldiges ,  Alvin W. Strong

IPC分类号： H01L29/00 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L27/1203 ,  H01L29/92

摘要： Disclosed is a semiconductor structure that incorporates a capacitor for reducing the soft error rate of a device within the structure. The multi-layer semiconductor structure includes an insulator-filled deep trench isolation structure that is formed through an active silicon layer, a first insulator layer, and a first bulk layer and extends to a second insulator layer. The resulting isolated portion of the first bulk layer defines the first capacitor plate. A portion of the second insulator layer that is adjacent the first capacitor plate functions as the capacitor dielectric. Either the silicon substrate or a portion of a second bulk layer that is isolated by a third insulator layer and another deep trench isolation structure can function as the second capacitor plate. A first capacitor contact couples, either directly or via a wire array, the first capacitor plate to a circuit node of the device in order to increase the critical charge, Qcrit, of the circuit node.

摘要翻译： 公开了一种包含用于降低结构内的器件的软错误率的电容器的半导体结构。 多层半导体结构包括通过有源硅层，第一绝缘体层和第一体层形成并延伸到第二绝缘体层的绝缘体填充的深沟槽隔离结构。 所形成的第一体层的隔离部分限定第一电容器板。 与第一电容器板相邻的第二绝缘体层的一部分用作电容器电介质。 硅衬底或由第三绝缘体层和另一个深沟槽隔离结构隔离的第二体层的一部分可以用作第二电容器板。 第一电容器触点直接地或经由线阵列将第一电容器板耦合到器件的电路节点，以便增加电路节点的临界电荷Qcrit。

公开(公告)号：US07064414B2

公开(公告)日：2006-06-20

申请号：US10904483

申请日：2004-11-12

申请人： John M Aitken ,  Ethan H. Cannon ,  Philip J. Oldiges ,  Alvin W. Strong

发明人： John M Aitken ,  Ethan H. Cannon ,  Philip J. Oldiges ,  Alvin W. Strong

IPC分类号： H01L29/00

CPC分类号： H01L24/80 ,  H01L23/345 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/00

摘要： A structure and associated method for annealing a trapped charge from a semiconductor device. The semiconductor structure comprises a substrate and a first heating element. The substrate comprises a bulk layer, an insulator layer and a device layer. The first heating element is formed within the bulk layer. A first side of the first heating element is adjacent to a first portion of the insulator layer. The first heating element is adapted to be selectively activated to generate thermal energy to heat the first portion of the insulator layer and anneal a trapped electrical charge from the first portion of the insulator layer.

摘要翻译： 一种从半导体器件退火俘获电荷的结构和相关方法。 半导体结构包括基板和第一加热元件。 衬底包括体层，绝缘体层和器件层。 第一加热元件形成在本体层内。 第一加热元件的第一侧与绝缘体层的第一部分相邻。 第一加热元件适于被选择性地激活以产生热能来加热绝缘体层的第一部分并且从绝缘体层的第一部分退火被俘获的电荷。

公开(公告)号：US08354720B2

公开(公告)日：2013-01-15

申请号：US13529558

申请日：2012-06-21

申请人： Dechao Guo ,  Shu-Jen Han ,  Pranita Kulkarni ,  Philip J. Oldiges

发明人： Dechao Guo ,  Shu-Jen Han ,  Pranita Kulkarni ,  Philip J. Oldiges

IPC分类号： H01L27/12

CPC分类号： H01L29/1054 ,  H01L29/517 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/78687

摘要： A semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; a plurality of spacers disposed on laterally opposing sides of the gate stack; source and drain regions proximate to the spacers, and a channel region subjacent to the gate stack and disposed between the source and drain regions; and a stressor subjacent to the channel region, and embedded within the semiconductor substrate, the embedded stressor being formed of a triangular-shape.

摘要翻译： 半导体结构包括半导体衬底; 半导体衬底上的栅极堆叠; 设置在所述栅极堆叠的横向相对侧上的多个间隔件; 邻近间隔物的源极和漏极区域以及位于栅极堆叠下方并设置在源极和漏极区域之间的沟道区域; 以及位于所述沟道区域的下方并嵌入在所述半导体衬底内的应力器，所述嵌入式应力器由三角形形成。