公开(公告)号：US5976911A

公开(公告)日：1999-11-02

申请号：US163132

申请日：1998-09-29

申请人： Jeffrey D. Bruce ,  Gordon D. Roberts ,  Aaron M. Schoenfeld

发明人： Jeffrey D. Bruce ,  Gordon D. Roberts ,  Aaron M. Schoenfeld

IPC分类号： H01L23/495 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L23/49531 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111

摘要： A semiconductor assembly includes two leads, a primary die and a secondary support structure. Impedance networks of the secondary support structure establish an impedance between each lead and a different bond pad of the primary die. Although the distances between each bond pad and lead are substantially different, the impedances between each bond pad and lead are substantially the same.

公开(公告)号：US6008533A

公开(公告)日：1999-12-28

申请号：US987000

申请日：1997-12-08

申请人： Jeffrey D. Bruce ,  Gordon D. Roberts ,  Aaron M. Schoenfeld

发明人： Jeffrey D. Bruce ,  Gordon D. Roberts ,  Aaron M. Schoenfeld

IPC分类号： H01L23/495 ,  H01L23/52

CPC分类号： H01L23/49531 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111

摘要： A semiconductor assembly includes two leads, a primary die and a secondary support structure. Impedance networks of the secondary support structure establish an impedance between each lead and a different bond pad of the primary die. Although the distances between each bond pad and lead are substantially different, the impedances between each bond pad and lead are substantially the same.

摘要翻译： 半导体组件包括两个引线，一个主晶片和二次支撑结构。 辅助支撑结构的阻抗网络在每个引线和主晶片的不同接合焊盘之间建立阻抗。 虽然每个接合焊盘和引线之间的距离基本上不同，但每个接合焊盘和引线之间的阻抗基本相同。

公开(公告)号：US6011731A

公开(公告)日：2000-01-04

申请号：US259221

申请日：1999-03-01

申请人： Kurt D. Beigel ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

发明人： Kurt D. Beigel ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

IPC分类号： G11C7/00 ,  G11C29/02 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/56

CPC分类号： G11C29/026 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/56 ,  G11C11/401 ,  G11C2029/5004

摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

摘要翻译： 作为存储器阵列的一部分，提供了用于改变施加到调节存储器阵列内的电通信的存取晶体管的驱动电路的电路。 在一个实施例中，该电路用于改变施加到感测放大器的电压 - 牵引晶体管的驱动，从而允许改变感测放大器部件的电压提升率。 将测试数据的样本写入存储器阵列，并以变化的驱动速率读取数次，以便确定感测放大器容纳外部电路的能力。 在另一个实施例中，电路用于改变施加到泄放装置的驱动，其调节存储器阵列的数字线与其单元板之间的通信。 减轻所述通信允许存储器阵列中的缺陷具有更显着的效果，并因此增加在测试期间发现这些缺陷的机会。 电路被配置为通过接触焊盘或耦合到电路的一系列离散电压源来接受和施加多个电压。

公开(公告)号：US5770480A

公开(公告)日：1998-06-23

申请号：US833863

申请日：1997-04-10

申请人： Manny Kin F. Ma ,  Jeffrey D. Bruce ,  Daryl L. Habersetzer ,  Gordon D. Roberts ,  James E. Miller

发明人： Manny Kin F. Ma ,  Jeffrey D. Bruce ,  Daryl L. Habersetzer ,  Gordon D. Roberts ,  James E. Miller

IPC分类号： H01L23/44 ,  H01L23/495 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L23/49575 ,  H01L23/49537 ,  H01L23/49541 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L24/45 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/30107

摘要： A device and method for increasing integrated circuit density comprising at least a pair of superimposed dice, wherein a least one of the superimposed dice has at least one bond pad variably positioned on an active surface of the die. A plurality of lead fingers from a leadframe extend between the dice. The leadframe comprises at least one lead with leads of non-uniform length and configuration to attach to the differently positioned bond pads of the multiple die. An advantage of the present invention is that it allows dice with differing bond pad arrangements to be used in a superimposed configuration to increase circuit density, while eliminating the use of bond wires in such a configuration.

摘要翻译： 一种用于提高集成电路密度的装置和方法，包括至少一对叠加的骰子，其中所述叠加的骰子中的至少一个具有可变地定位在所述骰子的有效表面上的至少一个接合衬垫。 来自引线框架的多根引线指在芯片之间延伸。 引线框架包括至少一个具有不均匀长度和配置的引线的引线，以连接到多个管芯的不同定位的焊盘。 本发明的一个优点是，允许具有不同粘合垫布置的骰子以叠加配置使用以增加电路密度，同时消除在这种配置中使用接合线。

公开(公告)号：US5677567A

公开(公告)日：1997-10-14

申请号：US664409

申请日：1996-06-17

申请人： Manny Kin F. Ma ,  Jeffrey D. Bruce ,  Daryl L. Habersetzer ,  Gordon D. Roberts ,  James E. Miller

发明人： Manny Kin F. Ma ,  Jeffrey D. Bruce ,  Daryl L. Habersetzer ,  Gordon D. Roberts ,  James E. Miller

IPC分类号： H01L23/44 ,  H01L23/495

CPC分类号： H01L23/49575 ,  H01L23/49537 ,  H01L23/49541 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L24/45 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/30107

摘要： A device and method for increasing integrated circuit density comprising at least a pair of superimposed dice, wherein at least one of the superimposed dice has at least one bond pad variably positioned on an active surface of the die. A plurality of lead fingers from a leadframe extend between the dice. The leadframe comprises at least one lead with leads of non-uniform length and configuration to attach to the differently positioned bond pads of the multiple dice. An advantage of the present invention is that it allows dice with differing bond pad arrangements to be used in a superimposed configuration to increase circuit density, while eliminating the use of bond wires in such a configuration.

摘要翻译： 一种用于增加集成电路密度的装置和方法，包括至少一对叠加的骰子，其中所述叠加的骰子中的至少一个具有可变地定位在所述骰子的有效表面上的至少一个接合衬垫。 来自引线框架的多根引线指在芯片之间延伸。 引线框架包括至少一个引线，引线具有不均匀的长度和结构，以连接到多个裸片的不同定位的焊盘。 本发明的一个优点是，允许具有不同粘合垫布置的骰子以叠加配置使用以增加电路密度，同时消除在这种配置中使用接合线。

公开(公告)号：US06600687B2

公开(公告)日：2003-07-29

申请号：US10253844

申请日：2002-09-23

申请人： Kurt D. Beigel ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

发明人： Kurt D. Beigel ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

IPC分类号： G11C700

CPC分类号： G11C29/026 ,  G11C11/401 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/56 ,  G11C2029/5004

摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

公开(公告)号：US06353564B1

公开(公告)日：2002-03-05

申请号：US09735157

申请日：2000-12-11

申请人： Kurt D. Beigel ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

发明人： Kurt D. Beigel ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

IPC分类号： G11C2900

CPC分类号： G11C29/026 ,  G11C11/401 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/56 ,  G11C2029/5004

摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

公开(公告)号：US06335888B2

公开(公告)日：2002-01-01

申请号：US09735120

申请日：2000-12-11

申请人： Kurt D. Beigel ,  Douglas J. Cutter ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

发明人： Kurt D. Beigel ,  Douglas J. Cutter ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

IPC分类号： G11C700

CPC分类号： G11C29/026 ,  G11C11/401 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/56 ,  G11C2029/5004

摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

摘要翻译： 作为存储器阵列的一部分，提供了用于改变施加到调节存储器阵列内的电通信的存取晶体管的驱动电路的电路。 在一个实施例中，该电路用于改变施加到感测放大器的电压 - 牵引晶体管的驱动，从而允许改变感测放大器部件的电压提升率。 将测试数据的样本写入存储器阵列，并以变化的驱动速率读取数次，以便确定感测放大器容纳外部电路的能力。 在另一个实施例中，电路用于改变施加到泄放装置的驱动，其调节存储器阵列的数字线与其单元板之间的通信。 减轻所述通信允许存储器阵列中的缺陷具有更显着的效果，并因此增加在测试期间发现这些缺陷的机会。 电路被配置为通过接触焊盘或耦合到电路的一系列离散电压源来接受和施加多个电压。

公开(公告)号：US06226210B1

公开(公告)日：2001-05-01

申请号：US09482716

申请日：2000-01-12

申请人： Kurt D. Beigel ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

发明人： Kurt D. Beigel ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

IPC分类号： G11C700

CPC分类号： G11C29/026 ,  G11C11/401 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/56 ,  G11C2029/5004

摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a is plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

摘要翻译： 作为存储器阵列的一部分，提供了用于改变施加到调节存储器阵列内的电通信的存取晶体管的驱动电路的电路。 在一个实施例中，该电路用于改变施加到感测放大器的电压 - 牵引晶体管的驱动，从而允许改变感测放大器部件的电压提升率。 将测试数据的样本写入存储器阵列，并以变化的驱动速率读取数次，以便确定感测放大器容纳外部电路的能力。 在另一个实施例中，电路用于改变施加到泄放装置的驱动，其调节存储器阵列的数字线与其单元板之间的通信。 减轻所述通信允许存储器阵列中的缺陷具有更显着的效果，并因此增加在测试期间发现这些缺陷的机会。 电路被配置为通过接触焊盘或耦合到电路的一系列离散电压源来接受和施加多个电压。

公开(公告)号：US06198676B1

公开(公告)日：2001-03-06

申请号：US09483266

申请日：2000-01-11

申请人： Kurt D. Beigel ,  Douglas J. Cutter ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

发明人： Kurt D. Beigel ,  Douglas J. Cutter ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

IPC分类号： G11C700

CPC分类号： G11C29/026 ,  G11C11/401 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/56 ,  G11C2029/5004

摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

摘要翻译： 作为存储器阵列的一部分，提供了用于改变施加到调节存储器阵列内的电通信的存取晶体管的驱动电路的电路。 在一个实施例中，该电路用于改变施加到感测放大器的电压 - 牵引晶体管的驱动，从而允许改变感测放大器部件的电压提升率。 将测试数据的样本写入存储器阵列，并以变化的驱动速率读取数次，以便确定感测放大器容纳外部电路的能力。 在另一个实施例中，电路用于改变施加到泄放装置的驱动，其调节存储器阵列的数字线与其单元板之间的通信。 减轻所述通信允许存储器阵列中的缺陷具有更显着的效果，并因此增加在测试期间发现这些缺陷的机会。 电路被配置为通过接触焊盘或耦合到电路的一系列离散电压源来接受和施加多个电压。