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1.发明授权Method for performing branch prediction and resolution of two or more branch instructions within two or more branch prediction buffers 失效用于在两个或更多个分支预测缓冲器内执行两个或多个分支指令的分支预测和分辨率的方法
公开(公告)号：US06157998A
公开(公告)日：2000-12-05
申请号：US54810
申请日：1998-04-03
CPC分类号： G06F9/3851 , G06F9/3844 , G06F9/3861
摘要： A branch prediction unit apparatus and method uses an instruction buffer (20), a completion unit (24), and a branch prediction unit (BPU) (28). The instruction buffer (20) and/or the completion unit (24) contain a plurality of instruction entries that contain valid bits and stream identifier (SID) bits. The branch prediction unit contains a plurality of branch prediction buffers (28a-28c). The SID bits are used to associate the pending and executing instructions in the units (20 and 24) into instruction streams related to predicted branches located in the buffers (28a-28c). The SID bits as well as age bits associated with the buffers (28a-28c) are used to perform efficient branch prediction, branch resolution/retirement, and branch misprediction recovery.
摘要翻译： 分支预测单元装置和方法使用指令缓冲器（20），完成单元（24）和分支预测单元（BPU）（28）。 指令缓冲器（20）和/或完成单元（24）包含包含有效位和流标识符（SID）位的多个指令条目。 分支预测单元包含多个分支预测缓冲器（28a-28c）。 SID位用于将单元（20和24）中的待执行和执行的指令与位于缓冲器（28a-28c）中的预测分支相关的指令流相关联。 SID位以及与缓冲器（28a-28c）相关联的老化位用于执行有效的分支预测，分支解决/退出和分支错误预测恢复。
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2.发明授权Apparatus and method for predicting multiple branches and performing out-of-order branch resolution 失效用于预测多个分支并执行无序分支分辨率的装置和方法公开(公告)号：US06477640B1
公开(公告)日：2002-11-05
申请号：US09659401
申请日：2000-09-11
IPC分类号： G06F1560
CPC分类号： G06F9/3851 , G06F9/3844 , G06F9/3861
摘要： A branch prediction unit apparatus and method uses an instruction buffer (20), a completion unit (24), and a branch prediction unit (BPU) (28). The instruction buffer (20) and/or the completion unit (24) contain a plurality of instruction entries that contain valid bits and stream identifier (SID) bits. The branch prediction unit contains a plurality of branch prediction buffers (28a-28c). The SID bits are used to associate the pending and executing instructions in the units (20 and 24) into instruction streams related to predicted branches located in the buffers (28a-28c). The SID bits as well as age bits associated with the buffers (28a-28c) are used to perform efficient branch prediction, branch resolution/retirement, and branch misprediction recovery.
摘要翻译： 分支预测单元装置和方法使用指令缓冲器（20），完成单元（24）和分支预测单元（BPU）（28）。 指令缓冲器（20）和/或完成单元（24）包含包含有效位和流标识符（SID）位的多个指令条目。 分支预测单元包含多个分支预测缓冲器（28a-28c）。 SID位用于将单元（20和24）中的待执行和执行的指令与位于缓冲器（28a-28c）中的预测分支相关的指令流相关联。 SID位以及与缓冲器（28a-28c）相关联的老化位用于执行有效的分支预测，分支解决/退出和分支错误预测恢复。
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公开(公告)号：US08508534B1
公开(公告)日：2013-08-13
申请号：US12131011
申请日：2008-05-30
IPC分类号： G06T13/00
CPC分类号： G06T13/80
摘要： Input is received that selects an animation aspect associated with an object within an animation. The animation involves the object and an original frame of reference through which the animation is displayed, and the selected animation aspect is one that changes over time with respect to the original frame of reference. The animation is displayed through a new frame of reference defined by holding the selected animation aspect constant over time. During the animation display through the new frame of reference, input is received that manipulates the object to create a new animation aspect associated with the object. The new animation aspect associated with the object is recorded in the animation.
摘要翻译： 接收到输入，其选择与动画内的对象相关联的动画方面。 该动画涉及对象以及显示动画的原始参照系，并且所选择的动画方面是相对于原始参考帧随时间而改变的动画方面。 动画通过一段新的参考框架来显示，通过随着时间的推移保持所选择的动画方面的常数而定义。 在通过新的参考框架的动画显示期间，接收到操纵对象以创建与对象相关联的新动画方面的输入。 与该对象相关联的新动画方面将记录在动画中。
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公开(公告)号：US20090172361A1
公开(公告)日：2009-07-02
申请号：US11967430
申请日：2007-12-31
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/3861 , G06F9/3867
摘要： A thread switch mechanism and technique for a microprocessor is disclosed wherein a processing of a first thread is completed, and a continuation of a second thread is initiated during completion of the first thread. In one form, the technique includes processing a first thread at a pipeline of a processing device, and initiating processing of a second thread at a front end of the pipeline in response to an occurrence of a context switch event. The technique can also include initiating a instruction progress metric in response the context switch event. The technique can further include enabling completion of processing of instructions of the first thread that are at a back end of the pipeline at the occurrence of the context switch event until an expiry of the instruction progress metric.
摘要翻译： 公开了一种用于微处理器的线程切换机制和技术，其中完成了第一线程的处理，并且在完成第一线程期间开始了第二线程的延续。 在一种形式中，该技术包括处理处理设备的流水线处的第一线程，以及响应于上下文切换事件的发生，在流水线的前端开始处理第二线程。 该技术还可以包括响应于上下文切换事件发起指令进展度量。 该技术还可以包括在上下文切换事件发生时能够完成在流水线的后端处理第一线程的指令，直到指令进度度量的到期为止。
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5.发明授权Multiple address and arithmetic bit-mode data processing device and methods thereof 有权多地址和算术位模式数据处理装置及其方法公开(公告)号：US07805581B2
公开(公告)日：2010-09-28
申请号：US11679590
申请日：2007-02-27
IPC分类号： G06F12/00
CPC分类号： G06F9/30181 , G06F9/30014 , G06F9/30189 , G06F9/342
摘要： A data processing device and methods thereof are disclosed. The data processing device can operate in three different modes. In a first, N-bit mode, the data processing device performs memory accesses based on N-bit values and performs arithmetic operations using N-bit values. In a second, hybrid N-bit/M-bit mode, the data processing device performs memory accesses based on M-bit values, where M is less than N, and performs arithmetic operations using N-bit values. In a third, M-bit mode, the data processing device performs memory accesses based on M-bit values and performs arithmetic operations using M-bit values. The three modes provide for compatibility with a wide range of applications. Further operation in the M-bit mode can provide a power savings when implementing applications compatible with that mode.
摘要翻译： 公开了一种数据处理装置及其方法。 数据处理设备可以在三种不同的模式下工作。 在第一N位模式中，数据处理装置根据N位值执行存储器访问，并使用N位值执行算术运算。 在第二种混合N比特/ M比特模式中，数据处理装置基于M比特值执行存储器访问，其中M小于N，并且使用N比特值进行算术运算。 在第三个M位模式中，数据处理设备基于M位值执行存储器访问，并使用M位值执行算术运算。 这三种模式提供与广泛应用的兼容性。 当实现与该模式兼容的应用时，在M位模式下的进一步操作可以提供功率节省。
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公开(公告)号：US5449302A
公开(公告)日：1995-09-12
申请号：US111260
申请日：1993-08-24
IPC分类号： H01R13/645 , H01R13/502
CPC分类号： H01R13/645
摘要： The present invention serves to prevent severe injury, loss of life or damage to expensive equipment by creating a system in which the conductors of a plug and the conductors of a receptacle can only be arranged, one with respect to the other, in a unique rotational manner depending upon the intended electrical rating of the plug and receptacle. The resulting plug will mate only with a receptacle having that same configuration. A separate indexer is disposed between the plug body and the conductor assembly to the conductors in the plug to prevent entry of the plug into a differently indexed receptacle. A polarizer in the receptacle fixes the conductor assembly of the receptacle in the same manner as the plug, to allow the plug and receptacle to be mated together when the receptacle is wired for the same electrical rating as the equipment to be energized by the plug. Visual means of identifying the rotational attitude of conductors is provided whereby the electrical rating of the plug or receptacle can be easily identified. The visual means of identification may include color as well as printed coding information.
摘要翻译： 本发明用于通过创建一种系统来防止严重的伤害，寿命损失或损坏昂贵的设备，其中插头的导体和插座的导体只能以独特的旋转方式相对于另一个布置 取决于插头和插座的预期电气额定值。 所得到的插头只能与具有相同配置的插座配合。 插头主体和导体组件之间的一个单独的分度器设置在插头中的导体上，以防止插头进入不同索引的插座。 插座中的偏振器以与插头相同的方式固定插座的导体组件，以便当插座被连接到与被插头激励的设备相同的额定电位时，将插头和插座配合在一起。 提供了识别导体的旋转姿态的视觉装置，由此能够容易地识别插头或插座的电气额定值。 识别的视觉方式可以包括颜色以及打印的编码信息。
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7.发明授权Completion continue on thread switch based on instruction progress metric mechanism for a microprocessor 有权基于微处理器的指令进度指标机制，完成线程切换公开(公告)号：US07941646B2
公开(公告)日：2011-05-10
申请号：US11967430
申请日：2007-12-31
IPC分类号： G06F9/00
CPC分类号： G06F9/3851 , G06F9/3861 , G06F9/3867
摘要： A thread switch mechanism and technique for a microprocessor is disclosed wherein a processing of a first thread is completed, and a continuation of a second thread is initiated during completion of the first thread. In one form, the technique includes processing a first thread at a pipeline of a processing device, and initiating processing of a second thread at a front end of the pipeline in response to an occurrence of a context switch event. The technique can also include initiating a instruction progress metric in response the context switch event. The technique can further include enabling completion of processing of instructions of the first thread that are at a back end of the pipeline at the occurrence of the context switch event until an expiry of the instruction progress metric.
摘要翻译： 公开了一种用于微处理器的线程切换机制和技术，其中完成了第一线程的处理，并且在完成第一线程期间开始了第二线程的延续。 在一种形式中，该技术包括处理处理设备的流水线处的第一线程，以及响应于上下文切换事件的发生，在流水线的前端开始处理第二线程。 该技术还可以包括响应于上下文切换事件发起指令进展度量。 该技术还可以包括在上下文切换事件发生时能够完成在流水线的后端处理第一线程的指令，直到指令进度度量的到期为止。
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公开(公告)号：US20080209182A1
公开(公告)日：2008-08-28
申请号：US11679590
申请日：2007-02-27
IPC分类号： G06F9/302
CPC分类号： G06F9/30181 , G06F9/30014 , G06F9/30189 , G06F9/342
摘要： A data processing device and methods thereof are disclosed. The data processing device can operate in three different modes. In a first, N-bit mode, the data processing device performs memory accesses based on N-bit values and performs arithmetic operations using N-bit values. In a second, hybrid N-bit/M-bit mode, the data processing device performs memory accesses based on M-bit values, where M is less than N, and performs arithmetic operations using N-bit values. In a third, M-bit mode, the data processing device performs memory accesses based on M-bit values and performs arithmetic operations using M-bit values. The three modes provide for compatibility with a wide range of applications. Further operation in the M-bit mode can provide a power savings when implementing applications compatible with that mode.
摘要翻译： 公开了一种数据处理装置及其方法。 数据处理设备可以在三种不同的模式下工作。 在第一N位模式中，数据处理装置根据N位值执行存储器访问，并使用N位值执行算术运算。 在第二种混合N比特/ M比特模式中，数据处理装置基于M比特值执行存储器访问，其中M小于N，并且使用N比特值进行算术运算。 在第三个M位模式中，数据处理设备基于M位值执行存储器访问，并使用M位值执行算术运算。 这三种模式提供与广泛应用的兼容性。 当实现与该模式兼容的应用时，在M位模式下的进一步操作可以提供功率节省。
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公开(公告)号：US08117618B2
公开(公告)日：2012-02-14
申请号：US11871626
申请日：2007-10-12
IPC分类号： G06F9/46
CPC分类号： G06F9/4881
摘要： A processing device includes a storage component configured to store instructions associated with a corresponding thread of a plurality of threads, and an execution unit configured to fetch and execute instructions. The processing device further includes a period timer comprising an output to provide an indicator in response to a count value of the period timer reaching a predetermined value based on a clock signal. The processing device additionally includes a plurality of thread forward-progress counter components, each configured to adjust a corresponding execution counter value based on an occurrence of a forward-progress indicator while instructions of a corresponding thread are being executed. The processing device further includes a thread select module configured to select threads of the plurality of threads for execution by the execution unit based a state of the period timer and a state of each of the plurality of thread forward-progress counter components.
摘要翻译： 处理装置包括：存储部件，被配置为存储与多个线程的相应线程相关联的指令;以及执行单元，被配置为获取并执行指令。 处理装置还包括周期定时器，其包括输出，以响应于周期定时器基于时钟信号达到预定值的计数值来提供指示符。 处理装置还包括多个线程正向进行计数器组件，每个组件被配置成在正在执行对应的线程的指令的同时基于前进进度指示符的发生来调整相应的执行计数器值。 所述处理装置还包括线程选择模块，所述线程选择模块被配置为基于所述周期定时器的状态和所述多个线程前进进程计数器组件中的每一个的状态来选择所述多个线程的线程以由所述执行单元执行。
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公开(公告)号：US07636097B1
公开(公告)日：2009-12-22
申请号：US11354427
申请日：2006-02-15
申请人： David C. Holloway
发明人： David C. Holloway
IPC分类号： G09G5/00
CPC分类号： G09G5/00 , G06T11/203 , G09G5/363 , G09G2340/12
摘要： A system provides processes image data by obtaining a first image in a first data format such as a raster image. The system applies a tracing algorithm to the first image to produce a trace image of the first image. The trace image is maintained in a second data format such as a vector data format. The system displays, in an overlapping format, each of the first image in the first data format and the trace image in the second data format to allow the used to compare the differences between the two image formats. The system also provides a live trace feature that automatically applies changes to the first image in the first data format to the trace image.
摘要翻译： 系统通过获得诸如光栅图像的第一数据格式的第一图像来提供处理图像数据。 系统将跟踪算法应用于第一图像以产生第一图像的跟踪图像。 跟踪图像维持在第二数据格式，例如矢量数据格式。 该系统以重叠格式显示第一数据格式的每个第一图像和第二数据格式的跟踪图像，以允许用于比较两种图像格式之间的差异。 该系统还提供实时跟踪功能，可以将第一个数据格式的第一个图像的更改自动应用到跟踪图像。
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