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    Differential input buffers with elevated power supplies
    1.
    发明授权
    Differential input buffers with elevated power supplies 有权
    带升压电源的差分输入缓冲器

    公开(公告)号：US07046037B1

    公开(公告)日：2006-05-16

    申请号：US11153676

    申请日：2005-06-15

    申请人： Jeffrey Tyhach ,  Bonnie Wang ,  Chiakang Sung ,  Khai Nguyen

    发明人： Jeffrey Tyhach ,  Bonnie Wang ,  Chiakang Sung ,  Khai Nguyen

    IPC分类号： H03K19/0175

    CPC分类号： H03K19/018528 ,  H03K17/04106 ,  H04L25/0272 ,  H04L25/0292

    摘要： Input buffer circuitry for handling high-speed differential input signals on an integrated circuit is provided. The input buffer circuitry may use two parallel differential input buffers with overlapping input-voltage ranges. Logic on the integrated circuit may be powered at a core-logic power supply voltage. Input-output circuitry on the integrated circuit may be powered at an input-output voltage level. To improve the performance of the input buffers in the overlap range, at least one the input buffers can be powered using a total power supply voltage drop that exceeds the core-logic power supply level. One of the input buffers may be configured to handle lower-voltage input signals. This input buffer may be powered using the input-output power supply level.

    摘要翻译： 提供了用于处理集成电路中的高速差分输入信号的输入缓冲电路。 输入缓冲器电路可以使用具有重叠输入电压范围的两个并行差分输入缓冲器。 集成电路上的逻辑可以以核心逻辑电源电压供电。 集成电路上的输入输出电路可以以输入 - 输出电压电平供电。 为了在重叠范围内提高输入缓冲器的性能，可以使用超过核心逻辑电源电平的总电源电压降供电至少一个输入缓冲器。 其中一个输入缓冲器可被配置为处理较低电压的输入信号。 该输入缓冲器可以使用输入 - 输出电源电平供电。

    Differential input buffers with elevated power supplies
    2.
    发明授权
    Differential input buffers with elevated power supplies 失效
    带升压电源的差分输入缓冲器

    公开(公告)号：US06956401B1

    公开(公告)日：2005-10-18

    申请号：US10704964

    申请日：2003-11-10

    申请人： Jeffrey Tyhach ,  Bonnie Wang ,  Chiakang Sung ,  Khai Nguyen

    发明人： Jeffrey Tyhach ,  Bonnie Wang ,  Chiakang Sung ,  Khai Nguyen

    IPC分类号： H03K17/041 ,  H03K19/0175 ,  H03K19/0185 ,  H04L25/02

    CPC分类号： H03K19/018528 ,  H03K17/04106 ,  H04L25/0272 ,  H04L25/0292

    摘要： Input buffer circuitry for handling high-speed differential input signals on an integrated circuit is provided. The input buffer circuitry may use two parallel differential input buffers with overlapping input-voltage ranges. Logic on the integrated circuit may be powered at a core-logic power supply voltage. Input-output circuitry on the integrated circuit may be powered at an input-output voltage level. To improve the performance of the input buffers in the overlap range, at least one the input buffers can be powered using a total power supply voltage drop that exceeds the core-logic power supply level. One of the input buffers may be configured to handle lower-voltage input signals. This input buffer may be powered using the input-output power supply level.

    摘要翻译： 提供了用于处理集成电路中的高速差分输入信号的输入缓冲电路。 输入缓冲器电路可以使用具有重叠输入电压范围的两个并行差分输入缓冲器。 集成电路上的逻辑可以以核心逻辑电源电压供电。 集成电路上的输入输出电路可以以输入 - 输出电压电平供电。 为了在重叠范围内提高输入缓冲器的性能，可以使用超过核心逻辑电源电平的总电源电压降供电至少一个输入缓冲器。 其中一个输入缓冲器可被配置为处理较低电压的输入信号。 该输入缓冲器可以使用输入 - 输出电源电平供电。

    Modular I/O bank architecture
    3.
    发明授权
    Modular I/O bank architecture 有权
    模块化I / O银行架构

    公开(公告)号：US07378868B2

    公开(公告)日：2008-05-27

    申请号：US11558363

    申请日：2006-11-09

    申请人： Jeffrey Tyhach ,  Chiakang Sung ,  Khai Nguyen ,  Sanjay K. Charagulla ,  Ali Burney

    发明人： Jeffrey Tyhach ,  Chiakang Sung ,  Khai Nguyen ,  Sanjay K. Charagulla ,  Ali Burney

    IPC分类号： H03K19/173

    CPC分类号： H03K19/17744

    摘要： A programmable device I/O architecture allows for a variable number of I/O banks. Each I/O bank is of an I/O bank type. Each I/O bank type has a fixed number of I/O pins. I/O banks of the same I/O bank type are compatible within the same programmable device and between different types of programmable devices. The largest size I/O bank type and intermediate size I/O bank types are adapted to be a compatible supersets of every smaller I/O bank type. Support pins are regularly distributed between data pins in each I/O bank type. Multiple instances of the same or compatible I/O banks are arranged to be accessible from different sides of the programmable device. To facilitate circuit board layout, each I/O bank is arranged as a mirror and/or rotation of other I/O banks on the device.

    摘要翻译： 可编程器件I / O架构允许可变数量的I / O bank。 每个I / O bank都是I / O bank类型。 每个I / O bank类型都有固定数量的I / O引脚。 相同I / O bank类型的I / O组在同一可编程器件内和不同类型的可编程器件之间兼容。 最大尺寸的I / O库类型和中等大小的I / O库类型适合于每个更小的I / O bank类型的兼容超集。 支持引脚定期分布在每个I / O bank类型的数据引脚之间。 相同或兼容的I / O组的多个实例被布置为可从可编程设备的不同侧面访问。 为了便于电路板布局，每个I / O组被布置为设备上的其他I / O组的镜像和/或旋转。

    MODULAR I/O BANK ARCHITECTURE
    4.
    发明申请
    MODULAR I/O BANK ARCHITECTURE 有权
    模块化I / O银行架构

    公开(公告)号：US20070165478A1

    公开(公告)日：2007-07-19

    申请号：US11558363

    申请日：2006-11-09

    申请人： Jeffrey Tyhach ,  Chiakang Sung ,  Khai Nguyen ,  Sanjay K. Charagulla ,  Ali Burney

    发明人： Jeffrey Tyhach ,  Chiakang Sung ,  Khai Nguyen ,  Sanjay K. Charagulla ,  Ali Burney

    IPC分类号： G11C8/00

    CPC分类号： H03K19/17744

    摘要： A programmable device I/O architecture allows for a variable number of I/O banks. Each I/O bank is of an I/O bank type. Each I/O bank type has a fixed number of I/O pins. I/O banks of the same I/O bank type are compatible within the same programmable device and between different types of programmable devices. The largest size I/O bank type and intermediate size I/O bank types are adapted to be a compatible supersets of every smaller I/O bank type. Support pins are regularly distributed between data pins in each I/O bank type. Multiple instances of the same or compatible I/O banks are arranged to be accessible from different sides of the programmable device. To facilitate circuit board layout, each I/O bank is arranged as a mirror and/or rotation of other I/O banks on the device.

    摘要翻译： 可编程器件I / O架构允许可变数量的I / O bank。 每个I / O bank都是I / O bank类型。 每个I / O bank类型都有固定数量的I / O引脚。 相同I / O bank类型的I / O组在同一可编程器件内和不同类型的可编程器件之间兼容。 最大尺寸的I / O库类型和中等大小的I / O库类型适合于每个更小的I / O bank类型的兼容超集。 支持引脚定期分布在每个I / O bank类型的数据引脚之间。 相同或兼容的I / O组的多个实例被布置为可从可编程设备的不同侧面访问。 为了便于电路板布局，每个I / O组被布置为设备上的其他I / O组的镜像和/或旋转。

    Programmable high speed interface
    7.
    发明申请
    Programmable high speed interface 有权
    可编程高速接口

    公开(公告)号：US20060220703A1

    公开(公告)日：2006-10-05

    申请号：US11446483

    申请日：2006-06-02

    申请人： Bonnie Wang ,  Chiakang Sung ,  Joseph Huang ,  Khai Nguyen ,  Philip Pan

    发明人： Bonnie Wang ,  Chiakang Sung ,  Joseph Huang ,  Khai Nguyen ,  Philip Pan

    IPC分类号： H03B1/00

    CPC分类号： H03K19/17744 ,  H03K19/0175 ,  H03K19/017509 ,  H03K19/017581 ,  H03K19/1774 ,  H03K19/17788

    摘要： Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.

    摘要翻译： 提供高速或低速灵活的输入和输出的方法和设备。 提供具有高速输入，高速输出，低速或中速输入以及低速或中速输出的输入和输出结构。 选择其中一个输入和输出电路，并取消选择其他电路。 高速输入和输出电路相对简单，在一个示例中，仅具有用于控制线输入的清除信号，并且能够与集成电路的核心内的低速电路接口。 低速或中速输入和输出电路比较灵活，例如具有预置，使能和清除作为控制线路输入，并且能够支持JTAG边界测试。 这些并行高速和低速电路是用户可选择的，使得输入输出结构根据应用的要求在速度和功能之间进行优化。

    On/off reference voltage switch for multiple I/O standards
    9.
    发明授权
    On/off reference voltage switch for multiple I/O standards 有权
    用于多个I / O标准的开/关参考电压开关

    公开(公告)号：US06911860B1

    公开(公告)日：2005-06-28

    申请号：US10037716

    申请日：2001-11-09

    申请人： Xiaobao Wang ,  Chiakang Sung ,  Khai Nguyen ,  Joseph Huang ,  Bonnie Wang ,  Philip Pan ,  Yan Chong ,  In Whan Kim ,  Gopinath Rangan ,  Tzung-Chin Chang

    发明人： Xiaobao Wang ,  Chiakang Sung ,  Khai Nguyen ,  Joseph Huang ,  Bonnie Wang ,  Philip Pan ,  Yan Chong ,  In Whan Kim ,  Gopinath Rangan ,  Tzung-Chin Chang

    IPC分类号： H03K17/35

    CPC分类号： H03K17/6871 ,  H03K3/356113 ,  H03K17/063

    摘要： A switch circuit selectively provides a reference voltage, needed in some I/O standards, to a logic device. The circuit receives a dedicated power supply that is different from the device's I/O supply. It may also include a level shifting circuit for converting a master control signal having a logic level determined by a first supply to a first control signal having a logic level determined by the dedicated supply. The switch circuit also includes a transmission switch that passes the reference voltage to an output in response to at least the first control signal. The transmission switch may be a CMOS transmission gate with at least one NMOS transistor controlled by the first control signal in parallel with at least one PMOS transistor controlled by a second control signal, complementary to the first. The second control signal may be generated by another level shifting circuit and have a logic level determined by the I/O supply.

    摘要翻译： 开关电路选择性地将某些I / O标准所需的参考电压提供给逻辑器件。 该电路接收与设备的I / O电源不同的专用电源。 其还可以包括电平移位电路，用于将具有由第一电源确定的逻辑电平的主控制信号转换成具有由专用电源确定的逻辑电平的第一控制信号。 开关电路还包括传输开关，其响应于至少第一控制信号将参考电压传递到输出。 传输开关可以是CMOS传输门，其中至少一个NMOS晶体管由第一控制信号控制，与由与第一控制信号互补的第二控制信号控制的至少一个PMOS晶体管并联。 第二控制信号可以由另一电平移位电路产生并具有由I / O电源确定的逻辑电平。

    Programmable high speed I/O interface
    10.
    发明申请
    Programmable high speed I/O interface 有权
    可编程高速I / O接口

    公开(公告)号：US20050134332A1

    公开(公告)日：2005-06-23

    申请号：US10886015

    申请日：2004-07-06

    申请人： Bonnie Wang ,  Chiakang Sung ,  Joseph Huang ,  Khai Nguyen ,  Philip Pan

    发明人： Bonnie Wang ,  Chiakang Sung ,  Joseph Huang ,  Khai Nguyen ,  Philip Pan

    IPC分类号： G06F3/00 ,  G06F13/38 ,  H03K19/0175 ,  H03K19/173 ,  H03K19/177 ,  H03K17/16

    CPC分类号： H03K19/17744 ,  H03K19/0175 ,  H03K19/017509 ,  H03K19/017581 ,  H03K19/1774 ,  H03K19/17788

    摘要： Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.

    摘要翻译： 提供高速或低速灵活的输入和输出的方法和设备。 提供具有高速输入，高速输出，低速或中速输入以及低速或中速输出的输入和输出结构。 选择其中一个输入和输出电路，并取消选择其他电路。 高速输入和输出电路相对简单，在一个示例中，仅具有用于控制线输入的清除信号，并且能够与集成电路的核心内的低速电路接口。 低速或中速输入和输出电路比较灵活，例如具有预置，使能和清除作为控制线路输入，并且能够支持JTAG边界测试。 这些并行高速和低速电路是用户可选择的，使得输入输出结构根据应用的要求在速度和功能之间进行优化。