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公开(公告)号：US20110087343A1
公开(公告)日：2011-04-14
申请号：US12791163
申请日：2010-06-01
申请人： Jeffry K. Kamenetz , Gregory DiVincenzo , Mark A. Johnston , Jay W. Kokas , Luke T. Orsini , Steven R. Fischer , Jay H. Hartman , Kevin P. Roy , William Betterini
发明人： Jeffry K. Kamenetz , Gregory DiVincenzo , Mark A. Johnston , Jay W. Kokas , Luke T. Orsini , Steven R. Fischer , Jay H. Hartman , Kevin P. Roy , William Betterini
IPC分类号： G05B9/03
CPC分类号： G06F11/0796 , G05B19/0428 , G05B2219/25471 , G06F11/2028
摘要： An electronic control configuration includes at least one secondary microprocessor operable to control a device. The at least one secondary microprocessor assumes protection control of the device responsive to a first type of failure by transmitting a protection control signal to a first effector. The at least one secondary microprocessor assumes backup control of the device responsive to a second type of failure by transmitting a backup control signal to a second effector. The backup control functionality of the at least one secondary microprocessor can be selectively disabled.
摘要翻译： 电子控制配置包括可操作以控制设备的至少一个二次微处理器。 所述至少一个次要微处理器通过将保护控制信号发送到第一执行器来假定对所述设备的保护控制，所述设备响应于第一类型的故障。 所述至少一个次级微处理器通过将备用控制信号发送到第二执行器来假定设备对第二类型故障的备份控制。 可以选择性地禁用至少一个次要微处理器的备用控制功能。
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公开(公告)号：US08340793B2
公开(公告)日：2012-12-25
申请号：US12791163
申请日：2010-06-01
申请人： Jeffry K. Kamenetz , Gregory DiVincenzo , Mark A. Johnston , Jay W. Kokas , Luke T. Orsini , Steven R. Fischer , Jay H. Hartman , Kevin P. Roy , William Betterini
发明人： Jeffry K. Kamenetz , Gregory DiVincenzo , Mark A. Johnston , Jay W. Kokas , Luke T. Orsini , Steven R. Fischer , Jay H. Hartman , Kevin P. Roy , William Betterini
CPC分类号： G06F11/0796 , G05B19/0428 , G05B2219/25471 , G06F11/2028
摘要： An electronic control configuration includes at least one secondary microprocessor operable to control a device. The at least one secondary microprocessor assumes protection control of the device responsive to a first type of failure by transmitting a protection control signal to a first effector. The at least one secondary microprocessor assumes backup control of the device responsive to a second type of failure by transmitting a backup control signal to a second effector. The backup control functionality of the at least one secondary microprocessor can be selectively disabled.
摘要翻译： 电子控制配置包括可操作以控制设备的至少一个二次微处理器。 所述至少一个次要微处理器通过将保护控制信号发送到第一执行器来假定对所述设备的保护控制，所述设备响应于第一类型的故障。 所述至少一个次级微处理器通过将备用控制信号发送到第二执行器来假定设备对第二类型故障的备份控制。 可以选择性地禁用至少一个次要微处理器的备用控制功能。
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公开(公告)号：US20100263900A1
公开(公告)日：2010-10-21
申请号：US12631358
申请日：2009-12-04
CPC分类号： H05K5/0247 , Y10T29/49002
摘要： A Full Authority Digital Controller (FADEC) has a stamped housing body, a FADEC circuit assembly within the housing body, and a cover. An electrical connector is mounted to the housing body.
摘要翻译： 全权限数字控制器（FADEC）具有冲压的壳体，壳体内的FADEC电路组件和盖。 电连接器安装到壳体上。
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公开(公告)号：US08536821B2
公开(公告)日：2013-09-17
申请号：US13239486
申请日：2011-09-22
CPC分类号： H02P8/36
摘要： A multi-channel stepper motor controller has at least a first and second stepper motor control channel. Each of the control channels has a solid state switching circuit operable to connect the control channel to a stepper motor.
摘要翻译： 多通道步进电机控制器至少具有第一和第二步进电机控制通道。 每个控制通道具有可操作以将控制通道连接到步进电机的固态切换电路。
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公开(公告)号：US20130076291A1
公开(公告)日：2013-03-28
申请号：US13239486
申请日：2011-09-22
IPC分类号： H02P8/36
CPC分类号： H02P8/36
摘要： A multi-channel stepper motor controller has at least a first and second stepper motor control channel. Each of the control channels has a solid state switching circuit operable to connect the control channel to a stepper motor.
摘要翻译： 多通道步进电机控制器至少具有第一和第二步进电机控制通道。 每个控制通道具有可操作以将控制通道连接到步进电机的固态切换电路。
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公开(公告)号：US20130079894A1
公开(公告)日：2013-03-28
申请号：US13239708
申请日：2011-09-22
CPC分类号： G05B9/03 , F01D21/02 , F02C9/46 , F02D41/22 , F02D41/266 , F02D41/28 , F02D2200/101 , F02D2400/08 , F05D2270/021
摘要： A multi-channel controller uses multiple logic gates and multiple control channels to provide fault tolerant protection against undesired events.
摘要翻译： 多通道控制器使用多个逻辑门和多个控制通道来提供针对不期望事件的容错保护。
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公开(公告)号：US20130079902A1
公开(公告)日：2013-03-28
申请号：US13239791
申请日：2011-09-22
申请人： Jeffry K. Kamenetz , Mark A. Johnston , Edward John Marotta , Cathleen R. Bleier , John M. O'Neil
发明人： Jeffry K. Kamenetz , Mark A. Johnston , Edward John Marotta , Cathleen R. Bleier , John M. O'Neil
IPC分类号： G05B9/03
CPC分类号： G05B19/0421 , G05B19/0428 , G05B2219/14014 , G05B2219/24177 , G05B2219/24183 , G05B2219/24186 , G06F11/2033 , G06F11/2041
摘要： A multi-channel control system includes at least a first primary control microprocessor and a second primary control microprocessor operable to control a device, and at least a first secondary control microprocessor and a second secondary control microprocessor operable to control the device. Each of the first and second primary control microprocessors and the first and second secondary control microprocessors are arranged as an independent control channel.
摘要翻译： 多通道控制系统至少包括可操作以控制设备的第一主控微处理器和第二主控微处理器，以及可操作以控制设备的至少第一副控制微处理器和第二副控微处理器。 第一和第二主要控制微处理器以及第一和第二次级控制微处理器中的每一个被布置为独立的控制通道。
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公开(公告)号：US09483032B2
公开(公告)日：2016-11-01
申请号：US13239708
申请日：2011-09-22
CPC分类号： G05B9/03 , F01D21/02 , F02C9/46 , F02D41/22 , F02D41/266 , F02D41/28 , F02D2200/101 , F02D2400/08 , F05D2270/021
摘要： A multi-channel controller uses multiple logic gates and multiple control channels to provide fault tolerant protection against undesired events.
摘要翻译： 多通道控制器使用多个逻辑门和多个控制通道来提供针对不期望事件的容错保护。
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公开(公告)号：US09625894B2
公开(公告)日：2017-04-18
申请号：US13239791
申请日：2011-09-22
申请人： Jeffry K. Kamenetz , Mark A. Johnston , Edward John Marotta , Cathleen R. Bleier , John M. O'Neil
发明人： Jeffry K. Kamenetz , Mark A. Johnston , Edward John Marotta , Cathleen R. Bleier , John M. O'Neil
CPC分类号： G05B19/0421 , G05B19/0428 , G05B2219/14014 , G05B2219/24177 , G05B2219/24183 , G05B2219/24186 , G06F11/2033 , G06F11/2041
摘要： A multi-channel control system includes a first primary control microprocessor and a second primary control microprocessor operable to control a device, and a first secondary control microprocessor and a second secondary control microprocessor operable to control the device. Each of the first and second primary control microprocessors and the first and second secondary control microprocessors are arranged as an independent control channel.
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公开(公告)号：US4845617A
公开(公告)日：1989-07-04
申请号：US57069
申请日：1987-06-01
CPC分类号： G05D1/0072 , B64D31/10
摘要： Each engine of a multi-engine aircraft is monitored to determine if it has become inoperative during a critical flight mode such as takeoff or landing. If so, the propeller of the inoperative engine is feathered and the remaining engine or engines is uptrimmed. A "state machine" indicative of the various states of the aircraft is established and the present state of the aircraft is stored in a non-volatile memory; if an electrical power interruption occurs during a critical flight mode the identity of the present operating state may be quickly recalled for immediate refeathering of an inoperative engine and reuptrimming of the remaining engine or engines.
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