公开(公告)号：US08238107B2

公开(公告)日：2012-08-07

申请号：US12713309

申请日：2010-02-26

申请人： Jen-Chuan Yeh ,  Kuo-Ting Lee

发明人： Jen-Chuan Yeh ,  Kuo-Ting Lee

IPC分类号： H01R4/22

CPC分类号： B81C1/00269 ,  B81C1/00888

摘要： A cap for a MEMS package includes a main body having a bottom surface, a top surface, a plurality of accommodations recessed from the bottom surface towards the top surface, and a plurality of slots recessed from the top surface towards the bottom surface in a way that the top surface is defined into a plurality of regions corresponding to the accommodations respectively. After completion of the MEMS package, the package can be cut along the slots into a plurality of MEMS package units, such that the cutting work can be done quickly and the cutting burrs can be minimized.

摘要翻译： 一种用于MEMS封装的盖包括具有底表面的主体，顶表面，从底表面朝向顶表面凹进的多个托架以及以顶部表面向底表面凹陷的多个槽 顶表面分别被定义成对应于住宿的多个区域。 在MEMS封装完成之后，封装可以沿着狭槽切割成多个MEMS封装单元，使得可以快速地进行切割加工，并且能够使切割毛刺最小化。

公开(公告)号：US20110293119A1

公开(公告)日：2011-12-01

申请号：US12855861

申请日：2010-08-13

申请人： Jen-Chuan YEH ,  Jyong-Yue Tian ,  Kuo-Ting Lee

发明人： Jen-Chuan YEH ,  Jyong-Yue Tian ,  Kuo-Ting Lee

IPC分类号： H04R25/00

CPC分类号： H04R19/005

摘要： An MEM microphone carrier module is composed of a substrate and a cover plate. The substrate includes a space layer, a bottom layer, a recession recessed from a top side of the space layer, and a groove formed in the recession. The bottom layer has a metallic plate defining a predetermined pattern and exposed outside a surface thereof. The bottom layer is a single-layer structure formed by the molding of the metallic plate and the insulating glue, such that the substrate is thinner to need lower production cost and take less assembly time than the prior art.

摘要翻译： MEM麦克风载体模块由基板和盖板组成。 基板包括空间层，底层，从空间层的顶侧凹陷的凹部和在凹部中形成的凹槽。 底层具有限定预定图案的金属板并暴露在其表面之外。 底层是通过金属板和绝缘胶的模制而形成的单层结构，使得基底更薄以减少生产成本并且比现有技术花费更少的装配时间。

公开(公告)号：US08254619B2

公开(公告)日：2012-08-28

申请号：US12855861

申请日：2010-08-13

申请人： Jen-Chuan Yeh ,  Jyong-Yue Tian ,  Kuo-Ting Lee

发明人： Jen-Chuan Yeh ,  Jyong-Yue Tian ,  Kuo-Ting Lee

IPC分类号： H04R21/02

CPC分类号： H04R19/005

摘要： An MEM microphone carrier module is composed of a substrate and a cover plate. The substrate includes a space layer, a bottom layer, a recession recessed from a top side of the space layer, and a groove formed in the recession. The bottom layer has a metallic plate defining a predetermined pattern and exposed outside a surface thereof. The bottom layer is a single-layer structure formed by the molding of the metallic plate and the insulating glue, such that the substrate is thinner to need lower production cost and take less assembly time than the prior art.

摘要翻译： MEM麦克风载体模块由基板和盖板组成。 基板包括空间层，底层，从空间层的顶侧凹陷的凹部和在凹部中形成的凹槽。 底层具有限定预定图案的金属板并暴露在其表面之外。 底层是通过金属板和绝缘胶的模制而形成的单层结构，使得基底更薄以减少生产成本并且比现有技术花费更少的装配时间。

公开(公告)号：US20110174532A1

公开(公告)日：2011-07-21

申请号：US12713309

申请日：2010-02-26

申请人： Jen-Chuan YEH ,  Kuo-Ting Lee

发明人： Jen-Chuan YEH ,  Kuo-Ting Lee

IPC分类号： H05K5/00

CPC分类号： B81C1/00269 ,  B81C1/00888

摘要： A cap for a MEMS package includes a main body having a bottom surface, a top surface, a plurality of accommodations recessed from the bottom surface towards the top surface, and a plurality of slots recessed from the top surface towards the bottom surface in a way that the top surface is defined into a plurality of regions corresponding to the accommodations respectively. After completion of the MEMS package, the package can be cut along the slots into a plurality of MEMS package units, such that the cutting work can be done quickly and the cutting burrs can be minimized.

摘要翻译： 一种用于MEMS封装的盖包括具有底表面的主体，顶表面，从底表面朝向顶表面凹进的多个托架以及以顶部表面向底表面凹陷的多个槽 顶表面分别被定义成对应于住宿的多个区域。 在MEMS封装完成之后，封装可以沿着狭槽切割成多个MEMS封装单元，使得可以快速地进行切割加工，并且能够使切割毛刺最小化。

公开(公告)号：US07247909B2

公开(公告)日：2007-07-24

申请号：US11271933

申请日：2005-11-10

申请人： Fu-Hsin Chen ,  Wen-Hua Huang ,  Kuo-Ting Lee ,  You-Kuo Wu ,  An-Min Chiang

发明人： Fu-Hsin Chen ,  Wen-Hua Huang ,  Kuo-Ting Lee ,  You-Kuo Wu ,  An-Min Chiang

IPC分类号： H01L29/76 ,  H01L21/8234

CPC分类号： H01L21/823418 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823481

摘要： A method is disclosed for integrally forming at least one low voltage device and at least one high voltage device. According to the method, a first gate structure and a second gate structure are formed on a semiconductor substrate, wherein the first and second gate structures are isolated from one another. One or more first double diffused regions are formed adjacent to the first gate structure in the semiconductor substrate. One or more second double diffused regions are formed adjacent to the second gate structure in the semiconductor substrate. One or more first source/drain regions are formed within the first double diffused regions. One or more second source/drain regions are formed within the second double diffused regions. The first double diffused regions function as one or more lightly doped source/drain regions for the low voltage device.

摘要翻译： 公开了一种用于整体形成至少一个低压装置和至少一个高压装置的方法。 根据该方法，在半导体衬底上形成第一栅极结构和第二栅极结构，其中第一和第二栅极结构彼此隔离。 一个或多个第一双扩散区域形成在半导体衬底中与第一栅极结构相邻。 在半导体衬底中形成与第二栅极结构相邻的一个或多个第二双扩散区。 在第一双扩散区域内形成一个或多个第一源极/漏极区域。 在第二双扩散区域内形成一个或多个第二源极/漏极区域。 第一双扩散区域用作低电压器件的一个或多个轻掺杂源极/漏极区域。

公开(公告)号：US20070108602A1

公开(公告)日：2007-05-17

申请号：US11280888

申请日：2005-11-16

申请人： Kuo-Ting Lee ,  You-Kuo Wu ,  Fu-Hsin Chen ,  An-Ming Chiang

发明人： Kuo-Ting Lee ,  You-Kuo Wu ,  Fu-Hsin Chen ,  An-Ming Chiang

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L21/761 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/66568 ,  H01L29/7833

摘要： The present invention discloses a semiconductor structure. A buried layer of a first polarity type is constructed on a semiconductor substrate. A first epitaxial layer of a second polarity type is formed on the buried layer. A second epitaxial layer of the second polarity type is formed on the buried layer. An isolation structure of the first polarity type is formed between the first and second epitaxial layers on the buried layer. A first well of the second polarity type is formed on the first epitaxial layer. A second well of the second polarity type is formed on the second epitaxial layer. A third well of the first polarity type is formed between the first and second wells, on the isolation structure. The isolation structure interfaces with the buried layer and the third well, thereby substantially blocking a leakage current path between the first and the second wells.

摘要翻译： 本发明公开了一种半导体结构。 第一极性类型的掩埋层构造在半导体衬底上。 在掩埋层上形成第二极性类型的第一外延层。 第二极性类型的第二外延层形成在掩埋层上。 在掩埋层上的第一和第二外延层之间形成第一极性类型的隔离结构。 在第一外延层上形成第二极性类型的第一阱。 在第二外延层上形成第二极性类型的第二阱。 第一极性类型的第三阱形成在隔离结构上的第一和第二阱之间。 隔离结构与埋层和第三阱接口，从而基本上阻挡第一和第二阱之间的漏电流路径。

公开(公告)号：US20060278631A1

公开(公告)日：2006-12-14

申请号：US11150816

申请日：2005-06-10

申请人： Kuo-Ting Lee ,  Chien-Hung Lee ,  Chung-Hua Hu ,  Chien-Yuan Chen

发明人： Kuo-Ting Lee ,  Chien-Hung Lee ,  Chung-Hua Hu ,  Chien-Yuan Chen

IPC分类号： H05B3/34

CPC分类号： H05B3/342 ,  H05B2203/003 ,  H05B2203/004 ,  H05B2203/005 ,  H05B2203/011 ,  H05B2203/017 ,  H05B2203/021 ,  H05B2203/026 ,  H05B2203/029 ,  H05B2203/036

摘要： A laminate fabric heater includes a heating element having a conductive fabric layer patterned to define an electrical circuit having first and second ends and an adhesive layer adhered to a first side of the conductive fabric layer. First and second electrical leads are electrically coupled to the conductive fabric layer at the first and second ends, respectively, and first and second protective layers are disposed on opposing sides of the heating element to form a laminate with the heating element. The heating element is preferably sandwiched between the first and second protective layers so that only the first and second electrical leads extend from the resulting laminate. The first and second ends each preferably include an area of reduced resistivity extending across the width of the electrical circuit and formed from an application of conductive glue. Methods of manufacturing laminate fabric heaters are also provided.

摘要翻译： 层压织物加热器包括加热元件，该加热元件具有图案化的导电织物层，以限定具有第一和第二端的电路以及粘附到导电织物层的第一侧的粘合剂层。 第一和第二电引线分别在第一和第二端电耦合到导电织物层，并且第一和第二保护层设置在加热元件的相对侧上以与加热元件形成层压体。 加热元件优选地夹在第一和第二保护层之间，使得仅第一和第二电引线从所得到的层压体延伸。 第一和第二端各自优选地包括延伸穿过电路的宽度并由导电胶施加而形成的电阻降低的区域。 还提供了制造层压织物加热器的方法。

公开(公告)号：US07868422B2

公开(公告)日：2011-01-11

申请号：US11280888

申请日：2005-11-16

申请人： Kuo-Ting Lee ,  You-Kuo Wu ,  Fu-Hsin Chen ,  An-Ming Chiang

发明人： Kuo-Ting Lee ,  You-Kuo Wu ,  Fu-Hsin Chen ,  An-Ming Chiang

IPC分类号： H01L29/06

CPC分类号： H01L21/761 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/66568 ,  H01L29/7833

摘要： The present invention discloses a semiconductor structure. A buried layer of a first polarity type is constructed on a semiconductor substrate. A first epitaxial layer of a second polarity type is formed on the buried layer. A second epitaxial layer of the second polarity type is formed on the buried layer. An isolation structure of the first polarity type is formed between the first and second epitaxial layers on the buried layer. A first well of the second polarity type is formed on the first epitaxial layer. A second well of the second polarity type is formed on the second epitaxial layer. A third well of the first polarity type is formed between the first and second wells, on the isolation structure. The isolation structure interfaces with the buried layer and the third well, thereby substantially blocking a leakage current path between the first and the second wells.

摘要翻译： 本发明公开了一种半导体结构。 第一极性类型的掩埋层构造在半导体衬底上。 在掩埋层上形成第二极性类型的第一外延层。 第二极性类型的第二外延层形成在掩埋层上。 在掩埋层上的第一和第二外延层之间形成第一极性类型的隔离结构。 在第一外延层上形成第二极性类型的第一阱。 在第二外延层上形成第二极性类型的第二阱。 第一极性类型的第三阱形成在隔离结构上的第一和第二阱之间。 隔离结构与埋层和第三阱接口，从而基本上阻挡第一和第二阱之间的漏电流路径。

公开(公告)号：US20100189627A1

公开(公告)日：2010-07-29

申请号：US12360414

申请日：2009-01-27

申请人： Chung-Hua Hu ,  Kuo-Ting Lee

发明人： Chung-Hua Hu ,  Kuo-Ting Lee

IPC分类号： C01B31/02 ,  B01J19/00

CPC分类号： D01F9/32 ,  C01B32/05

摘要： A continuous negative pressure carbonization apparatus includes a material feeding device, a carbonizing chamber and a material collecting device. The material feeding device feeds the raw material. The carbonizing chamber receives and carbonizes the raw material and it includes a carbonization device and two buffering devices. The carbonization device has a carbonization chamber. The carbonization chamber has a material inlet and a material outlet. The buffering devices are respectively mounted and connected to the material inlet and the material outlet. The material collecting device collects the carbonized product from the carbonization chamber. When the raw material is carbonized in the carbonization chamber, the pressure of the carbonization chamber is kept at a negative pressure state smaller than the atmospheric pressure.

摘要翻译： 连续负压碳化装置包括供料装置，碳化室和材料收集装置。 送料装置送料原料。 碳化室容纳碳化原料，包括碳化装置和两个缓冲装置。 碳化装置具有碳化室。 碳化室具有材料入口和材料出口。 缓冲装置分别安装并连接到材料入口和材料出口。 材料收集装置从碳化室收集碳化产物。 当原料在碳化室中碳化时，碳化室的压力保持在小于大气压的负压状态。

公开(公告)号：US20070102759A1

公开(公告)日：2007-05-10

申请号：US11271933

申请日：2005-11-10

申请人： Fu-Hsin Chen ,  Wen-Hua Huang ,  Kuo-Ting Lee ,  You-Kuo Wu ,  An-Ming Chiang

发明人： Fu-Hsin Chen ,  Wen-Hua Huang ,  Kuo-Ting Lee ,  You-Kuo Wu ,  An-Ming Chiang

IPC分类号： H01L21/336 ,  H01L29/76

CPC分类号： H01L21/823418 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823481

摘要： A method is disclosed for integrally forming at least one low voltage device and at least one high voltage device. According to the method, a first gate structure and a second gate structure are formed on a semiconductor substrate, wherein the first and second gate structures are isolated from one another. One or more first double diffused regions are formed adjacent to the first gate structure in the semiconductor substrate. One or more second double diffused regions are formed adjacent to the second gate structure in the semiconductor substrate. One or more first source/drain regions are formed within the first double diffused regions. One or more second source/drain regions are formed within the second double diffused regions. The first double diffused regions function as one or more lightly doped source/drain regions for the low voltage device.