公开(公告)号：US07247909B2

公开(公告)日：2007-07-24

申请号：US11271933

申请日：2005-11-10

申请人： Fu-Hsin Chen ,  Wen-Hua Huang ,  Kuo-Ting Lee ,  You-Kuo Wu ,  An-Min Chiang

发明人： Fu-Hsin Chen ,  Wen-Hua Huang ,  Kuo-Ting Lee ,  You-Kuo Wu ,  An-Min Chiang

IPC分类号： H01L29/76 ,  H01L21/8234

CPC分类号： H01L21/823418 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823481

摘要： A method is disclosed for integrally forming at least one low voltage device and at least one high voltage device. According to the method, a first gate structure and a second gate structure are formed on a semiconductor substrate, wherein the first and second gate structures are isolated from one another. One or more first double diffused regions are formed adjacent to the first gate structure in the semiconductor substrate. One or more second double diffused regions are formed adjacent to the second gate structure in the semiconductor substrate. One or more first source/drain regions are formed within the first double diffused regions. One or more second source/drain regions are formed within the second double diffused regions. The first double diffused regions function as one or more lightly doped source/drain regions for the low voltage device.

摘要翻译： 公开了一种用于整体形成至少一个低压装置和至少一个高压装置的方法。 根据该方法，在半导体衬底上形成第一栅极结构和第二栅极结构，其中第一和第二栅极结构彼此隔离。 一个或多个第一双扩散区域形成在半导体衬底中与第一栅极结构相邻。 在半导体衬底中形成与第二栅极结构相邻的一个或多个第二双扩散区。 在第一双扩散区域内形成一个或多个第一源极/漏极区域。 在第二双扩散区域内形成一个或多个第二源极/漏极区域。 第一双扩散区域用作低电压器件的一个或多个轻掺杂源极/漏极区域。

公开(公告)号：US20070108517A1

公开(公告)日：2007-05-17

申请号：US11273222

申请日：2005-11-12

申请人： You-Kuo Wu ,  Fu-Hsin Chen ,  P.Y. Chiang ,  An-Min Chiang

发明人： You-Kuo Wu ,  Fu-Hsin Chen ,  P.Y. Chiang ,  An-Min Chiang

IPC分类号： H01L29/76

CPC分类号： H01L29/7816 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/42356

摘要： A power metal-oxide semiconductor device provides an P-type base region that includes the N+ device source and is biased differently than the P-type substrate by application of an electrical load. In one embodiment, an LDMOS device with a NPN configuration is used but the coupling of the device source to the base contact prevents the NPN parasitic device from operating. The P-type base is formed in an N-well that separates the base from the P-type substrate and surrounding P-wells. Vertical punch-through is prevented by a high-impurity N+ buried layer that separates the N-well from the P-type substrate.

摘要翻译： 功率金属氧化物半导体器件提供包括N +器件源的P型基极区域，并且通过施加电负载而不同于P型衬底的偏置。 在一个实施例中，使用具有NPN配置的LDMOS器件，但是器件源与基极接触的耦合防止了NPN寄生器件的工作。 P型基底形成在将P基底和P型基底分隔开的N阱中。 通过将N阱与P型衬底分离的高杂质N +掩埋层防止垂直穿通。

公开(公告)号：US20060157816A1

公开(公告)日：2006-07-20

申请号：US11331442

申请日：2006-01-12

申请人： You-Kuo Wu ,  An-Min Chiang ,  Shun-Liang Hsu

发明人： You-Kuo Wu ,  An-Min Chiang ,  Shun-Liang Hsu

IPC分类号： H01L21/76 ,  H01L29/00

CPC分类号： H01L21/76218

摘要： A semiconductor device. The semiconductor device comprises an isolation structure and two heavily doped regions of a second conductivity type spaced apart from each other by the isolation structure. The isolation structure comprises an isolation region in a semiconductor substrate and a heavily doped region of the first conductivity type. The isolation region has an opening and the heavily doped region of the first conductivity type is substantially surrounded by the opening of the isolation region.

摘要翻译： 半导体器件。 半导体器件包括隔离结构和通过隔离结构彼此隔开的第二导电类型的两个重掺杂区域。 隔离结构包括半导体衬底中的隔离区和第一导电类型的重掺杂区。 隔离区域具有开口，并且第一导电类型的重掺杂区域基本上被隔离区域的开口包围。

公开(公告)号：US07911022B2

公开(公告)日：2011-03-22

申请号：US11331442

申请日：2006-01-12

申请人： You-Kuo Wu ,  An-Min Chiang ,  Shun-Liang Hsu

发明人： You-Kuo Wu ,  An-Min Chiang ,  Shun-Liang Hsu

IPC分类号： H01L21/70

CPC分类号： H01L21/76218

摘要： A semiconductor device. The semiconductor device comprises an isolation structure and two heavily doped regions of a second conductivity type spaced apart from each other by the isolation structure. The isolation structure comprises an isolation region in a semiconductor substrate and a heavily doped region of the first conductivity type. The isolation region has an opening and the heavily doped region of the first conductivity type is substantially surrounded by the opening of the isolation region.

摘要翻译： 半导体器件。 半导体器件包括隔离结构和通过隔离结构彼此隔开的第二导电类型的两个重掺杂区域。 隔离结构包括半导体衬底中的隔离区和第一导电类型的重掺杂区。 隔离区域具有开口，并且第一导电类型的重掺杂区域基本上被隔离区域的开口包围。

公开(公告)号：US5915178A

公开(公告)日：1999-06-22

申请号：US986531

申请日：1997-12-08

申请人： An-Min Chiang ,  Long-Shang Juang ,  Chi-Shiang Lee ,  Jyh-Feng Lin

发明人： An-Min Chiang ,  Long-Shang Juang ,  Chi-Shiang Lee ,  Jyh-Feng Lin

IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L29/788 ,  H01L21/8247

CPC分类号： H01L29/66825 ,  H01L29/42324 ,  H01L29/7883

摘要： A process for fabricating a flash EEPROM device, incorporating a shallow, heavily doped, source side region, used to improve the endurance of the flash EEPROM device, has been developed. The process features placing a shallow, ion implanted arsenic region, in the semiconductor substrate, adjacent to one side of a floating gate structure, prior to creation of the control gate structure. The addition of the shallow, ion implanted arsenic region, improves the coupling ratio at the source, which in turn results in the ability of the flash EEPROM device to sustain about 1,000,000 program/erase cycles, compared to counterparts, fabricated without the shallow, source side region, only able to sustain about 400,000 program/erase cycles.

摘要翻译： 已经开发了用于制造闪速EEPROM装置的方法，其包括用于提高快速EEPROM装置的耐久性的浅重掺杂的源极侧区域。 该方法在创建控制栅极结构之前，在与半导体衬底中相邻的浮栅结构的一侧放置浅的离子注入的砷区。 添加浅离子注入的砷区域可以提高源极耦合比，从而与快速EEPROM器件相比，快速EEPROM器件能够维持大约1,000,000个编程/擦除周期，与没有浅源的器件相比， 侧面区域，只能维持大约40万个编程/擦除周期。

公开(公告)号：US6159660A

公开(公告)日：2000-12-12

申请号：US794694

申请日：1997-02-03

申请人： Hsin-Pai Chen ,  An-Min Chiang ,  Pei-Hung Chen

发明人： Hsin-Pai Chen ,  An-Min Chiang ,  Pei-Hung Chen

IPC分类号： G03F7/20 ,  H01L21/027 ,  H01L21/3213 ,  G03F7/207

CPC分类号： G03F7/70425 ,  G03F7/20 ,  H01L21/0274 ,  H01L21/32139

摘要： A method of forming a number of closely spaced electrodes is described wherein covering the electrodes with a conformal layer of oxide or nitride deposited using plasma enhanced chemical vapor deposition does not result in the formation of restricted regions or keyholes between adjacent electrodes. The method uses de-focussing to form the electrode mask pattern in a layer of photoresist. The focal plane in which the electrode pattern is focussed is positioned a de-focus distance above the layer of photoresist. The de-focus method results in electrodes having a trapezoidal cross section wherein the bottom of the electrode is wider than the top of the electrode. The trapezoidal cross section avoids the formation of restricted regions or keyholes when the electrodes are covered with a conformal dielectric layer, such as a layer of oxide or nitride deposited using plasma enhanced chemical vapor deposition.

摘要翻译： 描述了形成多个紧密间隔的电极的方法，其中使用等离子体增强化学气相沉积沉积的氧化物或氮化物的保形层覆盖电极不会导致在相邻电极之间形成受限制的区域或键孔。 该方法使用去焦点在光致抗蚀剂层中形成电极掩模图案。 电极图案聚焦的焦平面位于光致抗蚀剂层之上的去焦距离。 脱焦方法导致具有梯形横截面的电极，其中电极的底部比电极的顶部宽。 梯形横截面避免了当电极覆盖有保形介质层（例如使用等离子体增强化学气相沉积沉积的氧化物或氮化物层）时形成限制区域或键孔。

公开(公告)号：US5811343A

公开(公告)日：1998-09-22

申请号：US683645

申请日：1996-07-15

申请人： Yeh-Jye Wann ,  An-Min Chiang ,  Shaun-Tsung Yu ,  Pei-Hung Chen

发明人： Yeh-Jye Wann ,  An-Min Chiang ,  Shaun-Tsung Yu ,  Pei-Hung Chen

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/265

CPC分类号： H01L29/66575 ,  H01L21/8234

摘要： A method for manufacturing integrated circuit semiconductor device is provided for doping polysilicon formed on an N-well in a semiconductor substrate. Form a silicon oxide layer on the N-well. Then form a blanket polysilicon layer over the silicon oxide layer and pattern the polysilicon layer into a structure. Form a sacrificial oxide layer over the polysilicon structure. Then ion implant .sup.49 (BF.sub.2).sup.+ ions into the N-well and the polysilicon layer forming the source/drain regions and doping the polysilicon layer with P-type dopant thereby forming a doped polysilicon layer from the polysilicon layer. Then etch the sacrificial oxide layer away from the device. Form a polyoxide layer over the polysilicon structure. Then form a silicon oxide layer over the polyoxide layer followed by forming a glass layer thereover.

摘要翻译： 提供一种用于制造集成电路半导体器件的方法，用于掺杂形成在半导体衬底中的N阱上的多晶硅。 在N阱上形成氧化硅层。 然后在氧化硅层上形成覆盖多晶硅层，并将多晶硅层图案化成结构。 在多晶硅结构上形成牺牲氧化层。 然后将离子注入49（BF 2）+离子注入N阱和形成源极/漏极区的多晶硅层，并用P型掺杂剂掺杂多晶硅层，从而从多晶硅层形成掺杂多晶硅层。 然后将牺牲氧化层蚀刻离开器件。 在多晶硅结构上形成多氧化物层。 然后在多氧化物层上形成氧化硅层，然后在其上形成玻璃层。

公开(公告)号：US06514785B1

公开(公告)日：2003-02-04

申请号：US09590125

申请日：2000-06-09

申请人： An-Min Chiang ,  Chi-Hsiang Lee ,  Wei-Kun Yeh ,  Hua-Yu Yang

发明人： An-Min Chiang ,  Chi-Hsiang Lee ,  Wei-Kun Yeh ,  Hua-Yu Yang

IPC分类号： H01L2100

CPC分类号： H01L27/14603

摘要： A method of forming an image sensor is disclosed. A partially processed semiconductor wafer is provide, containing p-type and/or n-type regions which are bounded by isolation regions and with gate oxide layers grown on the surfaces upon which gate electrode structures are disposed, some of said gate electrode structures will serve as gate electrodes of image sensor transistors. Ions are implanted to form source/drain structures about the said gate electrode structures. To form photodiodes ions are implanted in two steps overlapping a source/drain region. A deeper implant provides a low charge carrier density region and a shallow implant provides a high charge carrier density region near the surface. A blanket transparent insulating layer is deposited.

摘要翻译： 公开了一种形成图像传感器的方法。 提供部分处理的半导体晶片，其包含由隔离区域限定的p型和/或n型区域，并且在其上设置栅电极结构的表面上生长的栅极氧化物层，一些所述栅电极结构将用于 作为图像传感器晶体管的栅电极。 植入离子以形成围绕所述栅电极结构的源极/漏极结构。 为了形成光电二极管，以与源/漏区重叠的两个步骤注入离子。 较深的注入提供了低电荷载流子密度区域，浅的注入提供了表面附近的高电荷载流子密度区域。 沉积一层覆盖的透明绝缘层。

公开(公告)号：US06306678B1

公开(公告)日：2001-10-23

申请号：US09467122

申请日：1999-12-20

申请人： An-Min Chiang ,  Chi-Hsiang Lee ,  Wei-Kun Yeh ,  Hua-Yu Yang

发明人： An-Min Chiang ,  Chi-Hsiang Lee ,  Wei-Kun Yeh ,  Hua-Yu Yang

IPC分类号： H01L2100

CPC分类号： H01L27/14689 ,  H01L27/14609

摘要： A process of fabricating an image sensor cell, on a semiconductor substrate, with the image sensor cell exhibiting low dark current generation, and high signal to noise ratio, has been developed. The process features the use of a photoresist shape, used to protect a previously formed photodiode element, from an reactive ion etching procedure, used to define insulator spacers on the sides of a polysilicon gate structure, of a reset transistor structure This process sequence avoids damage to the surface of an N type component, of the photodiode element, resulting in the improved electrical characteristics, when compared to counterpart image sensor cells, in which the photodiode element was subjected to the insulator spacer definition procedure.

摘要翻译： 已经开发了在半导体衬底上制造具有低暗电流产生的图像传感器单元和高信噪比的图像传感器单元的工艺。 该方法的特征在于用于保护先前形成的光电二极管元件的光致抗蚀剂形状与用于限定多晶硅栅结构侧面上的绝缘体间隔物的反应离子蚀刻程序的复位晶体管结构的使用。该工艺顺序避免了损坏 与光电二极管元件经受绝缘体间隔物定义过程的对应图像传感器单元相比，到达光电二极管元件的N型部件的表面，导致改善的电特性。

公开(公告)号：US5753548A

公开(公告)日：1998-05-19

申请号：US719234

申请日：1996-09-24

申请人： Shau-Tsung Yu ,  An-Min Chiang ,  Yeh-Jye Wann ,  Pei-Hung Chen

发明人： Shau-Tsung Yu ,  An-Min Chiang ,  Yeh-Jye Wann ,  Pei-Hung Chen

IPC分类号： H01L21/8238

CPC分类号： H01L21/823814

摘要： A method is described for forming P-channel field effect transistors having shallow source/drain junctions and improved reliability for CMOS circuits. The method involves forming both N-channel and P-channel FETs by alternate photoresist masking and ion implantation. The shallow junction self-aligned source/drain areas for P-channel FETs are formed by implanting boron difluoride (BF.sub.2) ions. In more conventional processing, the BF.sub.2 ions implanted in the P-channel FET gate electrodes during the source/drain implant results in outgassing of fluorine from the gate electrodes after the interlevel dielectric (ILD) layer is deposited. This can result in void formation, or delamination, at the interface between the gate electrode and the ILD. The current invention provides an improved process which uses a photoresist block-out mask to eliminate the implantation of the BF.sub.2.sup.+ ions in the P-channel FET gate electrodes during the formation of the self-aligned P.sup.+ source/drain regions. This prevents voids from forming at the gate electrode/ILD interface after the ILD layer is deposited and subsequent high-temperature processing steps are performed. The invention also reduces the enhanced boron diffusion in the P-FET gate oxide that can degrade the threshold voltage.

摘要翻译： 描述了一种用于形成具有浅源极/漏极结的P沟道场效应晶体管和用于CMOS电路的改善的可靠性的方法。 该方法包括通过交替的光刻胶掩模和离子注入形成N沟道和P沟道FET。 用于P沟道FET的浅结自对准源极/漏极区域是通过注入二氟化硼（BF 2）离子形成的。 在更常规的处理中，在源极/漏极注入期间注入到P沟道FET栅电极中的BF 2离子导致沉积了层间电介质（ILD）层之后，从栅电极释放氟。 这可能导致在栅电极和ILD之间的界面处的空隙形成或分层。 本发明提供了一种改进的方法，其使用光致抗蚀剂阻挡掩模以在形成自对准P +源极/漏极区域期间消除P沟道FET栅极中的BF 2 +离子的注入。 这防止了在淀积ILD层之后在栅电极/ ILD界面处形成空隙，并且执行随后的高温处理步骤。 本发明还减少了可能降低阈值电压的P-FET栅极氧化物中增强的硼扩散。