公开(公告)号：US5966604A

公开(公告)日：1999-10-12

申请号：US890363

申请日：1997-07-09

申请人： Han Lin ,  Jengping Lin ,  Sun-Chieh Chien

发明人： Han Lin ,  Jengping Lin ,  Sun-Chieh Chien

IPC分类号： H01L21/265 ,  H01L21/285 ,  H01L21/336 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L21/28525 ,  H01L29/1045 ,  H01L21/26586 ,  H01L29/7833

摘要： The present invention relates to a method of manufacturing MOS components having lightly doped drains wherein the implanting type ion used is different than that used in the formation of the source/drain regions. The present invention also includes the use of a tilt implantation angle accompanied by substrate rotation during the implantation process to form lightly doped drain structures on two sides of the source/drain regions. The mask is the same for the formation of the source/drain regions as that for the formation of the lightly doped drain regions. The method of manufacturing MOS components having lightly doped drains according to this invention has fewer manufacturing processes for the formation of spacers than the conventional methods. Moreover, the reduction in spacer production results in an increased contact surface area for subsequent contact window formation, thereby lowering contact resistance.

摘要翻译： 本发明涉及一种制造具有轻掺杂漏极的MOS元件的方法，其中使用的注入型离子不同于形成源极/漏极区所用的离子。 本发明还包括在注入工艺期间伴随着衬底旋转的倾斜注入角度的使用，以在源极/漏极区域的两侧上形成轻掺杂的漏极结构。 掩模与用于形成轻掺杂漏极区的源极/漏极区相同。 根据本发明的制造具有轻掺杂漏极的MOS元件的制造方法比常规方法具有更少的用于形成间隔物的制造工艺。 此外，间隔物生产的减少导致随后的接触窗形成的接触表面积增加，从而降低接触电阻。

公开(公告)号：US5679602A

公开(公告)日：1997-10-21

申请号：US716730

申请日：1996-09-23

申请人： Jengping Lin ,  Sun-Chieh Chien

发明人： Jengping Lin ,  Sun-Chieh Chien

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/762 ,  Y10S148/05

摘要： Device isolation is provided for a MOSFET circuit by providing channel stop regions comprising a distribution of dopants localized beneath and adjacent to corresponding field oxide regions. Channel stop regions are not formed under the channel regions of the MOSFETs and are selectively formed under the narrower field oxide regions which are most likely to provide inadequate device isolation. The channel stop regions are formed subsequent to the formation of field oxide regions, beginning by forming polysilicon spacers so that the polysilicon spacers extend over the bird's beak regions of the field oxide regions. Next, a channel stop mask having openings over selected field oxide regions is formed. Trenches are etched near the center of the exposed field oxide regions, leaving approximately 500 .ANG. of oxide on the bottom of the trench. Ions are implanted through the bottom of the trenches to form channel stop regions beneath the field oxide regions.

摘要翻译： 通过提供通道停止区域来为MOSFET电路提供器件隔离，该通道停止区域包含位于相应的场氧化物区域下方并与之相邻的掺杂剂的分布。 通道停止区域不形成在MOSFET的沟道区域之下，并且选择性地形成在最可能提供不充分的器件隔离的较窄场氧化物区域下。 在形成场氧化物区域之后形成通道停止区域，首先通过形成多晶硅间隔物，使得多晶硅间隔物延伸超过场氧化物区域的鸟嘴区域。 接下来，形成在选定的场氧化物区域上具有开口的通道阻挡掩模。 在暴露的场氧化物区域的中心附近蚀刻沟槽，在沟槽的底部留下约500个ANGSTROM的氧化物。 离子通过沟槽的底部注入以形成场氧化物区域下方的通道停止区域。

公开(公告)号：US5504038A

公开(公告)日：1996-04-02

申请号：US450409

申请日：1995-05-25

申请人： Sun-Chieh Chien ,  Jengping Lin

发明人： Sun-Chieh Chien ,  Jengping Lin

IPC分类号： H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76876 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76879

摘要： A structure and method is provided for forming a contact plug in a contact hole in a dielectric layer on a semiconductor substrate. A polysilicon spacer is formed on the sidewalls and bottom of the contact hole. A metal, such as titanium, is deposited on the sidewalls and bottom of the hole and on the dielectric layer. The substrate is heated to form a metal silicide layer, such as TiSi.sub.x, and a metal nitride layer, such as TiN, on the side-walls and bottom of the contact hole. Any remaining metal layer and metal nitride layer formed in the heating process is removed. This leaves the titanium silicide layer on the contact hole walls. Tungsten is deposited to fill the contact hole where the metal silicide promotes the nucleation of the tungsten. In a preferred embodiment, to further promote nucleation of the tungsten, a second metal nitride layer is formed on the surface; of the metal silicide layer just prior to tungsten deposition.

摘要翻译： 提供一种用于在半导体衬底上的电介质层的接触孔中形成接触插塞的结构和方法。 在接触孔的侧壁和底部上形成多晶硅间隔物。 诸如钛的金属沉积在孔的侧壁和底部以及电介质层上。 加热衬底以在接触孔的侧壁和底部上形成诸如TiSix的金属硅化物层和诸如TiN的金属氮化物层。 去除在加热过程中形成的任何剩余的金属层和金属氮化物层。 这使得硅化钛层在接触孔壁上留下。 沉积钨以填充金属硅化物促进钨的成核的接触孔。 在优选的实施方案中，为了进一步促进钨的成核，在表面上形成第二金属氮化物层; 在钨沉积之前的金属硅化物层。

公开(公告)号：US6107175A

公开(公告)日：2000-08-22

申请号：US27844

申请日：1998-02-23

申请人： Han Lin ,  Sun-Chieh Chien ,  Jengping Lin

发明人： Han Lin ,  Sun-Chieh Chien ,  Jengping Lin

IPC分类号： H01L21/285 ,  H01L21/60 ,  H01L21/3205

CPC分类号： H01L21/76897 ,  H01L21/28525

摘要： A method of a method of fabricating a contact. A substrate having a plurality of gates and a plurality of lightly doped source/drain regions is provided. A dielectric layer is formed and patterned to form a self-align contact window to expose a first lightly doped source/drain region of said lightly doped source/drain regions, and to form a first spacer on a side wall of a first gate of said gates simultaneously. An ion implantation is performed by using the first spacer as a mask, so that a first heavily doped source/drain region is formed in the first lightly doped source/drain region. A doped poly-silicon layer is formed over the substrate, and a metal silicide layer is formed on the doped poly-silicon layer. The doped poly-silicon and the metal silicide layer are patterned to form a self-align contact.

摘要翻译： 一种制造触点的方法的方法。 提供具有多个栅极和多个轻掺杂源极/漏极区域的衬底。 形成介电层并图案化以形成自对准接触窗口，以暴露所述轻掺杂源极/漏极区域的第一轻掺杂源极/漏极区域，并在所述第一栅极的侧壁上形成第一间隔物 同时门。 通过使用第一间隔件作为掩模来执行离子注入，使得在第一轻掺杂源极/漏极区域中形成第一重掺杂源极/漏极区域。 在衬底上形成掺杂多晶硅层，并且在掺杂多晶硅层上形成金属硅化物层。 将掺杂的多晶硅和金属硅化物层图案化以形成自对准接触。

公开(公告)号：US5510279A

公开(公告)日：1996-04-23

申请号：US369728

申请日：1995-01-06

申请人： Sun-Chieh Chien ,  Jengping Lin ,  Chen-Chiu Hsue

发明人： Sun-Chieh Chien ,  Jengping Lin ,  Chen-Chiu Hsue

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L21/8234

CPC分类号： H01L29/66659 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/7835 ,  H01L21/26586

摘要： A method of fabricating an asymmetric lightly doped drain transistor device. The device's drain region is shielded with a barrier layer when ion implantation is applied to a implant a highly doped source region. A large angle implantation then follows to form a lightly doped pocket region adjacent to the highly doped source region. The implantation forming the pocket region increases the doping concentration along the device's source side which increases the device's threshold voltage diminishing short channel effects.

摘要翻译： 一种制造不对称轻掺杂漏极晶体管器件的方法。 当离子注入施加到植入物高度掺杂的源区域时，器件的漏极区域被屏蔽层屏蔽。 然后，随后进行大角度注入以形成与高掺杂源区域相邻的轻掺杂袋区域。 形成口袋区域的注入增加了器件源极侧的掺杂浓度，这增加了器件的阈值电压降低了短沟道效应。

公开(公告)号：US5652160A

公开(公告)日：1997-07-29

申请号：US613092

申请日：1996-03-08

申请人： Jengping Lin ,  Sun-Chieh Chien

发明人： Jengping Lin ,  Sun-Chieh Chien

IPC分类号： H01L21/74 ,  H01L23/48 ,  H01L21/335

CPC分类号： H01L21/28525

摘要： A method of forming WSi.sub.x sidewall spacers as an etching stop in the fabrication process of a buried contact. After a gate dielectric layer and a first conducting layer are formed over a substrate, an opening is formed by etching through the gate dielectric layer and first conducting layer. WSi.sub.x sidewall spacers are thereafter formed on the sidewalls of the opening. Then, a second conducting layer is deposited onto the overall surface as well as being connected to the substrate via the opening. When the second and first conducting layers are patterned and etched to form a gate electrode and an interconnect layer, the WSi.sub.x acts as the etching stop to prevent the formation of ditches in the substrate.

摘要翻译： 在掩埋接触的制造工艺中形成WSix侧壁间隔物作为蚀刻停止件的方法。 在基板之上形成栅极介电层和第一导电层之后，通过蚀刻通过栅极介电层和第一导电层形成开口。 此后在开口的侧壁上形成WSix侧壁间隔物。 然后，第二导电层沉积在整个表面上，并且经由开口连接到基板。 当第二导电层和第一导电层被图案化和蚀刻以形成栅电极和互连层时，WSix充当蚀刻停止件以防止在衬底中形成沟槽。

公开(公告)号：US5612239A

公开(公告)日：1997-03-18

申请号：US519069

申请日：1995-08-24

申请人： Jengping Lin ,  Sun-Chieh Chien

发明人： Jengping Lin ,  Sun-Chieh Chien

IPC分类号： H01L21/316 ,  H01L21/336

CPC分类号： H01L29/6659 ,  H01L21/316

摘要： A process for manufacturing an LDD type of FET, based on the salicide process, is described. Said process does not lead to short circuits between the drain region and and the main body of the FET through the buried contact. The process is based on the use of Liquid Phase Deposition (LPD) as the method for growing the oxide layer from which the spacers are formed. Since oxide layers formed through LPD will deposit preferentially on silicon and silicon oxide surfaces relative to photoresist surfaces, the areas in which the LPD layer forms are readily controlled. This feature allows the buried contact layer to be replaced by an extended drain region which can be connected to other parts of the integrated circuit (by the salicide process) without the danger of shorting paths being formed therein.

摘要翻译： 描述了基于自对准硅化物工艺制造LDD型FET的工艺。 所述工艺不会通过埋入触点而导致漏极区域和FET主体之间的短路。 该方法基于使用液相沉积（LPD）作为生长形成间隔物的氧化物层的方法。 由于通过LPD形成的氧化物层相对于光致抗蚀剂表面优先沉积在硅和氧化硅表面上，因此容易控制LPD层形成的区域。 该特征允许掩埋接触层被延伸的漏极区域替代，该漏极区域可以连接到集成电路的其它部分（通过自对准硅化物工艺），而不会在其中形成短路路径的危险。

公开(公告)号：US06509235B2

公开(公告)日：2003-01-21

申请号：US09764333

申请日：2001-01-19

申请人： Sun-Chieh Chien ,  Chien-Li Kuo

发明人： Sun-Chieh Chien ,  Chien-Li Kuo

IPC分类号： H01L218232

CPC分类号： H01L27/105 ,  H01L21/82345 ,  H01L27/1052

摘要： The present invention provides a method for forming an embedded memory MOS. The method involves first forming a dielectric layer and an undoped polysilicon layer, respectively, on the surface of the semiconductor wafer with a defined memory array area and a periphery circuits region. Then, the undoped polysilicon layer in the memory array area is doped to become a doped polysilicon layer. Thereafter, a protective layer is formed on the surface of the semiconductor wafer, followed by a first photolithographic and etching process (PEP) to define a plurality of gate patterns in the protective layer in the memory array area. Then, a second PEP is applied to etch the undoped polysilicon layer in the periphery circuits region and the doped polysilicon layer in the memory array area to simultaneously form a gate of each MOS in the periphery circuits region and the memory array area. Finally, a lightly doped drain (LDD) of each MOS is formed, as well as a spacer and a source/drain (S/D) adjacent to each gate in the periphery circuits region.

摘要翻译： 本发明提供一种形成嵌入式存储器MOS的方法。 该方法包括首先在具有限定的存储器阵列区域和外围电路区域的半导体晶片的表面上分别形成介电层和未掺杂的多晶硅层。 然后，将存储器阵列区域中未掺杂的多晶硅层掺杂成为掺杂多晶硅层。 此后，在半导体晶片的表面上形成保护层，然后进行第一光刻和蚀刻工艺（PEP），以在存储器阵列区域中的保护层中限定多个栅极图案。 然后，施加第二PEP以蚀刻外围电路区域中的未掺杂多晶硅层和存储器阵列区域中的掺杂多晶硅层，以在外围电路区域和存储器阵列区域中同时形成每个MOS的栅极。 最后，形成每个MOS的轻掺杂漏极（LDD），以及与外围电路区域中的每个栅极相邻的间隔物和源极/漏极（S / D）。

公开(公告)号：US06465364B2

公开(公告)日：2002-10-15

申请号：US09764328

申请日：2001-01-19

申请人： Sun-Chieh Chien ,  Chien-Li Kuo

发明人： Sun-Chieh Chien ,  Chien-Li Kuo

IPC分类号： H01L2100

CPC分类号： H01L27/11526 ,  H01L21/28518 ,  H01L21/76895 ,  H01L27/105 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/11546

摘要： The present invention provides a method for the formation of contact plugs of an embedded memory. The method first forms a plurality of MOS transistors on a defined memory array region and periphery circuit region of the semiconductor wafer. Then, a first dielectric layer is formed on the memory array region, and plurality of landing pads is formed in the first dielectric layer. Next, both a stop layer and a second dielectric layer are formed, respectively, on the surface of semiconductor wafer. A PEP process is then used to form a plurality of contact plug holes in the second dielectric layer in both the memory array region and the periphery circuit region. Finally, a conductive layer is filled into each hole to form in-situ each contact plug in both the memory array region and the periphery circuit region.

摘要翻译： 本发明提供一种用于形成嵌入式存储器的接触塞的方法。 该方法首先在半导体晶片的限定的存储器阵列区域和外围电路区域上形成多个MOS晶体管。 然后，在存储器阵列区域上形成第一电介质层，并且在第一介电层中形成多个着陆焊盘。 接下来，在半导体晶片的表面上分别形成停止层和第二电介质层。 然后使用PEP工艺在存储器阵列区域和外围电路区域中的第二介电层中形成多个接触插塞孔。 最后，将导电层填充到每个孔中，以在存储器阵列区域和外围电路区域中的原位形成每个接触插塞。

公开(公告)号：US06406968B1

公开(公告)日：2002-06-18

申请号：US09767499

申请日：2001-01-23

申请人： Sun-Chieh Chien ,  Chien-Li Kuo

发明人： Sun-Chieh Chien ,  Chien-Li Kuo

IPC分类号： H01L2120

CPC分类号： H01L27/10894 ,  H01L21/76895 ,  H01L27/10855 ,  H01L28/60 ,  H01L28/90

摘要： A method of forming a dynamic random access memory. A substrate having a memory cell region and a logic circuit region is provided. The substrate also has a first dielectric layer thereon. The first dielectric layer in the memory cell region has a bit line and a node contact while the first dielectric layer in the logic circuit region has a first metallic interconnect. An intermediate dielectric layer is formed over the first dielectric layer such that the intermediate dielectric layer in the logic circuit region has a second metallic interconnect that connects electrically with the first metallic interconnect. A capacitor is formed in the intermediate dielectric layer within the memory cell region. A second dielectric layer is formed over the substrate. A third metallic interconnect is formed in the second dielectric layer such that the third metallic interconnect and the second metallic interconnect are electrically connected.

摘要翻译： 一种形成动态随机存取存储器的方法。 提供具有存储单元区域和逻辑电路区域的衬底。 衬底上也具有第一介电层。 存储单元区域中的第一介电层具有位线和节点接​​触，而逻辑电路区域中的第一介电层具有第一金属互连。 中间电介质层形成在第一电介质层上，使得逻辑电路区域中的中间介电层具有与第一金属互连电连接的第二金属互连。 在存储单元区域内的中间介质层中形成电容器。 第二介质层形成在衬底上。 在第二电介质层中形成第三金属互连，使得第三金属互连和第二金属互连电连接。