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公开(公告)号：US09507638B2
公开(公告)日：2016-11-29
申请号：US13291369
申请日：2011-11-08
申请人： Philip Alexander Cuadra , Karim M. Abdalla , Jerome F. Duluk, Jr. , Luke Durant , Gerald F. Luiz , Timothy John Purcell , Lacky V. Shah
发明人： Philip Alexander Cuadra , Karim M. Abdalla , Jerome F. Duluk, Jr. , Luke Durant , Gerald F. Luiz , Timothy John Purcell , Lacky V. Shah
CPC分类号： G06F9/5022
摘要： One embodiment of the present invention sets forth a technique for managing the allocation and release of resources during multi-threaded program execution. Programmable reference counters are initialized to values that limit the amount of resources for allocation to tasks that share the same reference counter. Resource parameters are specified for each task to define the amount of resources allocated for consumption by each array of execution threads that is launched to execute the task. The resource parameters also specify the behavior of the array for acquiring and releasing resources. Finally, during execution of each thread in the array, an exit instruction may be configured to override the release of the resources that were allocated to the array. The resources may then be retained for use by a child task that is generated during execution of a thread.
摘要翻译： 本发明的一个实施例提出了一种用于在多线程程序执行期间管理资源的分配和释放的技术。 可编程参考计数器被初始化为限制用于分配给共享相同引用计数器的任务的资源量的值。 为每个任务指定资源参数，以定义为执行任务启动的每个执行线程数组分配的消耗资源量。 资源参数还指定数组用于获取和释放资源的行为。 最后，在执行阵列中的每个线程时，可以将退出指令配置为覆盖分配给阵列的资源的释放。 然后可以保留资源以供执行线程期间生成的子任务使用。
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公开(公告)号：US08922555B2
公开(公告)日：2014-12-30
申请号：US12898998
申请日：2010-10-06
IPC分类号： G06T15/00
CPC分类号： G06T15/005
摘要： One embodiment of the present invention sets forth a technique for storing only the enabled components for each enabled vector and writing only enabled components to one or more specified render targets. A shader program header (SPH) file provides per-component mask bits for each render target. Each enabled mask bit indicates that the pixel shader generates the corresponding component as an output to the raster operations unit. In the hardware, the per-component mask bits are combined with the applications programming interface (API)-level per-component write masks to determine the components that are updated by the shader program. The combined mask is used as the write enable bits for components in one or more render targets. One advantage of the combined mask is that the components that are not updated are not forwarded from the pixel shader to the ROP, thereby saving bandwidth between those processing units.
摘要翻译： 本发明的一个实施例提出了一种用于仅存储每个启用向量的启用组件并仅将启用的组件写入一个或多个指定的渲染目标的技术。 着色器程序头（SPH）文件为每个渲染目标提供每个组件掩码位。 每个启用的屏蔽位指示像素着色器生成相应的组件作为光栅操作单元的输出。 在硬件中，每个组件掩码位与应用程序编程接口（API）级的每个组件写入掩码相结合，以确定由着色器程序更新的组件。 组合掩码用作一个或多个渲染目标中的组件的写使能位。 组合掩码的一个优点是未更新的组件不会从像素着色器转发到ROP，从而节省了这些处理单元之间的带宽。
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公开(公告)号：US08823724B2
公开(公告)日：2014-09-02
申请号：US12651192
申请日：2009-12-31
IPC分类号： G06T17/00 , G06T15/00 , G06T11/40 , G06F12/02 , G09G5/00 , G06K9/40 , G06K9/36 , G06K9/54 , G06T5/00 , G06T3/40
CPC分类号： G06T5/001 , G06T3/4007 , G06T15/04
摘要： Systems and methods for texture processing are presented. In one embodiment a texture method includes creating a sparse texture residency translation map; performing a probe process utilizing the sparse texture residency translation map information to return a finest LOD that contains the texels for a texture lookup operation; and performing the texture lookup operation utilizing the finest LOD. In one exemplary implementation, the finest LOD is utilized as a minimum LOD clamp during the texture lookup operation. A finest LOD number indicates a minimum resident LOD and a sparse texture residency translation map includes one finest LOD number per tile of a sparse texture. The sparse texture residency translation can indicate a minimum resident LOD.
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公开(公告)号：US08786618B2
公开(公告)日：2014-07-22
申请号：US12899431
申请日：2010-10-06
申请人： Jerome F. Duluk, Jr. , Jesse David Hall , Patrick R. Brown , Gernot Schaufler , Mark D. Stadler
发明人： Jerome F. Duluk, Jr. , Jesse David Hall , Patrick R. Brown , Gernot Schaufler , Mark D. Stadler
IPC分类号： G06T1/00
CPC分类号： G06T15/005
摘要： One embodiment of the present invention sets forth a technique for configuring a graphics processing pipeline (GPP) to process data according to one or more shader programs. The method includes receiving a plurality of pointers, where each pointer references a different shader program header (SPH) included in a plurality of SPHs, and each SPH is associated with a different shader program that executes within the GPP. For each SPH included in the plurality of SPHs, one or more GPP configuration parameters included in the SPH are identified, and the GPP is adjusted based on the one or more GPP configuration parameters.
摘要翻译： 本发明的一个实施例提出了一种用于配置图形处理流水线（GPP）以根据一个或多个着色器程序处理数据的技术。 该方法包括接收多个指针，其中每个指针引用包括在多个SPH中的不同着色器程序头（SPH），并且每个SPH与在GPP内执行的不同着色器程序相关联。 对于包括在多个SPH中的每个SPH，识别包括在SPH中的一个或多个GPP配置参数，并且基于一个或多个GPP配置参数来调整GPP。
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公开(公告)号：US08493395B2
公开(公告)日：2013-07-23
申请号：US13550468
申请日：2012-07-16
CPC分类号： G06F11/0793 , G06F11/0715 , G06F11/0751
摘要： A method and system for overriding state information programmed into a processor using an application programming interface (API) avoids introducing error conditions in the processor. An override monitor unit within the processor stores the programmed state for any setting that is overridden so that the programmed state can be restored when the error condition no longer exists. The override monitor unit overrides the programmed state by forcing the setting to a legal value that does not cause an error condition. The processor is able to continue operating without notifying a device driver that an error condition has occurred since the error condition is avoided.
摘要翻译： 使用应用编程接口（API）将编程到处理器中的状态信息进行覆盖的方法和系统避免了在处理器中引入错误状况。 处理器内的覆盖监视单元存储被覆盖的任何设置的编程状态，以便当错误条件不再存在时可以恢复编程状态。 覆盖监视器单元通过强制设置为不引起错误条件的合法值来覆盖编程状态。 处理器能够在不通知设备驱动程序的情况下继续运行，因为避免了错误条件，所以发生了错误状况。
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公开(公告)号：US20110084975A1
公开(公告)日：2011-04-14
申请号：US12893617
申请日：2010-09-29
申请人： Jerome F. DULUK, JR. , Thomas Roell
发明人： Jerome F. DULUK, JR. , Thomas Roell
IPC分类号： G06T1/00
CPC分类号： G06T17/00 , G06F9/3009 , G06F9/30101 , G06F9/30109 , G06F9/3851 , G06F9/3887 , G06T2210/32
摘要： One embodiment of the present invention sets forth a technique for reducing the overhead for transmitting explicit begin and explicit end commands that are needed in primitive draw command sequences. A draw method includes a header to specify an implicit begin command, an implicit end command, and instancing information for a primitive draw command sequence. The header is followed by a packet including one or more data words (dwords) that each specify a primitive topology, starting offset into a vertex or index buffer, and vertex or index count. Only a single clock cycle is consumed to transmit and process the header. The performance of graphics application programs that have many small batches of geometry (as is typical of many workstation applications) may be improved since the overhead of transmitting and processing the explicit begin and explicit end draw commands is reduced.
摘要翻译： 本发明的一个实施例提出了用于减少用于发送原始绘制命令序列中所需的显式开始和显式终止命令的开销的技术。 绘制方法包括用于指定隐式开始命令的头部，隐式结束命令和用于原始绘制命令序列的实例化信息。 标题之后是包括一个或多个数据字（dwords）的数据包，每个数据字指定原始拓扑，将偏移开始到顶点或索引缓冲区，以及顶点或索引计数。 仅消耗一个时钟周期来传输和处理标题。 可以改进具有许多小批量几何图形应用程序的性能（如许多工作站应用程序的典型），因为减少了显式开始和显式结束绘制命令的传输和处理的开销。
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公开(公告)号：US20110080415A1
公开(公告)日：2011-04-07
申请号：US12895579
申请日：2010-09-30
IPC分类号： G06T1/20
CPC分类号： G06T1/20 , G06F9/3851 , G06F9/3887 , G06T15/005 , G06T2210/04 , G06T2210/52
摘要： One embodiment of the present invention sets forth a technique for reducing the amount of memory required to store vertex data processed within a processing pipeline that includes a plurality of shading engines. The method includes determining a first active shading engine and a second active shading engine included within the processing pipeline, wherein the second active shading engine receives vertex data output by the first active shading engine. An output map is received and indicates one or more attributes that are included in the vertex data and output by the first active shading engine. An input map is received and indicates one or more attributes that are included in the vertex data and received by the second active shading engine from the first active shading engine. Then, a buffer map is generated based on the input map, the output map, and a pre-defined set of rules that includes rule data associated with both the first shading engine and the second shading engine, wherein the buffer map indicates one or more attributes that are included in the vertex data and stored in a memory that is accessible by both the first active shading engine and the second active shading engine.
摘要翻译： 本发明的一个实施例提出了一种用于减少存储在包括多个着色引擎的处理流水线中处理的顶点数据所需的存储量的技术。 该方法包括确定包括在处理流水线内的第一主动着色引擎和第二主动着色引擎，其中第二主动着色引擎接收由第一主动着色引擎输出的顶点数据。 接收输出图，并指示包含在顶点数据中并由第一主动着色引擎输出的一个或多个属性。 接收输入图，并且指示包括在顶点数据中并由第二主动着色引擎从第一主动着色引擎接收的一个或多个属性。 然后，基于输入映射，输出映射和包括与第一着色引擎和第二着色引擎相关联的规则数据的预定义规则集来生成缓冲器映射，其中缓冲器映射指示一个或多个 包括在顶点数据中并存储在可由第一主动着色引擎和第二主动着色引擎访问的存储器中的属性。
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公开(公告)号：US20110080407A1
公开(公告)日：2011-04-07
申请号：US12898998
申请日：2010-10-06
IPC分类号： G06T15/80
CPC分类号： G06T15/005
摘要： One embodiment of the present invention sets forth a technique for storing only the enabled components for each enabled vector and writing only enabled components to one or more specified render targets. A shader program header (SPH) file provides per-component mask bits for each render target. Each enabled mask bit indicates that the pixel shader generates the corresponding component as an output to the raster operations unit. In the hardware, the per-component mask bits are combined with the applications programming interface (API)-level per-component write masks to determine the components that are updated by the shader program. The combined mask is used as the write enable bits for components in one or more render targets. One advantage of the combined mask is that the components that are not updated are not forwarded from the pixel shader to the ROP, thereby saving bandwidth between those processing units.
摘要翻译： 本发明的一个实施例提出了一种用于仅存储每个启用向量的启用组件并仅将启用的组件写入一个或多个指定的渲染目标的技术。 着色器程序头（SPH）文件为每个渲染目标提供每个组件掩码位。 每个启用的屏蔽位指示像素着色器生成相应的组件作为光栅操作单元的输出。 在硬件中，每个组件掩码位与应用程序编程接口（API）级的每个组件写入掩码相结合，以确定由着色器程序更新的组件。 组合掩码用作一个或多个渲染目标中的组件的写使能位。 组合掩码的一个优点是未更新的组件不会从像素着色器转发到ROP，从而节省了这些处理单元之间的带宽。
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公开(公告)号：US06664959B2
公开(公告)日：2003-12-16
申请号：US10231436
申请日：2002-08-29
申请人： Jerome F. Duluk, Jr. , Stephen L. Dodgen , Richard E. Hessel , Emerson S. Fang , Hengwei Hsu , Jason R. Redgrave , Sushma S. Trivedi
发明人： Jerome F. Duluk, Jr. , Stephen L. Dodgen , Richard E. Hessel , Emerson S. Fang , Hengwei Hsu , Jason R. Redgrave , Sushma S. Trivedi
IPC分类号： G06T1540
CPC分类号： G06T15/20 , G06T1/60 , G06T11/001 , G06T11/40 , G06T15/005 , G06T15/04 , G06T15/30 , G06T15/40 , G06T15/50 , G06T15/80 , G06T15/83 , G06T15/87
摘要： Structure, apparatus, and method for performing conservative hidden surface removal in a graphics processor. Culling is divided into two steps, a magnitude comparison content addressable memory cull operation (MCCAM Cull), and a subpixel cull operation. The MCCAM Cull discards primitives that are hidden completely by previously processed geometry. The Subpixel Cull takes the remaining primitives (which are partly or entirely visible), and determines the visible fragments. In one embodiment the method of performing hidden surface removal includes: selecting a current primitive comprising a plurality of stamps; comparing stamps to stamps from previously evaluated primitives; selecting a first stamp as a currently potentially visible stamp (CPVS) based on a relationship of depth states of samples in the first stamp with depth states of samples of previously evaluated stamps; comparing the CPVS to a second stamp; discarding the second stamp when no part of the second stamp would affect a final graphics display image based on the stamps that have been evaluated; discarding the CPVS and making the second stamp the CPVS, when the second stamp hides the CPVS; dispatching the CPVS and making the second stamp the CPVS when both the second stamp and the CPVS are at least partially visible in the final graphics display image; and dispatching the second stamp and the CPVS when the visibility of the second stamp and the CPVS depends on parameters evaluated later in the computer graphics pipeline.
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10.再颁专利Graphical rendering system using simultaneous parallel query Z-buffer and method therefor 有权图形渲染系统采用同时并行查询Z缓冲区及其方法公开(公告)号：USRE38078E1
公开(公告)日：2003-04-15
申请号：US09234932
申请日：1999-01-21
申请人： Jerome F. Duluk, Jr.
发明人： Jerome F. Duluk, Jr.
IPC分类号： G06T1540
CPC分类号： G06T15/405 , G06T2210/12
摘要： Apparatus and method for a Parallel Query Z-coordinate Buffer are described. The apparatus and method perform a keep/discard decision on screen coordinate geometry before the geometry is converted or rendered into individual display screen pixels by implementing a parallel searching technique within a novel z-coordinate buffer based on a novel magnitude comparison content addressable memory (MCCAM) structure. The MCCAM provides means structure and method for performing simultaneous arithmetic magnitude comparisons on numerical quantities. These arithmetic magnitude comparisons include arithmetic less-than, greater-than, less-than-or-equal to, and greater-than-or-equal-to operations between coordinate values of a selected graphical object and the coordinate values of other objects in the image scene which may or may not occult the selected graphical object. Embodiments of the method and apparatus utilizing variations The structure and method support variations and combinations of bounding box occulting tests, vertex bounding box occulting tests, span occulting tests, and raster-write occulting tests, as well as combinations of these tests are described .
摘要翻译： 描述并行查询Z坐标缓冲器的装置和方法
。 该装置和方法 在几何被转换或呈现为单独的显示屏像素之前对屏幕坐标几何执行保留/丢弃决定，通过在小说中实现并行搜索技术 基于新颖的量子比较内容可寻址存储器（MCCAM）结构的z坐标缓冲器。 表示 结构和方法 ，用于对数值进行同时算术大小比较。 这些算术大小比较包括算术小于，大于，小于或等于和大于或等于所选图形对象的坐标值与其他对象的坐标值之间的运算 可能或可能不隐藏所选择的图形对象的图像场景。 使用变化的方法和装置的实施例 结构和方法支持边界隐蔽测试，顶点边界隐蔽测试，跨度遮蔽的变体和组合 测试和光栅写入隐蔽测试 以及这些测试的组合描述 。
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