公开(公告)号：US06717850B1

公开(公告)日：2004-04-06

申请号：US10313676

申请日：2002-12-05

申请人： Jiang Li ,  Nian Yang ,  Zhigang Wang ,  John Jianshi Wang

发明人： Jiang Li ,  Nian Yang ,  Zhigang Wang ,  John Jianshi Wang

IPC分类号： G11C1604

CPC分类号： G11C29/50 ,  G11C16/04 ,  G11C2029/0403

摘要： A method of processing a semiconductor device is disclosed and comprises applying a relatively high voltage across a gate stack of a flash memory cell for a certain period of time. Then, the polarity of the applied voltage is reversed and is again applied across the gate stack for another certain period of time. The voltage applied is greater than a channel erase voltage utilized for the memory cell. This applied voltage causes extrinsic defects to become amplified at interfaces of oxide/insulator layers of the gate stack. Then, the memory cell is tested (e.g., via a battery of tests) in order to determine if the memory cell is defective. If the cell is defective (e.g., fails the test), it can be assumed that substantial extrinsic defects were present in the memory cell and have been amplified resulting in the test failure. If the cell passes the test, it can be assumed that the memory cell is substantially free from extrinsic defects. Defective memory cells/devices can be marked or otherwise indicated as being defective.

摘要翻译： 公开了一种处理半导体器件的方法，并且包括在闪存单元的栅极堆叠上施加相当高的电压一段时间。 然后，施加的电压的极性反转，并再次施加在栅极堆叠另外一段时间。 施加的电压大于用于存储器单元的通道擦除电压。 该施加的电压导致外部缺陷在栅极堆叠的氧化物/绝缘体层的界面处被放大。 然后，测试存储器单元（例如，通过测试电池），以便确定存储器单元是否有故障。 如果细胞有缺陷（例如，测试失败），则可以认为在存储单元中存在大量的外在缺陷并且被放大，导致测试失败。 如果单元通过测试，则可以认为存储单元基本上没有外在缺陷。 存储器单元/器件不良或可能被标记为有缺陷。

公开(公告)号：US06797650B1

公开(公告)日：2004-09-28

申请号：US10342032

申请日：2003-01-14

申请人： Zhigang Wang ,  Nian Yang ,  John Jianshi Wang ,  Jiang Li

发明人： Zhigang Wang ,  Nian Yang ,  John Jianshi Wang ,  Jiang Li

IPC分类号： H01L2131

CPC分类号： H01L21/28202 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/3144 ,  H01L21/3145 ,  H01L29/513 ,  H01L29/518

摘要： One aspect of the invention relates to flash memory device that stores charge in a substantially stoichiometric silicon oxynitride dielectric. A stoichiometric silicon oxynitride dielectric can be represented by the formula (Si3N4)x(SiO2)(1-x), where x is from 0-1. A substantially stoichiometric silicon oxynitride dielectric has relatively few atoms that do not fit into the foregoing formula. The flash memory devices of the present invention have fewer defects and lower leakage than comparable SONOS-type flash memory devices. Another aspect of the invention relates to assessing the stoichiometry by FTIR, refractive index measurement, or a combination of the two.

摘要翻译： 本发明的一个方面涉及将电荷存储在基本上化学计量的氮氧化硅电介质中的闪存器件。 化学计量的氮氧化硅电介质可由式（Si 3 N 4）x（SiO 2）（1-x）表示，其中x为0-1。 基本上化学计量的氮氧化硅电介质具有不符合上述公式的相对较少的原子。 本发明的闪速存储器件具有比可比较的SONOS型闪存器件更少的缺陷和更低的泄漏。 本发明的另一方面涉及通过FTIR，折射率测量或两者的组合来评估化学计量。

公开(公告)号：US06777957B1

公开(公告)日：2004-08-17

申请号：US10174734

申请日：2002-06-18

申请人： Nian Yang ,  Zhigang Wang ,  John Jianshi Wang

发明人： Nian Yang ,  Zhigang Wang ,  John Jianshi Wang

IPC分类号： G01R2726

CPC分类号： H01L27/11521 ,  G11C16/04 ,  G11C29/50 ,  G11C2029/0403 ,  G11C2029/5002 ,  H01L22/34 ,  H01L27/115 ,  H01L2924/3011

摘要： An apparatus for testing a dielectric property of a material constituting the interlayer dielectric of a flash memory device is formed by a layer (122) of the dielectric material disposed throughout a test structure (200) representative of the flash memory device and a plurality of conductors (117A, 117B, 117C) disposed within that layer (122) or a pair of planar conductors (402, 404; 502, 503; 504, 505; 506, 507; 508, 509) deposited such that the conductors (402, 404; 502, 503; 504, 505; 506, 507; 508, 509) are substantially parallel to each other and the layer (122) of dielectric material is disposed throughout a test structure (400, 500) so as to separate the conductors (402, 404; 502, 503; 504, 505; 506, 507; 508, 509), the test structure (400, 500) functioning as a capacitor. The apparatus may also test a conductive property of a material constituting the conducting lines of a flash memory device by disposing a conductor (801, 901) through the dielectric material (122).

摘要翻译： 用于测试构成闪速存储器件的层间电介质的材料的介电性能的装置由设置在表示闪速存储器件的测试结构（200）内的介电材料层（122）和多个导体 （122A），或者一对平面导体（402,404; 502,503,504,505,506,507,508,509），这些导体（402,404） ; 502,503,504,505,506,507,508,509,506,507,508,505,506,507,508,505,505,505,508,505,509,506,507,508,505,509,508,509,508,509,508,509,505,505,509,508,509,508,509,505,505,509,505,505,509,505,505,509,505,505,509,50 所述测试结构（400,500）用作电容器，所述测试结构（400,500）用作电容器（402,404; 502,503,504,505,506,507,508,509）。 该设备还可以通过将电介质材料（122）布置在导体（801,901）上来测试构成闪存器件的导线的材料的导电性能。

公开(公告)号：US06590260B1

公开(公告)日：2003-07-08

申请号：US10103077

申请日：2002-03-20

申请人： Nian Yang ,  John Jianshi Wang ,  Zhigang Wang

发明人： Nian Yang ,  John Jianshi Wang ,  Zhigang Wang

IPC分类号： H01L2976

CPC分类号： H01L21/28273 ,  H01L29/42324 ,  H01L29/7883

摘要： A method for enhancing the operating characteristics of memory devices (400C), such as flash memory devices, by manipulating the Fermi energy levels of the substrate (406) and the floating gate (404). In so doing, the gap between the minimum conduction band energy level (408) and the Fermi energy level (412) of the floating gate (404) is extended so as to readily facilitate the movement of electrons from the substrate (406) into the floating gate (404).

摘要翻译： 一种用于通过操纵衬底（406）和浮动栅极（404）的费米能级来增强诸如闪存器件的存储器件（400C）的操作特性的方法。 在这样做时，浮动栅极（404）的最小导带能量水平（408）和费米能级（412）之间的间隙被延伸，以便容易地促进电子从衬底（406）移动到 浮动门（404）。

公开(公告)号：US06643185B1

公开(公告)日：2003-11-04

申请号：US10215140

申请日：2002-08-07

申请人： Zhigang Wang ,  Nian Yang ,  Jiang Li

发明人： Zhigang Wang ,  Nian Yang ,  Jiang Li

IPC分类号： G11C1604

CPC分类号： G11C16/3404

摘要： A method for repairing over-erasure of floating gate memory devices. Specifically, one embodiment of the present invention discloses a method for performing a program disturb operation on an array of memory cells for repairing over-erasure of fast bits. The program disturb operation is applied simultaneously to the entire array making it compatible with channel erase schemes. The fast bits are programmed back to a normal state above 0 Volts by applying a substrate voltage to a substrate common to the array of memory cells. A gate voltage is applied to a plurality of word lines coupled to control gates of said array of memory cells. A program pulse time for applying voltages ranges from approximately 10 microseconds to 1 second. A voltage differential between a control gate and the substrate in a memory cell is in the range of approximately 9 Volts to about 20 Volts.

摘要翻译： 一种用于修复浮动栅极存储器件的过度擦除的方法。 具体地，本发明的一个实施例公开了一种用于对用于修复快速位的擦除的存储器单元阵列执行编程干扰操作的方法。 编程干扰操作同时应用于整个阵列，使其与信道擦除方案兼容。 通过将衬底电压施加到存储器单元阵列共用的衬底上，快速位被编程回0伏以上的正常状态。 栅极电压被施加到耦合到所述存储器单元阵列的控制栅极的多个字线。 用于施加电压的编程脉冲时间范围从大约10微秒到1秒。 存储器单元中的控制栅极和衬底之间的电压差在大约9伏至大约20伏的范围内。

公开(公告)号：US07042767B2

公开(公告)日：2006-05-09

申请号：US10909693

申请日：2004-08-02

申请人： Zhigang Wang ,  Nian Yang ,  Zhizheng Liu

发明人： Zhigang Wang ,  Nian Yang ,  Zhizheng Liu

IPC分类号： G11C16/04

CPC分类号： G11C16/12

摘要： Disclosed are a flash memory unit and a method of programming a flash memory device. The method of programming can include applying respective programming voltages to a control gate and a drain of the memory device. A source bias potential can be applied to a source of the memory device. The application of the source bias potential can be controlled with the selective application of one of the programming voltages to a source bias switching device.

公开(公告)号：US07042766B1

公开(公告)日：2006-05-09

申请号：US10896651

申请日：2004-07-22

申请人： Zhigang Wang ,  Nian Yang ,  Zhizheng Liu

发明人： Zhigang Wang ,  Nian Yang ,  Zhizheng Liu

IPC分类号： G11C16/06

CPC分类号： G11C11/5628 ,  G11C16/12 ,  G11C16/3468 ,  G11C2211/5621

摘要： Disclosed is a method of programming a flash memory device to store an amount of charge corresponding to one of a plurality of charged program states. The method can include pulsing the memory device with program voltages including at least a gate voltage. If the gate voltage is greater than or equal to a predetermined minimum threshold voltage for the one of the plurality of charged program states, an amount of charge stored by the memory device can be verified. Otherwise the memory device can be repulsed. This procedure can be carried out until verifying is conducted and the verifying indicates that the amount of charge stored by the memory device corresponds to the one of the plurality of charged program states.

摘要翻译： 公开了一种编程闪速存储器件以存储对应于多个充电程序状态之一的电荷量的方法。 该方法可以包括使具有至少包括栅极电压的编程电压脉冲存储器件。 如果栅极电压大于或等于多个充电程序状态之一的预定最小阈值电压，则可以验证由存储器件存储的电荷量。 否则可能会使存储器件发生故障。 可以执行该过程，直到进行验证，并且验证指示存储器件存储的电荷量对应于多个充电程序状态中的一个。

公开(公告)号：US06888157B1

公开(公告)日：2005-05-03

申请号：US09917440

申请日：2001-07-27

申请人： Zhigang Wang ,  Nian Yang ,  Yue-song He

发明人： Zhigang Wang ,  Nian Yang ,  Yue-song He

IPC分类号： H01L23/544 ,  H01L23/58

CPC分类号： H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A capacitor structure for characterizing polysilicon gate depletion effects of a particular semiconductor fabrication process. In one embodiment, an N-Gate/N-Substrate capacitor is fabricated with the semiconductor fabrication process which is being evaluated for its polysilicon gate depletion effects. The N-gate of capacitor structure is driven to depletion while the N-substrate is simultaneously driven to accumulation. Capacitance-voltage measurements are taken. Based on these CV measurements, the polysilicon depletion effects are then obtained for that particular semiconductor fabrication process. In another embodiment, a P-Gate/P-Substrate capacitor is fabricated with the semiconductor fabrication process. The gate of the P-Gate/P-Substrate capacitor is driven to depletion while the substrate is simultaneously driven to accumulation. Based on the CV measurements performed on the P-Gate/P-Substrate capacitor, the polysilicon depletion effects can be obtained for that particular semiconductor fabrication process. In a third embodiment, a capacitor structure device is used to evaluate the polysilicon gate depletion effects of a semiconductor fabrication process. Different voltages are selectively applied to the gate of either an N-Gate/N-Substrate capacitor or a P-Gate/P-Substrate capacitor while its capacitance is measured. Based on the CV measurements, the polysilicon gate depletion effects for that particular semiconductor fabrication process is characterized.

摘要翻译： 用于表征特定半导体制造工艺的多晶硅栅极耗尽效应的电容器结构。 在一个实施例中，通过正在评估其多晶硅栅极耗尽效应的半导体制造工艺来制造N栅极/ N-衬底电容器。 驱动电容器结构的N栅极耗尽，同时驱动N衬底进行积累。 进行电容电压测量。 基于这些CV测量，然后获得针对该特定半导体制造工艺的多晶硅耗尽效应。 在另一个实施例中，通过半导体制造工艺制造P栅极/ P-基板电容器。 P栅极/ P基板电容器的栅极被驱动为耗尽，同时基板同时被驱动以累积。 基于在P型栅极/ P-基板电容器上执行的CV测量，可以获得针对该特定半导体制造工艺的多晶硅耗尽效应。 在第三实施例中，使用电容器结构器件来评估半导体制造工艺的多晶硅栅极耗尽效应。 在测量其电容时，不同的电压选择性地施加到N栅极/ N基板电容器或P栅极/ P基板电容器的栅极。 基于CV测量，对该特定半导体制造工艺的多晶硅栅极耗尽效应进行了表征。

公开(公告)号：US06818462B1

公开(公告)日：2004-11-16

申请号：US10224028

申请日：2002-08-19

申请人： Tien-Chun Yang ,  Nian Yang ,  Zhigang Wang

发明人： Tien-Chun Yang ,  Nian Yang ,  Zhigang Wang

IPC分类号： H01L2166

CPC分类号： H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of determining the active region width (10) of an active region (4) by measuring the respective capacitance values (C100, C100′, C100″) of respective composite capacitance structures (100, 100′, 100″), respectively comprising at least one capacitor element(16, 17, 18; 16′, 17′, 18″; 16″, 17″, 18″) having respective predetermined widths (Wi) for fabricating a flash memory semiconductor device, and a device thereby fabricated. The present method also comprises plotting the respective capacitance values (C100, C100′, C100″) as a quasi-linear function (CW) of the respective predetermined widths (Wi), extrapolating a calibration term (WC=0) from the quasi-linear function (CW), and subtracting the calibration term (WC=0) from the respective predetermined widths (Wi) to define and constrain the active region width (10) for facilitating device fabrication.

摘要翻译： 通过测量各个复合电容结构（100,100'，100“）的各个电容值（C100，C100'，C100”）来确定有源区域（4）的有源区宽度（10）的方法， 分别包括至少一个电容器元件（16,17,18; 16'，17“，18”，16“，17”，18“），其具有用于制造闪速存储器半导体器件的各自的预定宽度 ，以及由此制造的装置。 本方法还包括将各个电容值（C100，C100'，C100“）绘制为各个预定宽度（Wi）的准线性函数（CW），从准准则中外推校准项（WC = 0） 线性函数（CW），并从相应的预定宽度（Wi）减去校准项（WC = 0），以限定和约束有源区宽度（10）以便于器件制造。

公开(公告)号：US06716710B1

公开(公告)日：2004-04-06

申请号：US10126207

申请日：2002-04-19

申请人： Hsiao-Han Thio ,  Nian Yang ,  Zhigang Wang

发明人： Hsiao-Han Thio ,  Nian Yang ,  Zhigang Wang

IPC分类号： H01L21336

CPC分类号： H01L29/6656 ,  H01L21/76224 ,  H01L21/823468 ,  H01L21/823481

摘要： A method of fabricating a semiconductor device. A first layer comprising a first material is deposited to a first thickness on a sidewall of a stacked gate. A second layer comprising a second material is deposited over the first layer. The second layer is deposited without the first layer being etched; hence, the first thickness is unchanged along the sidewall. The second layer is reduced to a second thickness along the sidewall. The first layer and the second layer in combination form a spacer along the sidewall that has a thickness corresponding to the first thickness and the second thickness. Thus, the spacer can be formed using a single etch, reducing the number of processing steps. In addition, the first layer protects shallow trench filler material from gouging during the etch.

摘要翻译： 一种制造半导体器件的方法。 包括第一材料的第一层在堆叠栅极的侧壁上沉积到第一厚度。 包含第二材料的第二层沉积在第一层上。 沉积第二层，而不蚀刻第一层; 因此，第一厚度沿侧壁不变。 第二层沿着侧壁被还原成第二厚度。 第一层和第二层组合形成沿着侧壁的间隔物，其具有对应于第一厚度和第二厚度的厚度。 因此，间隔物可以使用单一蚀刻形成，减少了处理步骤的数量。 此外，第一层在蚀刻期间保护浅沟槽填料材料免于气刨。