公开(公告)号：US07042767B2

公开(公告)日：2006-05-09

申请号：US10909693

申请日：2004-08-02

申请人： Zhigang Wang ,  Nian Yang ,  Zhizheng Liu

发明人： Zhigang Wang ,  Nian Yang ,  Zhizheng Liu

IPC分类号： G11C16/04

CPC分类号： G11C16/12

摘要： Disclosed are a flash memory unit and a method of programming a flash memory device. The method of programming can include applying respective programming voltages to a control gate and a drain of the memory device. A source bias potential can be applied to a source of the memory device. The application of the source bias potential can be controlled with the selective application of one of the programming voltages to a source bias switching device.

公开(公告)号：US07042766B1

公开(公告)日：2006-05-09

申请号：US10896651

申请日：2004-07-22

申请人： Zhigang Wang ,  Nian Yang ,  Zhizheng Liu

发明人： Zhigang Wang ,  Nian Yang ,  Zhizheng Liu

IPC分类号： G11C16/06

CPC分类号： G11C11/5628 ,  G11C16/12 ,  G11C16/3468 ,  G11C2211/5621

摘要： Disclosed is a method of programming a flash memory device to store an amount of charge corresponding to one of a plurality of charged program states. The method can include pulsing the memory device with program voltages including at least a gate voltage. If the gate voltage is greater than or equal to a predetermined minimum threshold voltage for the one of the plurality of charged program states, an amount of charge stored by the memory device can be verified. Otherwise the memory device can be repulsed. This procedure can be carried out until verifying is conducted and the verifying indicates that the amount of charge stored by the memory device corresponds to the one of the plurality of charged program states.

摘要翻译： 公开了一种编程闪速存储器件以存储对应于多个充电程序状态之一的电荷量的方法。 该方法可以包括使具有至少包括栅极电压的编程电压脉冲存储器件。 如果栅极电压大于或等于多个充电程序状态之一的预定最小阈值电压，则可以验证由存储器件存储的电荷量。 否则可能会使存储器件发生故障。 可以执行该过程，直到进行验证，并且验证指示存储器件存储的电荷量对应于多个充电程序状态中的一个。

公开(公告)号：US20060023511A1

公开(公告)日：2006-02-02

申请号：US10909693

申请日：2004-08-02

申请人： Zhigang Wang ,  Nian Yang ,  Zhizheng Liu

发明人： Zhigang Wang ,  Nian Yang ,  Zhizheng Liu

IPC分类号： G11C16/04 ,  G11C11/34

CPC分类号： G11C16/12

摘要： Disclosed are a flash memory unit and a method of programming a flash memory device. The method of programming can include applying respective programming voltages to a control gate and a drain of the memory device. A source bias potential can be applied to a source of the memory device. The application of the source bias potential can be controlled with the selective application of one of the programming voltages to a source bias switching device.

摘要翻译： 公开了一种闪速存储器单元和一种对闪速存储器件进行编程的方法。 编程的方法可以包括将相应的编程电压施加到存储器件的控制栅极和漏极。 源极偏置电位可以应用于存储器件的源极。 可以通过选择性地将一个编程电压施加到源极偏置开关器件来控制源极偏置电位的应用。

公开(公告)号：US06888157B1

公开(公告)日：2005-05-03

申请号：US09917440

申请日：2001-07-27

申请人： Zhigang Wang ,  Nian Yang ,  Yue-song He

发明人： Zhigang Wang ,  Nian Yang ,  Yue-song He

IPC分类号： H01L23/544 ,  H01L23/58

CPC分类号： H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A capacitor structure for characterizing polysilicon gate depletion effects of a particular semiconductor fabrication process. In one embodiment, an N-Gate/N-Substrate capacitor is fabricated with the semiconductor fabrication process which is being evaluated for its polysilicon gate depletion effects. The N-gate of capacitor structure is driven to depletion while the N-substrate is simultaneously driven to accumulation. Capacitance-voltage measurements are taken. Based on these CV measurements, the polysilicon depletion effects are then obtained for that particular semiconductor fabrication process. In another embodiment, a P-Gate/P-Substrate capacitor is fabricated with the semiconductor fabrication process. The gate of the P-Gate/P-Substrate capacitor is driven to depletion while the substrate is simultaneously driven to accumulation. Based on the CV measurements performed on the P-Gate/P-Substrate capacitor, the polysilicon depletion effects can be obtained for that particular semiconductor fabrication process. In a third embodiment, a capacitor structure device is used to evaluate the polysilicon gate depletion effects of a semiconductor fabrication process. Different voltages are selectively applied to the gate of either an N-Gate/N-Substrate capacitor or a P-Gate/P-Substrate capacitor while its capacitance is measured. Based on the CV measurements, the polysilicon gate depletion effects for that particular semiconductor fabrication process is characterized.

摘要翻译： 用于表征特定半导体制造工艺的多晶硅栅极耗尽效应的电容器结构。 在一个实施例中，通过正在评估其多晶硅栅极耗尽效应的半导体制造工艺来制造N栅极/ N-衬底电容器。 驱动电容器结构的N栅极耗尽，同时驱动N衬底进行积累。 进行电容电压测量。 基于这些CV测量，然后获得针对该特定半导体制造工艺的多晶硅耗尽效应。 在另一个实施例中，通过半导体制造工艺制造P栅极/ P-基板电容器。 P栅极/ P基板电容器的栅极被驱动为耗尽，同时基板同时被驱动以累积。 基于在P型栅极/ P-基板电容器上执行的CV测量，可以获得针对该特定半导体制造工艺的多晶硅耗尽效应。 在第三实施例中，使用电容器结构器件来评估半导体制造工艺的多晶硅栅极耗尽效应。 在测量其电容时，不同的电压选择性地施加到N栅极/ N基板电容器或P栅极/ P基板电容器的栅极。 基于CV测量，对该特定半导体制造工艺的多晶硅栅极耗尽效应进行了表征。

公开(公告)号：US06818462B1

公开(公告)日：2004-11-16

申请号：US10224028

申请日：2002-08-19

申请人： Tien-Chun Yang ,  Nian Yang ,  Zhigang Wang

发明人： Tien-Chun Yang ,  Nian Yang ,  Zhigang Wang

IPC分类号： H01L2166

CPC分类号： H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of determining the active region width (10) of an active region (4) by measuring the respective capacitance values (C100, C100′, C100″) of respective composite capacitance structures (100, 100′, 100″), respectively comprising at least one capacitor element(16, 17, 18; 16′, 17′, 18″; 16″, 17″, 18″) having respective predetermined widths (Wi) for fabricating a flash memory semiconductor device, and a device thereby fabricated. The present method also comprises plotting the respective capacitance values (C100, C100′, C100″) as a quasi-linear function (CW) of the respective predetermined widths (Wi), extrapolating a calibration term (WC=0) from the quasi-linear function (CW), and subtracting the calibration term (WC=0) from the respective predetermined widths (Wi) to define and constrain the active region width (10) for facilitating device fabrication.

摘要翻译： 通过测量各个复合电容结构（100,100'，100“）的各个电容值（C100，C100'，C100”）来确定有源区域（4）的有源区宽度（10）的方法， 分别包括至少一个电容器元件（16,17,18; 16'，17“，18”，16“，17”，18“），其具有用于制造闪速存储器半导体器件的各自的预定宽度 ，以及由此制造的装置。 本方法还包括将各个电容值（C100，C100'，C100“）绘制为各个预定宽度（Wi）的准线性函数（CW），从准准则中外推校准项（WC = 0） 线性函数（CW），并从相应的预定宽度（Wi）减去校准项（WC = 0），以限定和约束有源区宽度（10）以便于器件制造。

公开(公告)号：US06717850B1

公开(公告)日：2004-04-06

申请号：US10313676

申请日：2002-12-05

申请人： Jiang Li ,  Nian Yang ,  Zhigang Wang ,  John Jianshi Wang

发明人： Jiang Li ,  Nian Yang ,  Zhigang Wang ,  John Jianshi Wang

IPC分类号： G11C1604

CPC分类号： G11C29/50 ,  G11C16/04 ,  G11C2029/0403

摘要： A method of processing a semiconductor device is disclosed and comprises applying a relatively high voltage across a gate stack of a flash memory cell for a certain period of time. Then, the polarity of the applied voltage is reversed and is again applied across the gate stack for another certain period of time. The voltage applied is greater than a channel erase voltage utilized for the memory cell. This applied voltage causes extrinsic defects to become amplified at interfaces of oxide/insulator layers of the gate stack. Then, the memory cell is tested (e.g., via a battery of tests) in order to determine if the memory cell is defective. If the cell is defective (e.g., fails the test), it can be assumed that substantial extrinsic defects were present in the memory cell and have been amplified resulting in the test failure. If the cell passes the test, it can be assumed that the memory cell is substantially free from extrinsic defects. Defective memory cells/devices can be marked or otherwise indicated as being defective.

摘要翻译： 公开了一种处理半导体器件的方法，并且包括在闪存单元的栅极堆叠上施加相当高的电压一段时间。 然后，施加的电压的极性反转，并再次施加在栅极堆叠另外一段时间。 施加的电压大于用于存储器单元的通道擦除电压。 该施加的电压导致外部缺陷在栅极堆叠的氧化物/绝缘体层的界面处被放大。 然后，测试存储器单元（例如，通过测试电池），以便确定存储器单元是否有故障。 如果细胞有缺陷（例如，测试失败），则可以认为在存储单元中存在大量的外在缺陷并且被放大，导致测试失败。 如果单元通过测试，则可以认为存储单元基本上没有外在缺陷。 存储器单元/器件不良或可能被标记为有缺陷。

公开(公告)号：US06716710B1

公开(公告)日：2004-04-06

申请号：US10126207

申请日：2002-04-19

申请人： Hsiao-Han Thio ,  Nian Yang ,  Zhigang Wang

发明人： Hsiao-Han Thio ,  Nian Yang ,  Zhigang Wang

IPC分类号： H01L21336

CPC分类号： H01L29/6656 ,  H01L21/76224 ,  H01L21/823468 ,  H01L21/823481

摘要： A method of fabricating a semiconductor device. A first layer comprising a first material is deposited to a first thickness on a sidewall of a stacked gate. A second layer comprising a second material is deposited over the first layer. The second layer is deposited without the first layer being etched; hence, the first thickness is unchanged along the sidewall. The second layer is reduced to a second thickness along the sidewall. The first layer and the second layer in combination form a spacer along the sidewall that has a thickness corresponding to the first thickness and the second thickness. Thus, the spacer can be formed using a single etch, reducing the number of processing steps. In addition, the first layer protects shallow trench filler material from gouging during the etch.

摘要翻译： 一种制造半导体器件的方法。 包括第一材料的第一层在堆叠栅极的侧壁上沉积到第一厚度。 包含第二材料的第二层沉积在第一层上。 沉积第二层，而不蚀刻第一层; 因此，第一厚度沿侧壁不变。 第二层沿着侧壁被还原成第二厚度。 第一层和第二层组合形成沿着侧壁的间隔物，其具有对应于第一厚度和第二厚度的厚度。 因此，间隔物可以使用单一蚀刻形成，减少了处理步骤的数量。 此外，第一层在蚀刻期间保护浅沟槽填料材料免于气刨。

公开(公告)号：US06606273B1

公开(公告)日：2003-08-12

申请号：US10121140

申请日：2002-04-11

申请人： Xin Guo ,  Nian Yang ,  Zhigang Wang

发明人： Xin Guo ,  Nian Yang ,  Zhigang Wang

IPC分类号： G11C700

CPC分类号： G11C29/50004 ,  G11C16/04 ,  G11C29/006 ,  G11C29/50

摘要： Methods are disclosed for determining tunnel oxide reliability of flash memory devices in a wafer prior to sorting and packaging without damaging or stressing the devices. The methods comprise measuring an initial threshold voltage of a test cell having the same tunnel oxide as other flash cells on the wafer, applying an erase stress to the test cell for a first time period and a program stress to the test cell for a second time period, and measuring the final threshold voltage of the test cell. The difference between the initial and final threshold voltages is then used to determine or estimate the tunnel oxide reliability of the flash memory cells on the wafer.

摘要翻译： 公开了用于在分选和包装之前确定晶片中闪存器件的隧道氧化物可靠性的方法，而不会损坏或强调器件。 该方法包括测量具有与晶片上的其它闪存单元相同的隧道氧化物的测试单元的初始阈值电压，将第一时间段的擦除应力施加到测试单元上，并且向测试单元施加程序应力第二次 周期，并测量测试单元的最终阈值电压。 然后使用初始阈值电压和最终阈值电压之间的差异来确定或估计晶片上闪存单元的隧道氧化物可靠性。

公开(公告)号：US06864106B1

公开(公告)日：2005-03-08

申请号：US10217965

申请日：2002-08-12

申请人： Zhigang Wang ,  Nian Yang ,  Xin Guo

发明人： Zhigang Wang ,  Nian Yang ,  Xin Guo

IPC分类号： G01R31/26 ,  G11C29/50 ,  H01L21/66 ,  G01R27/28

CPC分类号： G11C29/50 ,  G01R31/2621 ,  G11C16/04 ,  G11C2029/5002

摘要： A method for detecting tunnel oxide encroachment on a memory device. In one method embodiment, the present invention applies a baseline voltage burst to a gate of the memory device. Next, the present embodiment generates a baseline performance distribution graph of bit line current as a function of gate voltage for the memory device. The present embodiment then applies a channel program voltage burst to the gate of the memory device. Moreover, the present embodiment generates a channel program performance distribution graph of bit line current as a function of gate voltage for the memory device. The present embodiment then applies a channel erase voltage burst to the gate of the memory device. Additionally, the present embodiment generates a channel erase performance distribution graph of bit line current as a function of gate voltage for the memory device. A comparison of the channel program performance distribution graph and the channel erase performance distribution graph with respect to said baseline performance distribution graph is then performed. In so doing, an asymmetric distribution of the channel program performance distribution graph and the channel erase performance distribution graph with respect to the baseline performance distribution indicates tunnel oxide encroachment.

摘要翻译： 一种用于检测存储器件上的隧道氧化物侵蚀的方法。 在一个方法实施例中，本发明将基线电压脉冲串应用于存储器件的栅极。 接下来，本实施例生成作为存储器件的栅极电压的函数的位线电流的基线性能分布图。 本实施例然后将通道编程电压脉冲串施加到存储器件的栅极。 此外，本实施例产生作为存储器件的栅极电压的函数的位线电流的通道程序性能分布图。 本实施例然后将通道擦除电压脉冲串施加到存储器件的栅极。 此外，本实施例产生作为存储器件的栅极电压的函数的位线电流的沟道擦除性能分布图。 然后执行频道节目性能分布图与信道擦除性能分布图相对于所述基线性能分布图的比较。 在这样做时，相对于基线性能分布，信道节目性能分布图和信道擦除性能分布图的不对称分布表示隧道氧化物侵蚀。

公开(公告)号：US06461905B1

公开(公告)日：2002-10-08

申请号：US10081246

申请日：2002-02-22

申请人： Zhigang Wang ,  Hsiao Han Thio ,  Nian Yang

发明人： Zhigang Wang ,  Hsiao Han Thio ,  Nian Yang

IPC分类号： H01L21338

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/511

摘要： One aspect of the invention relates to a method of manufacturing a flash memory device in which Vss lines are salicided prior to forming memory cell stacks. According to the invention, silicide is aligned to the Vss lines by a layer of temporary material, such as a silicon nitride layer, patterned to form dummy gates. A dielectric layer can be deposited and planarized with the dummy gates prior to their removal. The dielectric layer facilitates selective removal of the dummy gates and formation of memory cell stacks that are properly aligned with the Vss lines and drain regions. The dummy gate concept can be used with methods of forming low resistance Vss lines other than saliciding. One advantage of the invention is that the memory cell stacks are not exposed to high temperature processing used in forming low resistance Vss lines.

摘要翻译： 本发明的一个方面涉及一种制造闪存器件的方法，其中在形成存储单元堆栈之前，Vss线被浸渍。 根据本发明，硅化物通过图案化以形成伪栅极的诸如氮化硅层的临时材料层与Vss线对准。 介电层可以在其去除之前与虚拟栅极沉积并平坦化。 电介质层有助于选择性地去除伪栅极并形成与Vss线和漏极区正确对准的存储单元堆叠。 虚拟栅极概念可以用于形成除了防水之外的低电阻Vss线的方法。 本发明的一个优点是存储单元堆不暴露于用于形成低电阻Vss线的高温处理。