公开(公告)号：US06292521B1

公开(公告)日：2001-09-18

申请号：US09150365

申请日：1998-09-09

申请人： Jiin Lai ,  Hsin-Chieh Lin ,  Fang-Yi Chen

发明人： Jiin Lai ,  Hsin-Chieh Lin ,  Fang-Yi Chen

IPC分类号： H04L700

CPC分类号： H04L7/0338 ,  H03L7/0805 ,  H03L7/0814 ,  H04L7/0008 ,  H04L7/0033

摘要： A phase lock device and method applicable to a data transmission system, particularly to a high speed transmission system are provided. Based on that the optimum operation margin for delaying data strobe is to shift the edge of data strobe to the middle region of data signal, the phase lock device and method suggest a solution, by analyzing the influence of environmental and operational conditions on delaying data strobe and system clock, to adapt delay element to the variation of environmental and operational conditions, so that the delay of data strobe is always in such a range that the data receiver can be enabled to do accurate and reliable data reading, regardless of external interference.

摘要翻译： 提供一种适用于数据传输系统，特别是高速传输系统的锁相装置和方法。 基于数据选通延迟的最佳运行余量是将数据选通的边沿移动到数据信号的中间区域，相位锁定装置和方法通过分析环境和运行条件对延迟数据选通的影响来提出解决方案 和系统时钟，以使延迟元件适应环境和操作条件的变化，使得数据选通的延迟总是处于使数据接收器能够进行精确和可靠的数据读取的范围，而不管外部干扰如何。

公开(公告)号：US06233528B1

公开(公告)日：2001-05-15

申请号：US09148949

申请日：1998-09-08

申请人： Jiin Lai ,  Jyhfong Lin ,  Hsin-Chieh Lin

发明人： Jiin Lai ,  Jyhfong Lin ,  Hsin-Chieh Lin

IPC分类号： G01R1300

CPC分类号： G01R31/31709 ,  G01R31/3016

摘要： A signal-testing device used with a tester for testing a first signal and a second signal includes a selected signal generator receiving first signal and second signal for generating a selected signal the state of which is changed when first signal and second signal are in specific states, and a signal selector for selectively outputting one of first and second signals in response to the selected signal state. The present invention also provides a signal-testing method including steps of a) generating a selected signal having a plurality of pulses in response to a first signal and a second signal, b) obtaining a plurality of time differences between times when two inter-adjacent respective pulses respectively reach a specific voltage, c) obtaining a plurality of absolute values between two inter-adjacent respective time differences, and d) obtaining a phase difference by dividing by 2 an average value of the absolute values.

摘要翻译： 与用于测试第一信号和第二信号的测试仪一起使用的信号测试装置包括接收第一信号的选择信号发生器和用于产生当第一信号和第二信号处于特定状态时其状态改变的选择信号的第二信号 以及信号选择器，用于响应于所选择的信号状态选择性地输出第一和第二信号之一。 本发明还提供了一种信号测试方法，包括以下步骤：a）响应于第一信号和第二信号产生具有多个脉冲的选定信号，b）获得两个相邻时间之间的多个时间差 各个脉冲分别达到特定电压，c）在两个相邻的相应时间差之间获得多个绝对值，以及d）通过将绝对值的平均值除以2来获得相位差。

公开(公告)号：US06687320B1

公开(公告)日：2004-02-03

申请号：US09322072

申请日：1999-05-27

申请人： You-Ming Chiu ,  Jiin Lai ,  Jyhfong Lin ,  Hsin-Chieh Lin ,  Wei-Yu Wang

发明人： You-Ming Chiu ,  Jiin Lai ,  Jyhfong Lin ,  Hsin-Chieh Lin ,  Wei-Yu Wang

IPC分类号： H03D324

CPC分类号： H03L7/081 ,  G06F1/08 ,  G06F1/10 ,  H03L7/18

摘要： A phase lock loop (PLL) clock generator with programmable frequency and skew is provided in the present invention, in which frequency of clock signals generated can be dynamically changed and skew of the clock signals generated can be dynamically adjusted by a computer program. Also, the signal skew due to the change of loading can be compensated. Therefore, the PLL clock generator based on a closed-loop configuration can better control the skew of clock signals to provide higher stability and durability to the system.

摘要翻译： 在本发明中提供了具有可编程频率和偏斜的锁相环（PLL）时钟发生器，其中产生的时钟信号的频率可以被动态地改变，并且可以通过计算机程序动态地调整产生的时钟信号的偏移。 此外，可以补偿由于负载变化引起的信号偏移。 因此，基于闭环配置的PLL时钟发​​生器可以更好地控制时钟信号的偏斜，为系统提供更高的稳定性和耐久性。

公开(公告)号：US06400197B2

公开(公告)日：2002-06-04

申请号：US09766952

申请日：2001-01-22

申请人： Jiin Lai ,  Hsin-Chieh Lin ,  Kuo-Ping Liu

发明人： Jiin Lai ,  Hsin-Chieh Lin ,  Kuo-Ping Liu

IPC分类号： H03L700

CPC分类号： G06F5/06 ,  G06F1/10 ,  G06F2205/104 ,  H03L7/0814

摘要： A signal delay device having an internal delay lock loop for calibrating the delay interval. The signal delay device receives an input signal and then outputs the signal after a pre-defined delay period. The input signal varies according to a reference clock signal, and the required delay period is a quarter cycle of the clock signal. The delay device includes a multiplexer, an inverter, a phase detector, a counter and a delay element. During calibration, the phase detector, the counter and the delay element form a delay lock loop that can set up the delay time automatically.

摘要翻译： 一种具有用于校准延迟间隔的内部延迟锁定环路的信号延迟装置。 信号延迟装置接收输入信号，然后在预定义的延迟周期之后输出信号。 输入信号根据参考时钟信号而变化，所需的延迟周期是时钟信号的四分之一周期。 延迟装置包括多路复用器，反相器，相位检测器，计数器和延迟元件。 在校准期间，相位检测器，计数器和延迟元件形成可以自动设置延迟时间的延迟锁定环。

公开(公告)号：US08174573B2

公开(公告)日：2012-05-08

申请号：US12204871

申请日：2008-09-05

申请人： Hsin-Chieh Lin ,  Julian Lin

发明人： Hsin-Chieh Lin ,  Julian Lin

IPC分类号： H04N7/18

CPC分类号： H04N5/2252 ,  G08B13/19619

摘要： A monitoring camera has a base, a camera module and a casing. The base has a parapet formed on the base. The parapet has a memory slot and at least one pair of guide slots formed oppositely on the parapet. Each guide slot has a notch extending toward the bottom of the parapet. The casing corresponds to and covers the parapet and has at least one pair of guide protrusions formed on the casing. The guide protrusions respectively engage corresponding guide slots. When unscrewing the casing, the guide protrusions will correspondingly move and be mounted in the notches and the memory slot is accessible. Therefore, the casing need not to be completely detached from the base to allow a removable memory to be installed or removed easily.

摘要翻译： 监控摄像机具有基座，相机模块和外壳。 基地有一个在基地形成的护栏。 护栏具有存储槽和在栏杆上相对形成的至少一对引导槽。 每个导槽具有向栏杆底部延伸的凹口。 壳体对应于并且覆盖栏杆并且具有形成在壳体上的至少一对引导突起。 引导突起分别接合相应的引导槽。 当旋转外壳时，引导突起将相应地移动并安装在凹口中，并且存储器插槽可接近。 因此，壳体不需要从基座完全分离，从而容易地安装或移除可移动存储器。

公开(公告)号：US20100060731A1

公开(公告)日：2010-03-11

申请号：US12204871

申请日：2008-09-05

申请人： Hsin-Chieh Lin ,  Julian Lin

发明人： Hsin-Chieh Lin ,  Julian Lin

IPC分类号： H04N7/18

CPC分类号： H04N5/2252 ,  G08B13/19619

摘要： A monitoring camera has a base, a camera module and a casing. The base has a parapet formed on the base. The parapet has a memory slot and at least one pair of guide slots formed oppositely on the parapet. Each guide slot has a notch extending toward the bottom of the parapet. The casing corresponds to and covers the parapet and has at least one pair of guide protrusions formed on the casing. The guide protrusions respectively engage corresponding guide slots. When unscrewing the casing, the guide protrusions will correspondingly move and be mounted in the notches and the memory slot is accessible. Therefore, the casing need not to be completely detached from the base to allow a removable memory to be installed or removed easily.

摘要翻译： 监控摄像机具有基座，相机模块和外壳。 基地有一个在基地形成的护栏。 护栏具有存储槽和在栏杆上相对形成的至少一对引导槽。 每个导槽具有向栏杆底部延伸的凹口。 壳体对应于并且覆盖栏杆并且具有形成在壳体上的至少一对引导突起。 引导突起分别接合相应的引导槽。 当旋转外壳时，引导突起将相应地移动并安装在凹口中，并且存储器插槽可接近。 因此，壳体不需要从基座完全分离，从而容易地安装或移除可移动存储器。

公开(公告)号：US07016450B2

公开(公告)日：2006-03-21

申请号：US10064215

申请日：2002-06-21

申请人： Jyh-Fong Lin ,  Hsin-Chieh Lin ,  Yi-Bin Hsieh

发明人： Jyh-Fong Lin ,  Hsin-Chieh Lin ,  Yi-Bin Hsieh

IPC分类号： H03D3/24

CPC分类号： H03L7/0891 ,  H03L7/093 ,  H03L7/18

摘要： A clock recovery circuit for generating an output signal that is synchronized with an input signal. The clock recovery circuit includes a charge pump, a first filter, an oscillator, a switch circuit, and a second filter. When the charge pump operates, the switch circuit will disconnect the first filter from the oscillator. Additionally, when the charge pump stops operating, the switch circuit will connect the first filter and the oscillator such that the oscillator adjusts a frequency or phase of the output signal according to the output voltage of the first filter.

摘要翻译： 一种用于产生与输入信号同步的输出信号的时钟恢复电路。 时钟恢复电路包括电荷泵，第一滤波器，振荡器，开关电路和第二滤波器。 当电荷泵运行时，开关电路将使第一个滤波器与振荡器断开。 此外，当电荷泵停止工作时，开关电路将连接第一滤波器和振荡器，使得振荡器根据第一滤波器的输出电压来调节输出信号的频率或相位。

公开(公告)号：US6005426A

公开(公告)日：1999-12-21

申请号：US73746

申请日：1998-05-06

申请人： Jyhfong Lin ,  Hsin-Chieh Lin

发明人： Jyhfong Lin ,  Hsin-Chieh Lin

IPC分类号： H03L7/081 ,  H03L7/10 ,  H03L7/06

CPC分类号： H03L7/0814 ,  H03L7/10

摘要： A low-jitter delay locked loop having an expanded phase locking range without the necessity of setting the initial delay is provided. The loop is to be supplied by a system clock and includes a pulse generator receiving the system clock for generating a first pulse signal and a second pulse signal in response to a triggering signal, a delay device receiving the system clock for providing a delayed clock in response to a control signal, a frequency-reducing device for frequency-reducing the system clock into a first clock in response to the first pulse signal and frequency-reducing the delayed clock into a second clock in response to the second pulse signal, and a comparator for comparing the first and second clocks to generate the control signal.

摘要翻译： 提供具有扩展相位锁定范围的低抖动延迟锁定环，而不需要设置初始延迟。 该回路由系统时钟提供，并且包括接收用于响应于触发信号产生第一脉冲信号和第二脉冲信号的系统时钟的脉冲发生器，延迟装置接收用于提供延迟时钟的系统时钟 响应于控制信号的频率降低装置，用于响应于第一脉冲信号将系统时钟频率降低到第一时钟并响应于第二脉冲信号将延迟的时钟频率降低到第二时钟的频率降低装置，以及 比较器，用于比较第一和第二时钟以产生控制信号。

公开(公告)号：US07106235B1

公开(公告)日：2006-09-12

申请号：US11139475

申请日：2005-05-31

申请人： Ming-Chou Yen ,  Hsin-Chieh Lin ,  Kun-Ying Tsai ,  Jui-Tai Ko ,  Chun-Wang Wei

发明人： Ming-Chou Yen ,  Hsin-Chieh Lin ,  Kun-Ying Tsai ,  Jui-Tai Ko ,  Chun-Wang Wei

IPC分类号： H03M1/66

CPC分类号： H04B1/58 ,  H04B3/03

摘要： An active hybrid circuit for a full duplex channel generates a duplicated voltage at the current output stage to reduce the energy of the transmitter transmitted to the receiver. The active hybrid circuit cancels the energy of the transmitter transmitted to the receiver when it is operated in a full duplex channel with high-speed transmission. The active hybrid circuit for full a duplex channel comprises a transmit digital-to-analog converter for generating an analog transmit signal, a receive analog-to-digital converter for receiving an analog receive signal, a duplicated voltage digital-to-analog converter for generating a corresponding duplicated voltage according to the analog transmit signal of the transmit digital-to-analog converter, and a plurality of signal combiners for subtracting the duplicated voltage from the analog transmit signal to cancel the influence of analog transmit signal to the analog receive signal.

摘要翻译： 用于全双工信道的主动混合电路在当前输出级产生复制电压，以减少发送到接收机的发射机的能量。 当主动混合电路在具有高速传输的全双工信道中工作时，消除发射到接收机的发射机的能量。 用于全双工通道的主动混合电路包括用于产生模拟发射信号的发射数模转换器，用于接收模拟接收信号的接收模数转换器，用于接收模拟接收信号的复制电压数/模转换器， 根据发射数模转换器的模拟发射信号产生相应的重复电压，以及多个信号组合器，用于从模拟发射信号中减去复制电压，以消除模拟发射信号对模拟接收信号的影响 。

公开(公告)号：US06859027B2

公开(公告)日：2005-02-22

申请号：US10064767

申请日：2002-08-15

申请人： Sung-Hung Li ,  Steven Su ,  Hsin-Chieh Lin

发明人： Sung-Hung Li ,  Steven Su ,  Hsin-Chieh Lin

IPC分类号： H03D13/00 ,  H03L7/089 ,  G01R23/12

CPC分类号： H03L7/089 ,  H03D13/004 ,  H03L7/0891

摘要： A device and method for measuring the jitters of phase locked loop signals. A phase lead or phase lag relationship between an input signal and an output signal of a phase locked loop is found. According to the phase relationship and using multiplexers, a first phase difference signal and a second phase difference signal are re-routed to a subtraction unit and produces a jitter-level output signal. The jitter-level output signal represents the absolute value of the difference of pulse width between the first phase difference signal and the second phase difference signal.

摘要翻译： 一种用于测量锁相环信号抖动的装置和方法。 发现输入信号和锁相环路的输出信号之间的相位相位或相位滞后关系。 根据相位关系和使用多路复用器，将第一相位差信号和第二相位差信号重新路由到减法单元并产生抖动电平输出信号。 抖动电平输出信号表示第一相位差信号和第二相位差信号之间的脉冲宽度差的绝对值。