公开(公告)号：US06233528B1

公开(公告)日：2001-05-15

申请号：US09148949

申请日：1998-09-08

申请人： Jiin Lai ,  Jyhfong Lin ,  Hsin-Chieh Lin

发明人： Jiin Lai ,  Jyhfong Lin ,  Hsin-Chieh Lin

IPC分类号： G01R1300

CPC分类号： G01R31/31709 ,  G01R31/3016

摘要： A signal-testing device used with a tester for testing a first signal and a second signal includes a selected signal generator receiving first signal and second signal for generating a selected signal the state of which is changed when first signal and second signal are in specific states, and a signal selector for selectively outputting one of first and second signals in response to the selected signal state. The present invention also provides a signal-testing method including steps of a) generating a selected signal having a plurality of pulses in response to a first signal and a second signal, b) obtaining a plurality of time differences between times when two inter-adjacent respective pulses respectively reach a specific voltage, c) obtaining a plurality of absolute values between two inter-adjacent respective time differences, and d) obtaining a phase difference by dividing by 2 an average value of the absolute values.

摘要翻译： 与用于测试第一信号和第二信号的测试仪一起使用的信号测试装置包括接收第一信号的选择信号发生器和用于产生当第一信号和第二信号处于特定状态时其状态改变的选择信号的第二信号 以及信号选择器，用于响应于所选择的信号状态选择性地输出第一和第二信号之一。 本发明还提供了一种信号测试方法，包括以下步骤：a）响应于第一信号和第二信号产生具有多个脉冲的选定信号，b）获得两个相邻时间之间的多个时间差 各个脉冲分别达到特定电压，c）在两个相邻的相应时间差之间获得多个绝对值，以及d）通过将绝对值的平均值除以2来获得相位差。

公开(公告)号：US06687320B1

公开(公告)日：2004-02-03

申请号：US09322072

申请日：1999-05-27

申请人： You-Ming Chiu ,  Jiin Lai ,  Jyhfong Lin ,  Hsin-Chieh Lin ,  Wei-Yu Wang

发明人： You-Ming Chiu ,  Jiin Lai ,  Jyhfong Lin ,  Hsin-Chieh Lin ,  Wei-Yu Wang

IPC分类号： H03D324

CPC分类号： H03L7/081 ,  G06F1/08 ,  G06F1/10 ,  H03L7/18

摘要： A phase lock loop (PLL) clock generator with programmable frequency and skew is provided in the present invention, in which frequency of clock signals generated can be dynamically changed and skew of the clock signals generated can be dynamically adjusted by a computer program. Also, the signal skew due to the change of loading can be compensated. Therefore, the PLL clock generator based on a closed-loop configuration can better control the skew of clock signals to provide higher stability and durability to the system.

摘要翻译： 在本发明中提供了具有可编程频率和偏斜的锁相环（PLL）时钟发生器，其中产生的时钟信号的频率可以被动态地改变，并且可以通过计算机程序动态地调整产生的时钟信号的偏移。 此外，可以补偿由于负载变化引起的信号偏移。 因此，基于闭环配置的PLL时钟发​​生器可以更好地控制时钟信号的偏斜，为系统提供更高的稳定性和耐久性。

公开(公告)号：US06400197B2

公开(公告)日：2002-06-04

申请号：US09766952

申请日：2001-01-22

申请人： Jiin Lai ,  Hsin-Chieh Lin ,  Kuo-Ping Liu

发明人： Jiin Lai ,  Hsin-Chieh Lin ,  Kuo-Ping Liu

IPC分类号： H03L700

CPC分类号： G06F5/06 ,  G06F1/10 ,  G06F2205/104 ,  H03L7/0814

摘要： A signal delay device having an internal delay lock loop for calibrating the delay interval. The signal delay device receives an input signal and then outputs the signal after a pre-defined delay period. The input signal varies according to a reference clock signal, and the required delay period is a quarter cycle of the clock signal. The delay device includes a multiplexer, an inverter, a phase detector, a counter and a delay element. During calibration, the phase detector, the counter and the delay element form a delay lock loop that can set up the delay time automatically.

摘要翻译： 一种具有用于校准延迟间隔的内部延迟锁定环路的信号延迟装置。 信号延迟装置接收输入信号，然后在预定义的延迟周期之后输出信号。 输入信号根据参考时钟信号而变化，所需的延迟周期是时钟信号的四分之一周期。 延迟装置包括多路复用器，反相器，相位检测器，计数器和延迟元件。 在校准期间，相位检测器，计数器和延迟元件形成可以自动设置延迟时间的延迟锁定环。

公开(公告)号：US06292521B1

公开(公告)日：2001-09-18

申请号：US09150365

申请日：1998-09-09

申请人： Jiin Lai ,  Hsin-Chieh Lin ,  Fang-Yi Chen

发明人： Jiin Lai ,  Hsin-Chieh Lin ,  Fang-Yi Chen

IPC分类号： H04L700

CPC分类号： H04L7/0338 ,  H03L7/0805 ,  H03L7/0814 ,  H04L7/0008 ,  H04L7/0033

摘要： A phase lock device and method applicable to a data transmission system, particularly to a high speed transmission system are provided. Based on that the optimum operation margin for delaying data strobe is to shift the edge of data strobe to the middle region of data signal, the phase lock device and method suggest a solution, by analyzing the influence of environmental and operational conditions on delaying data strobe and system clock, to adapt delay element to the variation of environmental and operational conditions, so that the delay of data strobe is always in such a range that the data receiver can be enabled to do accurate and reliable data reading, regardless of external interference.

摘要翻译： 提供一种适用于数据传输系统，特别是高速传输系统的锁相装置和方法。 基于数据选通延迟的最佳运行余量是将数据选通的边沿移动到数据信号的中间区域，相位锁定装置和方法通过分析环境和运行条件对延迟数据选通的影响来提出解决方案 和系统时钟，以使延迟元件适应环境和操作条件的变化，使得数据选通的延迟总是处于使数据接收器能够进行精确和可靠的数据读取的范围，而不管外部干扰如何。

公开(公告)号：US08781332B2

公开(公告)日：2014-07-15

申请号：US13018548

申请日：2011-02-01

申请人： Jin-Kuan Tang ,  Jiin Lai

发明人： Jin-Kuan Tang ,  Jiin Lai

IPC分类号： H04B10/00

CPC分类号： H04B10/40

摘要： An optical transceiver module adapted to a link device includes a connection unit, a driving unit and optical transmitting and receiving units. The connection unit, to be coupled with the link device, includes an indicating element for generating an indicating signal when the connection unit is coupled with the link device. The driving unit, coupled with the connection unit, receives the indicating signal and outputs a control signal according to the indicating signal. The optical transmitting unit, coupled with the driving unit, receives the control signal for driving the optical transmitting unit to output a first optical signal. The optical receiving unit, coupled with the driving unit, transmits a received second optical signal to the driving unit. An optical transmission device using the optical transceiver module, and an optical transmission method are also disclosed. A link training sequence can be initiated after the connection unit is actually coupled with the link device. Thus, a host cannot enter a disable mode due to error connection.

摘要翻译： 适于链接装置的光收发模块包括连接单元，驱动单元和光发射和接收单元。 要与链接装置耦合的连接单元包括用于当连接单元与链接装置耦合时产生指示信号的指示元件。 与连接单元耦合的驱动单元接收指示信号，并根据指示信号输出控制信号。 与驱动单元耦合的光发送单元接收用于驱动光发送单元的控制信号以输出第一光信号。 光接收单元与驱动单元耦合，将接收到的第二光信号发送到驱动单元。 还公开了使用光收发模块的光传输装置和光传输方法。 链路训练序列可以在连接单元实际上与链路设备耦合之后启动。 因此，由于错误连接，主机无法进入禁用模式。

公开(公告)号：US08549184B2

公开(公告)日：2013-10-01

申请号：US12959299

申请日：2010-12-02

申请人： Jinkuan Tang ,  Jiin Lai ,  Buheng Xu ,  Hui Jiang

发明人： Jinkuan Tang ,  Jiin Lai ,  Buheng Xu ,  Hui Jiang

IPC分类号： G06F3/00 ,  G06F13/12

CPC分类号： G06F13/385

摘要： The present invention is directed to a universal serial bus (USB) transaction translator and an associated IN/OUT bulk transaction method. A device interface is coupled to a device via a device bus, and a host interface is coupled to a host via a host bus, wherein the host USB version is higher than the device USB version. At least two buffers configured to store data are disposed between the device interface and the host interface. A controller stores the data in the buffers alternately. In a bulk-IN transaction, before the host sends an IN packet, the controller pre-fetches data and stores the data in the buffers until all the buffers are full or a requested data length has been achieved; the pre-fetched data are then sent to the host after the host sends the IN packet. In a bulk-OUT transaction, the controller stores the data sent from the host in the buffers, and the data are then post-written to the device.

摘要翻译： 本发明涉及通用串行总线（USB）事务转换器和相关的IN / OUT批量交易方法。 设备接口经由设备总线耦合到设备，并且主机接口通过主机总线耦合到主机，其中主机USB版本高于设备USB版本。 配置为存储数据的至少两个缓冲器被布置在设备接口和主机接口之间。 控制器交替地将数据存储在缓冲器中。 在批量IN事务中，在主机发送IN数据包之前，控制器预取数据并将数据存储在缓冲器中，直到所有缓冲器已满或已达到所请求的数据长度为止; 在主机发送IN数据包之后，将预取的数据发送到主机。 在bulk-OUT事务中，控制器将从主机发送的数据存储在缓冲区中，然后将数据写入设备。

公开(公告)号：US20110246681A1

公开(公告)日：2011-10-06

申请号：US12818342

申请日：2010-06-18

申请人： Jiin Lai

发明人： Jiin Lai

IPC分类号： G06F3/00 ,  G06F13/12

CPC分类号： G06F13/4081 ,  G06F2213/0042

摘要： An apparatus configured to couple to a universal serial bus (USB) 3.0 connector. The apparatus includes a management controller configured to couple to the USB 3.0 connector. The management controller is configured to detect from behavior on the D+ and D− pins of the USB 3.0 connector whether a device plugged into the USB 3.0 connector is a conventional USB 3.0 device or an optical USB device.

摘要翻译： 一种被配置为耦合到通用串行总线（USB）3.0连接器的装置。 该装置包括配置成耦合到USB 3.0连接器的管理控制器。 管理控制器配置为检测USB 3.0连接器的D +和D-引脚上的行为，连接USB 3.0连接器的设备是传统的USB 3.0设备还是光学USB设备。

公开(公告)号：US20110219272A1

公开(公告)日：2011-09-08

申请号：US12862134

申请日：2010-08-24

申请人： Jiin Lai ,  Buheng Xu ,  Jinkuan Tang

发明人： Jiin Lai ,  Buheng Xu ,  Jinkuan Tang

IPC分类号： G06F11/08 ,  G06F13/00 ,  G06F13/12

CPC分类号： G06F13/385 ,  G06F11/08 ,  G06F13/00 ,  G06F13/12

摘要： A data transmission system is provided. The data transmission system includes a first control circuit coupled to a first device, a translation circuit coupled to the first control circuit and a second control circuit coupled to the translation circuit. The first control circuit decodes a first format data packet sent by the first device. The translation circuit receives the decoded first format data packet and translates the decoded first format data packet into a second format data packet. The second control circuit transmits the second format data packet to a host. A data transmission rate of the first device is slower than that of a second device, and the data transmission system is backward compatible to the first device.

摘要翻译： 提供数据传输系统。 数据传输系统包括耦合到第一设备的第一控制电路，耦合到第一控制电路的平移电路和耦合到转换电路的第二控制电路。 第一控制电路解码由第一设备发送的第一格式数据分组。 翻译电路接收解码的第一格式数据分组，并将解码的第一格式数据分组转换为第二格式数据分组。 第二控制电路将第二格式数据包发送到主机。 第一设备的数据传输速率比第二设备的数据传输速率慢，并且数据传输系统向后兼容于第一设备。

公开(公告)号：US07805567B2

公开(公告)日：2010-09-28

申请号：US11854576

申请日：2007-09-13

申请人： Chun-Yuan Su ,  Chau-Chad Tsai ,  Jiin Lai

发明人： Chun-Yuan Su ,  Chau-Chad Tsai ,  Jiin Lai

IPC分类号： G06F12/00

CPC分类号： G06F13/4027 ,  G06F11/1076 ,  G06F2211/1054

摘要： A Northbridge providing RAID access is coupled among a central processing unit, a system memory, and a Southbridge. Furthermore, the Northbridge further couples to a RAID through a Southbridge. The Northbridge include a RAID accelerator for performing RAID operations according to RAID control commands which are stored in a register.

摘要翻译： 在中央处理单元，系统存储器和南桥之间耦合提供RAID访问的北桥。 此外，北桥通过南桥进一步融合到RAID。 北桥包含RAID加速器，用于根据存储在寄存器中的RAID控制命令进行RAID操作。

公开(公告)号：US07271578B2

公开(公告)日：2007-09-18

申请号：US11131401

申请日：2005-05-18

申请人： Hung Yi Kuo ,  Jenny Chen ,  Jiin Lai

发明人： Hung Yi Kuo ,  Jenny Chen ,  Jiin Lai

IPC分类号： G01R17/06

CPC分类号： G01R19/16552

摘要： A voltage monitoring circuit is capable of being integrated into a chip and monitoring the voltage quality. It mainly uses a first waveshaper to receive a voltage signal of a voltage source to be measured, process it to a logic signal, and output to a first logic level transformer. A first digital signal is transformed by the processing and can be recorded by a register such that a managing system can read content of the register through a bus to further determine whether the voltage source has a situation of voltage surge. Similarly, an inverter can be concatenated between a second waveshaper and a second logic level transformer to monitor whether the voltage source has undercurrent pulse. This way, an object of monitoring voltage quality in the chip with a combination of simple analog circuit can be achieved.

摘要翻译： 电压监测电路能够集成到芯片中并监测电压质量。 它主要使用第一个波形器接收要测量的电压源的电压信号，将其处理为逻辑信号，并输出到第一逻辑电平变压器。 第一数字信号通过处理变换，并且可以由寄存器记录，使得管理系统可以通过总线读取寄存器的内容，以进一步确定电压源是否具有电压浪涌的情况。 类似地，逆变器可以连接在第二波形与第二逻辑电平变换器之间，以监测电压源是否具有欠电流脉冲。 这样，可以实现利用简单模拟电路的组合来监视芯片中的电压质量的目的。