公开(公告)号：US07601569B2

公开(公告)日：2009-10-13

申请号：US11761568

申请日：2007-06-12

申请人： Jin Cai ,  Wilfried Haensch ,  Amlan Majumdar

发明人： Jin Cai ,  Wilfried Haensch ,  Amlan Majumdar

IPC分类号： H01L21/335 ,  H01L21/00 ,  H01L21/338 ,  H01L21/8234

CPC分类号： H01L29/78696 ,  H01L29/458 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78624

摘要： Source and drain extension regions and source side halo region and drain side halo region are formed in a top semiconductor layer aligned with a gate stack on an SOI substrate. A deep source region and a deep drain region are formed asymmetrically in the top semiconductor layer by an angled ion implantation. The deep source region is offset away from one of the outer edges of the at least spacer to expose the source extension region on the surface of the semiconductor substrate. A source metal semiconductor alloy is formed by reacting a metal layer with portions of the deep source region, the source extension region, and the source side halo region. The source metal semiconductor alloy abuts the remaining portion of the source side halo region, providing a body contact tied to the deep source region to the partially depleted SOI MOSFET.

摘要翻译： 源极和漏极延伸区域和源极侧卤素区域和漏极侧晕圈形成在与SOI衬底上的栅极堆叠对准的顶部半导体层中。 通过成角度的离子注入，在顶部半导体层中不均匀地形成深源区和深漏区。 深源区域远离至少间隔物的外缘之一偏离以暴露半导体衬底的表面上的源延伸区域。 源金属半导体合金通过使金属层与深源区，源极延伸区和源极侧晕区的一部分反应而形成。 源极金属半导体合金与源极侧光晕区域的剩余部分相邻，从而将与源极区域连接的体接触部分连接到部分耗尽的SOI MOSFET。

公开(公告)号：US07919812B2

公开(公告)日：2011-04-05

申请号：US12554344

申请日：2009-09-04

申请人： Jin Cai ,  Wilfried Haensch ,  Amlan Majumdar

发明人： Jin Cai ,  Wilfried Haensch ,  Amlan Majumdar

IPC分类号： H01L21/70 ,  H01K29/60

CPC分类号： H01L29/78696 ,  H01L29/458 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78624

摘要： Source and drain extension regions and source side halo region and drain side halo region are formed in a top semiconductor layer aligned with a gate stack on an SOI substrate. A deep source region and a deep drain region are formed asymmetrically in the top semiconductor layer by an angled ion implantation. The deep source region is offset away from one of the outer edges of the at least spacer to expose the source extension region on the surface of the semiconductor substrate. A source metal semiconductor alloy is formed by reacting a metal layer with portions of the deep source region, the source extension region, and the source side halo region. The source metal semiconductor alloy abuts the remaining portion of the source side halo region, providing a body contact tied to the deep source region to the partially depleted SOI MOSFET.

摘要翻译： 源极和漏极延伸区域和源极侧卤素区域和漏极侧晕圈形成在与SOI衬底上的栅极堆叠对准的顶部半导体层中。 通过成角度的离子注入，在顶部半导体层中不均匀地形成深源区和深漏区。 深源区域远离至少间隔物的外缘之一偏离以暴露半导体衬底的表面上的源延伸区域。 源金属半导体合金通过使金属层与深源区，源极延伸区和源极侧晕区的一部分反应而形成。 源极金属半导体合金与源极侧光晕区域的剩余部分相邻，从而将与源极区域连接的体接触部分连接到部分耗尽的SOI MOSFET。

公开(公告)号：US20090321831A1

公开(公告)日：2009-12-31

申请号：US12554344

申请日：2009-09-04

申请人： Jin Cai ,  Wilfried Haensch ,  Amlan Majumdar

发明人： Jin Cai ,  Wilfried Haensch ,  Amlan Majumdar

IPC分类号： H01L29/786

CPC分类号： H01L29/78696 ,  H01L29/458 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78624

摘要： Source and drain extension regions and source side halo region and drain side halo region are formed in a top semiconductor layer aligned with a gate stack on an SOI substrate. A deep source region and a deep drain region are formed asymmetrically in the top semiconductor layer by an angled ion implantation. The deep source region is offset away from one of the outer edges of the at least spacer to expose the source extension region on the surface of the semiconductor substrate. A source metal semiconductor alloy is formed by reacting a metal layer with portions of the deep source region, the source extension region, and the source side halo region. The source metal semiconductor alloy abuts the remaining portion of the source side halo region, providing a body contact tied to the deep source region to the partially depleted SOI MOSFET.

摘要翻译： 源极和漏极延伸区域和源极侧卤素区域和漏极侧晕圈形成在与SOI衬底上的栅极堆叠对准的顶部半导体层中。 通过成角度的离子注入，在顶部半导体层中不均匀地形成深源区和深漏区。 深源区域远离至少间隔物的外缘之一偏离以暴露半导体衬底的表面上的源延伸区域。 源金属半导体合金通过使金属层与深源区，源极延伸区和源极侧晕区的一部分反应而形成。 源极金属半导体合金与源极侧光晕区域的剩余部分相邻，从而将与源极区域连接的体接触部分连接到部分耗尽的SOI MOSFET。

公开(公告)号：US20080308867A1

公开(公告)日：2008-12-18

申请号：US11761568

申请日：2007-06-12

申请人： Jin Cai ,  Wilfried Haensch ,  Amlan Majumdar

发明人： Jin Cai ,  Wilfried Haensch ,  Amlan Majumdar

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/78696 ,  H01L29/458 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78624

摘要： Source and drain extension regions and source side halo region and drain side halo region are formed in a top semiconductor layer aligned with a gate stack on an SOI substrate. A deep source region and a deep drain region are formed asymmetrically in the top semiconductor layer by an angled ion implantation. The deep source region is offset away from one of the outer edges of the at least spacer to expose the source extension region on the surface of the semiconductor substrate. A source metal semiconductor alloy is formed by reacting a metal layer with portions of the deep source region, the source extension region, and the source side halo region. The source metal semiconductor alloy abuts the remaining portion of the source side halo region, providing a body contact tied to the deep source region to the partially depleted SOI MOSFET.

摘要翻译： 源极和漏极延伸区域和源极侧卤素区域和漏极侧晕圈形成在与SOI衬底上的栅极堆叠对准的顶部半导体层中。 通过成角度的离子注入，在顶部半导体层中不均匀地形成深源区和深漏区。 深源区域远离至少间隔物的外缘之一偏离以暴露半导体衬底的表面上的源延伸区域。 源金属半导体合金通过使金属层与深源区，源极延伸区和源极侧晕区的一部分反应而形成。 源极金属半导体合金与源极侧光晕区域的剩余部分相邻，从而将与源极区域连接的体接触部分连接到部分耗尽的SOI MOSFET。

公开(公告)号：US09178061B2

公开(公告)日：2015-11-03

申请号：US13572039

申请日：2012-08-10

申请人： Jin Cai ,  Steven J. Koester ,  Amlan Majumdar

发明人： Jin Cai ,  Steven J. Koester ,  Amlan Majumdar

IPC分类号： H01L21/28 ,  H01L21/44 ,  H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L29/0847 ,  H01L29/41733 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/78612 ,  H01L29/78621

摘要： A method is provided for fabricating a semiconductor device. According to the method, a semiconductor layer is formed over a semiconductor-on-insulator substrate, and a gate is formed on the semiconductor layer. Source and drain extension regions and a deep drain region are formed in the semiconductor layer. A deep source region is formed in the semiconductor layer. A drain metal-semiconductor alloy contact is located on the upper portion of the deep drain region and abutting the drain extension region. A source metal-semiconductor alloy contact abuts the source extension region. The deep source region is located below and contacts a first portion of the source metal-semiconductor alloy contact. The deep source region is not located below and does not contact a second portion of the source metal-semiconductor alloy contact. The second portion of the source metal-semiconductor alloy contact is an internal body contact that directly contacts the semiconductor layer.

摘要翻译： 提供了制造半导体器件的方法。 根据该方法，在绝缘体上半导体基板上形成半导体层，在半导体层上形成栅极。 源极和漏极延伸区域和深的漏极区域形成在半导体层中。 在半导体层中形成深源区。 漏极金属 - 半导体合金触点位于深漏区域的上部并邻接漏极延伸区域。 源极金属 - 半导体合金接触件邻接源极延伸区域。 深源区域位于源极金属 - 半导体合金接触件的第一部分下方并接触。 深源区不位于源极金属 - 半导体合金触点的第二部分下方并且不接触。 源极金属 - 半导体合金触点的第二部分是直接接触半导体层的内部主体接触。

公开(公告)号：US08766410B2

公开(公告)日：2014-07-01

申请号：US13153806

申请日：2011-06-06

申请人： Jin Cai ,  Josephine Chang ,  Leland Chang ,  Brian L. Ji ,  Steven John Koester ,  Amlan Majumdar

发明人： Jin Cai ,  Josephine Chang ,  Leland Chang ,  Brian L. Ji ,  Steven John Koester ,  Amlan Majumdar

IPC分类号： H01L23/58

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/10894

摘要： Integrated circuits having combined memory and logic functions are provided. In one aspect, an integrated circuit is provided. The integrated circuit comprises: a substrate comprising a silicon layer over a BOX layer, wherein a select region of the silicon layer has a thickness of between about three nanometers and about 20 nanometers; at least one eDRAM cell comprising: at least one pass transistor having a pass transistor source region, a pass transistor drain region and a pass transistor channel region formed in the select region of the silicon layer; and a capacitor electrically connected to the pass transistor.

摘要翻译： 提供具有组合的存储器和逻辑功能的集成电路。 一方面，提供集成电路。 集成电路包括：衬底，其包括在BOX层上的硅层，其中硅层的选择区域具有在约3纳米和约20纳米之间的厚度; 至少一个eDRAM单元包括：至少一个传输晶体管，其具有形成在所述硅层的所述选择区域中的传输晶体管源极区域，传输晶体管漏极区域和传输晶体管沟道区域; 以及电连接到传输晶体管的电容器。

公开(公告)号：US08314463B2

公开(公告)日：2012-11-20

申请号：US12542879

申请日：2009-08-18

申请人： Jin Cai ,  Amlan Majumdar ,  Tak H. Ning ,  Zhibin Ren

发明人： Jin Cai ,  Amlan Majumdar ,  Tak H. Ning ,  Zhibin Ren

IPC分类号： H01L27/12

CPC分类号： H01L29/1083 ,  H01L21/28052 ,  H01L21/28088 ,  H01L21/28247 ,  H01L29/165 ,  H01L29/4933 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A method is provided to fabricate a semiconductor device, where the method includes providing a substrate comprised of crystalline silicon; implanting a ground plane in the crystalline silicon so as to be adjacent to a surface of the substrate, the ground plane being implanted to exhibit a desired super-steep retrograde well (SSRW) implant doping profile; annealing implant damage using a substantially diffusionless thermal annealing to maintain the desired super-steep retrograde well implant doping profile in the crystalline silicon and, prior to performing a shallow trench isolation process, depositing a silicon cap layer over the surface of the substrate. The substrate may be a bulk Si substrate or a Si-on-insulator substrate. The method accommodates the use of an oxynitride gate stack structure or a high dielectric constant oxide/metal (high-K/metal) gate stack structure. The various thermal processes used during fabrication are selected/controlled so as to maintain the desired super-steep retrograde well implant doping profile in the crystalline silicon.

公开(公告)号：US07985633B2

公开(公告)日：2011-07-26

申请号：US11929943

申请日：2007-10-30

申请人： Jin Cai ,  Josephine Chang ,  Leland Chang ,  Brian L. Ji ,  Steven John Koester ,  Amlan Majumdar

发明人： Jin Cai ,  Josephine Chang ,  Leland Chang ,  Brian L. Ji ,  Steven John Koester ,  Amlan Majumdar

IPC分类号： H01L21/84

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/10894

摘要： Integrated circuits having combined memory and logic functions are provided. In one aspect, an integrated circuit is provided. The integrated circuit comprises: a substrate comprising a silicon layer over a BOX layer, wherein a select region of the silicon layer has a thickness of between about three nanometers and about 20 nanometers; at least one eDRAM cell comprising: at least one pass transistor having a pass transistor source region, a pass transistor drain region and a pass transistor channel region formed in the select region of the silicon layer; and a capacitor electrically connected to the pass transistor.

摘要翻译： 提供具有组合的存储器和逻辑功能的集成电路。 一方面，提供集成电路。 集成电路包括：衬底，其包括在BOX层上的硅层，其中硅层的选择区域具有在约3纳米和约20纳米之间的厚度; 至少一个eDRAM单元包括：至少一个传输晶体管，其具有形成在所述硅层的所述选择区域中的传输晶体管源极区域，传输晶体管漏极区域和传输晶体管沟道区域; 以及电连接到传输晶体管的电容器。

公开(公告)号：US08329564B2

公开(公告)日：2012-12-11

申请号：US11925069

申请日：2007-10-26

申请人： Jin Cai ,  Amlan Majumdar ,  Tak H. Ning ,  Zhibin Ren

发明人： Jin Cai ,  Amlan Majumdar ,  Tak H. Ning ,  Zhibin Ren

IPC分类号： H01L21/20

CPC分类号： H01L29/1083 ,  H01L21/28052 ,  H01L21/28088 ,  H01L21/28247 ,  H01L29/165 ,  H01L29/4933 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A method is provided to fabricate a semiconductor device, where the method includes providing a substrate comprised of crystalline silicon; implanting a ground plane in the crystalline silicon so as to be adjacent to a surface of the substrate, the ground plane being implanted to exhibit a desired super-steep retrograde well (SSRW) implant doping profile; annealing implant damage using a substantially diffusionless thermal annealing to maintain the desired super-steep retrograde well implant doping profile in the crystalline silicon and, prior to performing a shallow trench isolation process, depositing a silicon cap layer over the surface of the substrate. The substrate may be a bulk Si substrate or a Si-on-insulator substrate. The method accommodates the use of an oxynitride gate stack structure or a high dielectric constant oxide/metal (high-K/metal) gate stack structure. The various thermal processes used during fabrication are selected/controlled so as to maintain the desired super-steep retrograde well implant doping profile in the crystalline silicon.

摘要翻译： 提供了一种制造半导体器件的方法，其中该方法包括提供由晶体硅构成的衬底; 在晶体硅中注入接地平面以与衬底的表面相邻，所述接地平面被植入以呈现期望的超陡逆向阱（SSRW）注入掺杂分布; 使用基本上无扩散的热退火来退火植入物损伤，以在晶体硅中保持期望的超陡逆向阱注入掺杂分布，并且在执行浅沟槽隔离工艺之前，在衬底的表面上沉积硅帽层。 衬底可以是体积Si衬底或绝缘体上硅衬底。 该方法适应于使用氧氮化物栅叠层结构或高介电常数氧化物/金属（高K /金属）栅叠层结构。 选择/控制在制造期间使用的各种热处理，以便在晶体硅中保持期望的超陡逆向阱注入掺杂分布。

公开(公告)号：US20090108314A1

公开(公告)日：2009-04-30

申请号：US11929943

申请日：2007-10-30

申请人： Jin Cai ,  Josephine Chang ,  Leland Chang ,  Brian L. Ji ,  Steven John Koester ,  Amlan Majumdar

发明人： Jin Cai ,  Josephine Chang ,  Leland Chang ,  Brian L. Ji ,  Steven John Koester ,  Amlan Majumdar

IPC分类号： H01L21/84 ,  H01L27/12

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/10894

摘要： Integrated circuits having combined memory and logic functions are provided. In one aspect, an integrated circuit is provided. The integrated circuit comprises: a substrate comprising a silicon layer over a BOX layer, wherein a select region of the silicon layer has a thickness of between about three nanometers and about 20 nanometers; at least one eDRAM cell comprising: at least one pass transistor having a pass transistor source region, a pass transistor drain region and a pass transistor channel region formed in the select region of the silicon layer; and a capacitor electrically connected to the pass transistor.

摘要翻译： 提供具有组合的存储器和逻辑功能的集成电路。 一方面，提供集成电路。 集成电路包括：衬底，其包括在BOX层上的硅层，其中硅层的选择区域具有在约3纳米和约20纳米之间的厚度; 至少一个eDRAM单元包括：至少一个传输晶体管，其具有形成在所述硅层的所述选择区域中的传输晶体管源极区域，传输晶体管漏极区域和传输晶体管沟道区域; 以及电连接到传输晶体管的电容器。