公开(公告)号：US08314463B2

公开(公告)日：2012-11-20

申请号：US12542879

申请日：2009-08-18

申请人： Jin Cai ,  Amlan Majumdar ,  Tak H. Ning ,  Zhibin Ren

发明人： Jin Cai ,  Amlan Majumdar ,  Tak H. Ning ,  Zhibin Ren

IPC分类号： H01L27/12

CPC分类号： H01L29/1083 ,  H01L21/28052 ,  H01L21/28088 ,  H01L21/28247 ,  H01L29/165 ,  H01L29/4933 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A method is provided to fabricate a semiconductor device, where the method includes providing a substrate comprised of crystalline silicon; implanting a ground plane in the crystalline silicon so as to be adjacent to a surface of the substrate, the ground plane being implanted to exhibit a desired super-steep retrograde well (SSRW) implant doping profile; annealing implant damage using a substantially diffusionless thermal annealing to maintain the desired super-steep retrograde well implant doping profile in the crystalline silicon and, prior to performing a shallow trench isolation process, depositing a silicon cap layer over the surface of the substrate. The substrate may be a bulk Si substrate or a Si-on-insulator substrate. The method accommodates the use of an oxynitride gate stack structure or a high dielectric constant oxide/metal (high-K/metal) gate stack structure. The various thermal processes used during fabrication are selected/controlled so as to maintain the desired super-steep retrograde well implant doping profile in the crystalline silicon.

公开(公告)号：US08329564B2

公开(公告)日：2012-12-11

申请号：US11925069

申请日：2007-10-26

申请人： Jin Cai ,  Amlan Majumdar ,  Tak H. Ning ,  Zhibin Ren

发明人： Jin Cai ,  Amlan Majumdar ,  Tak H. Ning ,  Zhibin Ren

IPC分类号： H01L21/20

CPC分类号： H01L29/1083 ,  H01L21/28052 ,  H01L21/28088 ,  H01L21/28247 ,  H01L29/165 ,  H01L29/4933 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A method is provided to fabricate a semiconductor device, where the method includes providing a substrate comprised of crystalline silicon; implanting a ground plane in the crystalline silicon so as to be adjacent to a surface of the substrate, the ground plane being implanted to exhibit a desired super-steep retrograde well (SSRW) implant doping profile; annealing implant damage using a substantially diffusionless thermal annealing to maintain the desired super-steep retrograde well implant doping profile in the crystalline silicon and, prior to performing a shallow trench isolation process, depositing a silicon cap layer over the surface of the substrate. The substrate may be a bulk Si substrate or a Si-on-insulator substrate. The method accommodates the use of an oxynitride gate stack structure or a high dielectric constant oxide/metal (high-K/metal) gate stack structure. The various thermal processes used during fabrication are selected/controlled so as to maintain the desired super-steep retrograde well implant doping profile in the crystalline silicon.

摘要翻译： 提供了一种制造半导体器件的方法，其中该方法包括提供由晶体硅构成的衬底; 在晶体硅中注入接地平面以与衬底的表面相邻，所述接地平面被植入以呈现期望的超陡逆向阱（SSRW）注入掺杂分布; 使用基本上无扩散的热退火来退火植入物损伤，以在晶体硅中保持期望的超陡逆向阱注入掺杂分布，并且在执行浅沟槽隔离工艺之前，在衬底的表面上沉积硅帽层。 衬底可以是体积Si衬底或绝缘体上硅衬底。 该方法适应于使用氧氮化物栅叠层结构或高介电常数氧化物/金属（高K /金属）栅叠层结构。 选择/控制在制造期间使用的各种热处理，以便在晶体硅中保持期望的超陡逆向阱注入掺杂分布。

公开(公告)号：US20090302388A1

公开(公告)日：2009-12-10

申请号：US12542879

申请日：2009-08-18

申请人： Jin Cai ,  Amlan Majumdar ,  Tak H. Ning ,  Zhibin Ren

发明人： Jin Cai ,  Amlan Majumdar ,  Tak H. Ning ,  Zhibin Ren

IPC分类号： H01L27/12 ,  H01L27/092

CPC分类号： H01L29/1083 ,  H01L21/28052 ,  H01L21/28088 ,  H01L21/28247 ,  H01L29/165 ,  H01L29/4933 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A method is provided to fabricate a semiconductor device, where the method includes providing a substrate comprised of crystalline silicon; implanting a ground plane in the crystalline silicon so as to be adjacent to a surface of the substrate, the ground plane being implanted to exhibit a desired super-steep retrograde well (SSRW) implant doping profile; annealing implant damage using a substantially diffusionless thermal annealing to maintain the desired super-steep retrograde well implant doping profile in the crystalline silicon and, prior to performing a shallow trench isolation process, depositing a silicon cap layer over the surface of the substrate. The substrate may be a bulk Si substrate or a Si-on-insulator substrate. The method accommodates the use of an oxynitride gate stack structure or a high dielectric constant oxide/metal (high-K/metal) gate stack structure. The various thermal processes used during fabrication are selected/controlled so as to maintain the desired super-steep retrograde well implant doping profile in the crystalline silicon.

摘要翻译： 提供了一种制造半导体器件的方法，其中该方法包括提供由晶体硅构成的衬底; 在晶体硅中注入接地平面以与衬底的表面相邻，所述接地平面被植入以呈现期望的超陡逆向阱（SSRW）注入掺杂分布; 使用基本上无扩散的热退火来退火植入物损伤，以在晶体硅中保持期望的超陡逆向阱注入掺杂分布，并且在执行浅沟槽隔离工艺之前，在衬底的表面上沉积硅帽层。 衬底可以是体积Si衬底或绝缘体上硅衬底。 该方法适应于使用氧氮化物栅叠层结构或高介电常数氧化物/金属（高K /金属）栅叠层结构。 选择/控制在制造期间使用的各种热处理，以便在晶体硅中保持期望的超陡逆向阱注入掺杂分布。

公开(公告)号：US20090108350A1

公开(公告)日：2009-04-30

申请号：US11925069

申请日：2007-10-26

申请人： Jin Cai ,  Amlan Majumdar ,  Tak H. Ning ,  Zhibin Ren

发明人： Jin Cai ,  Amlan Majumdar ,  Tak H. Ning ,  Zhibin Ren

IPC分类号： H01L21/336 ,  H01L29/786

CPC分类号： H01L29/1083 ,  H01L21/28052 ,  H01L21/28088 ,  H01L21/28247 ,  H01L29/165 ,  H01L29/4933 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A method is provided to fabricate a semiconductor device, where the method includes providing a substrate comprised of crystalline silicon; implanting a ground plane in the crystalline silicon so as to be adjacent to a surface of the substrate, the ground plane being implanted to exhibit a desired super-steep retrograde well (SSRW) implant doping profile; annealing implant damage using a substantially diffusionless thermal annealing to maintain the desired super-steep retrograde well implant doping profile in the crystalline silicon and, prior to performing a shallow trench isolation process, depositing a silicon cap layer over the surface of the substrate. The substrate may be a bulk Si substrate or a Si-on-insulator substrate. The method accommodates the use of an oxynitride gate stack structure or a high dielectric constant oxide/metal (high-K/metal) gate stack structure. The various thermal processes used during fabrication are selected/controlled so as to maintain the desired super-steep retrograde well implant doping profile in the crystalline silicon.

摘要翻译： 提供了一种制造半导体器件的方法，其中该方法包括提供由晶体硅构成的衬底; 在晶体硅中注入接地平面以与衬底的表面相邻，所述接地平面被植入以呈现期望的超陡逆向阱（SSRW）注入掺杂分布; 使用基本上无扩散的热退火来退火植入物损伤，以在晶体硅中保持期望的超陡逆向阱注入掺杂分布，并且在执行浅沟槽隔离工艺之前，在衬底的表面上沉积硅帽层。 衬底可以是体积Si衬底或绝缘体上硅衬底。 该方法适应于使用氧氮化物栅叠层结构或高介电常数氧化物/金属（高K /金属）栅叠层结构。 选择/控制在制造期间使用的各种热处理，以便在晶体硅中保持期望的超陡逆向阱注入掺杂分布。

公开(公告)号：US08859302B2

公开(公告)日：2014-10-14

申请号：US13036243

申请日：2011-02-28

申请人： Ali Khakifirooz ,  Jin Cai ,  Kangguo Cheng ,  Robert H. Dennard ,  Tak H. Ning

发明人： Ali Khakifirooz ,  Jin Cai ,  Kangguo Cheng ,  Robert H. Dennard ,  Tak H. Ning

IPC分类号： H01L21/66 ,  G11C11/412 ,  H01L27/11 ,  H01L27/12 ,  H01L21/84 ,  H01L27/115 ,  H01L29/66

CPC分类号： G11C11/418 ,  G11C11/412 ,  G11C11/419 ,  G11C29/50004 ,  G11C2029/5004 ,  G11C2029/5006 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/0603 ,  H01L29/66833 ,  H01L29/786 ,  H01L29/792

摘要： A semiconductor device including a charge storage element present in a buried dielectric layer of the substrate on which the semiconductor device is formed. Charge injection may be used to introduce charge to the charge storage element of the buried dielectric layer that is present within the substrate. The charge that is injected to the charge storage element may be used to adjust the threshold voltage (Vt) of each of the semiconductor devices within an array of semiconductor devices that are present on the substrate.

摘要翻译： 一种半导体器件，包括存在于其上形成有半导体器件的衬底的埋置介质层中的电荷存储元件。 可以使用电荷注入来将电荷引入存在于衬底内的掩埋介电层的电荷存储元件。 注入电荷存储元件的电荷可用于调整存在于基板上的半导体器件阵列内的每个半导体器件的阈值电压（Vt）。

公开(公告)号：US08558282B1

公开(公告)日：2013-10-15

申请号：US13607672

申请日：2012-09-08

申请人： Jin Cai ,  Kevin K. Chan ,  Christopher P. D'Emic ,  Bahman Hekmatshoartabari ,  Tak H. Ning ,  Dae-Gyu Park

发明人： Jin Cai ,  Kevin K. Chan ,  Christopher P. D'Emic ,  Bahman Hekmatshoartabari ,  Tak H. Ning ,  Dae-Gyu Park

IPC分类号： H01L21/331

CPC分类号： H01L29/6625 ,  H01L29/161 ,  H01L29/735

摘要： A germanium lateral bipolar junction transistor (BJT) is formed employing a germanium-on-insulator (GOI) substrate. A silicon passivation layer is deposited on the top surface of a germanium layer in the GOI substrate. Shallow trench isolation structures, an extrinsic base region structure, and a base spacer are subsequently formed. A germanium emitter region, a germanium base region, and a germanium collector region are formed within the germanium layer by ion implantation. A silicon emitter region, a silicon base region, and a silicon collector region are formed in the silicon passivation layer. After optional formation of an emitter contact region and a collector contact region, metal semiconductor alloy regions can be formed. A wide gap contact for minority carriers is provided between the silicon base region and the germanium base region and between the silicon emitter region and the germanium emitter region.

公开(公告)号：US20130260526A1

公开(公告)日：2013-10-03

申请号：US13605253

申请日：2012-09-06

申请人： Jin Cai ,  Kevin K. Chan ,  Christopher P. D'Emic ,  Tak H. Ning ,  Dae-Gyu Park

发明人： Jin Cai ,  Kevin K. Chan ,  Christopher P. D'Emic ,  Tak H. Ning ,  Dae-Gyu Park

IPC分类号： H01L21/8222

CPC分类号： H01L29/42304 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/7322 ,  H01L29/7371

摘要： A lateral heterojunction bipolar transistor is formed on a semiconductor-on-insulator substrate including a top semiconductor portion of a first semiconductor material having a first band gap and a doping of a first conductivity type. A stack of an extrinsic base and a base cap is formed such that the stack straddles over the top semiconductor portion. A dielectric spacer is formed around the stack. Ion implantation of dopants of a second conductivity type is performed to dope regions of the top semiconductor portion that are not masked by the stack and the dielectric spacer, thereby forming an emitter region and a collector region. A second semiconductor material having a second band gap greater than the first band gap and having a doping of the second conductivity type is selectively deposited on the emitter region and the collector region to form an emitter contact region and a collector contact region, respectively.

公开(公告)号：US08526220B2

公开(公告)日：2013-09-03

申请号：US13158420

申请日：2011-06-12

申请人： Jin Cai ,  Tak H. Ning

发明人： Jin Cai ,  Tak H. Ning

IPC分类号： G11C11/00

CPC分类号： H01L27/082 ,  G11C11/41 ,  G11C11/411 ,  G11C11/412 ,  H01L21/8228 ,  H01L21/84 ,  H01L27/1023 ,  H01L27/1203

摘要： An example embodiment is a memory cell including a SOI substrate. A first and second set of lateral bipolar transistors are fabricated on the SOI substrate. The first and second set of lateral bipolar transistors are electrically coupled to form two inverters. The inverters are cross coupled to form a memory element.

摘要翻译： 示例性实施例是包括SOI衬底的存储单元。 在SOI衬底上制造第一和第二组横向双极晶体管。 第一和第二组横向双极晶体管电耦合以形成两个反相器。 逆变器交叉耦合以形成存储元件。

公开(公告)号：US20130168821A1

公开(公告)日：2013-07-04

申请号：US13343688

申请日：2012-01-04

申请人： Jin Cai ,  Tak H. Ning

发明人： Jin Cai ,  Tak H. Ning

IPC分类号： H01L27/082 ,  H01L21/328 ,  H01L29/70

CPC分类号： H01L27/082 ,  H01L21/8249 ,  H01L29/1004 ,  H01L29/42304 ,  H01L29/45 ,  H01L29/6625 ,  H01L29/735

摘要： A Bipolar Junction Transistor with an intrinsic base, wherein the intrinsic base includes a top surface and two side walls orthogonal to the top surface, and a base contact electrically coupled to the side walls of the intrinsic base. In one embodiment an apparatus can include a plurality of Bipolar Junction Transistors, and a base contact electrically coupled to the side walls of the intrinsic bases of each BJT.

摘要翻译： 一种具有本征基极的双极结晶体管，其中本征基极包括顶表面和与顶表面正交的两个侧壁，以及电耦合到本征基底的侧壁的基部接触。 在一个实施例中，装置可以包括多个双极结晶体管，以及电耦合到每个BJT的内部基极的侧壁的基部触点。

公开(公告)号：US20120314485A1

公开(公告)日：2012-12-13

申请号：US13158420

申请日：2011-06-12

申请人： Jin Cai ,  Tak H. Ning

发明人： Jin Cai ,  Tak H. Ning

IPC分类号： G11C11/34 ,  H01L21/8222 ,  G11C11/00

CPC分类号： H01L27/082 ,  G11C11/41 ,  G11C11/411 ,  G11C11/412 ,  H01L21/8228 ,  H01L21/84 ,  H01L27/1023 ,  H01L27/1203

摘要： An example embodiment is a memory cell including a SOI substrate. A first and second set of lateral bipolar transistors are fabricated on the SOI substrate. The first and second set of lateral bipolar transistors are electrically coupled to form two inverters. The inverters are cross coupled to form a memory element.

摘要翻译： 示例性实施例是包括SOI衬底的存储单元。 在SOI衬底上制造第一和第二组横向双极晶体管。 第一和第二组横向双极晶体管电耦合以形成两个反相器。 逆变器交叉耦合以形成存储元件。