公开(公告)号：US20080020556A1

公开(公告)日：2008-01-24

申请号：US11827686

申请日：2007-07-13

Applicant: Jin Ha Park

Inventor： Jin Ha Park

IPC: H01L21/425 ,  H01L29/12

CPC classification number: H01L21/26586 ,  H01L21/26506 ,  H01L21/28035 ,  H01L21/823807 ,  H01L29/4925 ,  H01L29/7845

Abstract: Provided is a method for fabricating a semiconductor device. In the method, a poly layer on a semiconductor substrate is etched to a predetermined depth. Ions are implanted into the poly layer at a predetermined angle. The poly layer is etched again to expose a portion of the semiconductor substrate. Therefore, stress is applied to the poly gate instead of the barrier layer, so that the barrier layer is not opened during contact etching because effects of the barrier layer thickness can be solved. Also, stress is applied to a poly gate directly contacting a channel region of the semiconductor substrate to allow tensile force caused by the stress of the poly gate to directly induce tensile force to the channel region, and thus increase mobility, so that device characteristics can be remarkably enhanced.

Abstract translation: 提供一种制造半导体器件的方法。 在该方法中，将半导体衬底上的多晶硅层蚀刻到预定深度。 离子以预定角度植入多层中。 再次蚀刻多晶硅层以暴露半导体衬底的一部分。 因此，应力被施加到多晶硅栅极而不是阻挡层，使得在接触蚀刻期间阻挡层不会被打开，因为可以解决阻挡层厚度的影响。 此外，应力施加到与半导体衬底的沟道区直接接触的多晶硅栅极，以允许由多晶硅栅极的应力引起的张力直接引起对沟道区的拉伸力，从而增加迁移率，使得器件特性可以 明显增强。

公开(公告)号：US07732257B2

公开(公告)日：2010-06-08

申请号：US11926147

申请日：2007-10-29

Applicant: Jin Ha Park

Inventor： Jin Ha Park

IPC: H01L21/00

CPC classification number: H01L27/11 ,  H01L27/1104

Abstract: A semiconductor device and a fabricating method thereof are provided. The semiconductor device can include a first chip having transistors of only the NMOS type, a second chip having transistors of only the PMOS type, and an interconnection electrically connecting the first and second chips to each other. By forming NMOS and PMOS transistors on separate chips, the total number of implant photo processes can be decreased, thereby reducing the fabrication cost.

Abstract translation: 提供了一种半导体器件及其制造方法。 半导体器件可以包括具有仅NMOS晶体管的第一芯片，具有仅PMOS晶体管的第二芯片和将第一和第二芯片彼此电连接的互连。 通过在单独的芯片上形成NMOS和PMOS晶体管，可以减少植入照相工艺的总数，从而降低制造成本。

公开(公告)号：US07687384B2

公开(公告)日：2010-03-30

申请号：US11827686

申请日：2007-07-13

Applicant: Jin Ha Park

Inventor： Jin Ha Park

IPC: H01L21/426

CPC classification number: H01L21/26586 ,  H01L21/26506 ,  H01L21/28035 ,  H01L21/823807 ,  H01L29/4925 ,  H01L29/7845

Abstract: Provided is a method for fabricating a semiconductor device. In the method, a poly layer on a semiconductor substrate is etched to a predetermined depth. Ions are implanted into the poly layer at a predetermined angle. The poly layer is etched again to expose a portion of the semiconductor substrate. Therefore, stress is applied to the poly gate instead of the barrier layer, so that the barrier layer is not opened during contact etching because effects of the barrier layer thickness can be solved. Also, stress is applied to a poly gate directly contacting a channel region of the semiconductor substrate to allow tensile force caused by the stress of the poly gate to directly induce tensile force to the channel region, and thus increase mobility, so that device characteristics can be remarkably enhanced.

Abstract translation: 提供一种制造半导体器件的方法。 在该方法中，将半导体衬底上的多晶硅层蚀刻到预定深度。 离子以预定角度植入多层中。 再次蚀刻多晶硅层以暴露半导体衬底的一部分。 因此，应力被施加到多晶硅栅极而不是阻挡层，使得在接触蚀刻期间阻挡层不会被打开，因为可以解决阻挡层厚度的影响。 此外，应力施加到与半导体衬底的沟道区直接接触的多晶硅栅极，以允许由多晶硅栅极的应力引起的张力直接引起对沟道区的拉伸力，从而增加迁移率，使得器件特性可以 明显增强。

公开(公告)号：US20100059812A1

公开(公告)日：2010-03-11

申请号：US12546323

申请日：2009-08-24

Applicant: Jin Ha Park

Inventor： Jin Ha Park

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L29/4234 ,  H01L29/40117 ,  H01L29/66833 ,  H01L29/792

Abstract: Disclosed are a flash memory device and a method for manufacturing the same. The flash memory device includes a semiconductor substrate having a unit cell defined by an isolation layer, a gate formed over the semiconductor substrate, LDD areas formed at shallow areas of the semiconductor substrate at both sides of the gate, a source and a drain formed at deep areas of the semiconductor substrate while making contact with the LDD areas, and spacers formed at sidewalls of the gate. The spacer includes a first oxide layer pattern, a nitride layer pattern, and a second oxide layer pattern, and the semiconductor substrate includes silicon, so that a silicon-oxide-nitride-oxide-silicon structure for the flash memory device is formed by the silicon of the semiconductor substrate and the spacer at the drain side of the gate.

Abstract translation: 公开了一种闪存器件及其制造方法。 闪速存储器件包括具有由隔离层限定的单元电池的半导体衬底，形成在半导体衬底上的栅极，形成在栅极两侧的半导体衬底的浅区域处的LDD区域，形成在栅极的源极和漏极 与LDD区域接触的半导体衬底的深部区域，以及形成在栅极侧壁处的间隔物。 间隔物包括第一氧化物层图案，氮化物层图案和第二氧化物层图案，并且半导体衬底包括硅，使得用于闪存器件的氧化硅 - 氧化物 - 氧化物 - 氧化物 - 硅结构由 半导体衬底的硅和栅极的漏极侧的间隔物。

公开(公告)号：US07732813B2

公开(公告)日：2010-06-08

申请号：US11842608

申请日：2007-08-21

Applicant: Jin Ha Park

Inventor： Jin Ha Park

IPC: H01L31/0376

CPC classification number: H01L27/14692 ,  H01L27/1463 ,  H01L27/14632 ,  H01L27/14643

Abstract: An image sensor and a method of manufacturing the same are provided. A metal wiring layer is formed on a semiconductor substrate including a circuit region, and first conductive layers are formed on the metal layer separated by a pixel isolation layer. An intrinsic layer is formed on the first conductive layers, and a second conductive layer is formed on the intrinsic layer.

Abstract translation: 提供了图像传感器及其制造方法。 在包括电路区域的半导体衬底上形成金属布线层，并且在由像素隔离层分离的金属层上形成第一导电层。 在第一导电层上形成本征层，在本征层上形成第二导电层。

公开(公告)号：US07666755B2

公开(公告)日：2010-02-23

申请号：US11842715

申请日：2007-08-21

Applicant: Jin Ha Park

Inventor： Jin Ha Park

IPC: H01L21/00

CPC classification number: H01L21/76237 ,  H01L21/26506 ,  H01L21/76232

Abstract: A method of forming a device isolation film of a semiconductor device is provided. The method of forming a device isolation film of a semiconductor device according to an embodiment includes forming the device isolation film by ion-implanting insulation materials inside of a trench formed on a semiconductor substrate.

Abstract translation: 提供一种形成半导体器件的器件隔离膜的方法。 根据实施例的形成半导体器件的器件隔离膜的方法包括通过在半导体衬底上形成的沟槽内离子注入绝缘材料来形成器件隔离膜。

公开(公告)号：US20070152282A1

公开(公告)日：2007-07-05

申请号：US11615078

申请日：2006-12-22

Applicant: Jin Ha Park

Inventor： Jin Ha Park

IPC: H01L29/76

CPC classification number: H01L21/265 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

Abstract: A semiconductor device is provided. An embodiment of the semiconductor device includes: P-type source/drain regions formed in a semiconductor substrate; a gate insulation layer formed on a channel between the P-type source/drain regions; an N-type gate electrode formed on the gate insulation layer; and spacers with an ON structure formed on sidewalls of the gate insulation layer and the gate electrode, the spacers being made from an oxide layer and a nitride layer, wherein the nitride layer includes an implanted impurity. The implanted impurity in the nitride layer can cause compressive stress in the channel between the P-type source/drain regions.

Abstract translation: 提供半导体器件。 半导体器件的一个实施例包括：形成在半导体衬底中的P型源/漏区; 形成在P型源极/漏极区域之间的沟道上的栅极绝缘层; 形成在栅极绝缘层上的N型栅电极; 以及形成在栅极绝缘层和栅电极的侧壁上的具有ON结构的间隔物，所述间隔物由氧化物层和氮化物层制成，其中所述氮化物层包括注入的杂质。 氮化物层中注入的杂质可能导致P型源/漏区之间的沟道中的压应力。

公开(公告)号：US08466030B2

公开(公告)日：2013-06-18

申请号：US11980528

申请日：2007-10-31

Applicant: Jin Ha Park

Inventor： Jin Ha Park

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7833 ,  H01L21/2254 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/3145 ,  H01L29/665 ,  H01L29/6659

Abstract: A semiconductor device, such as a positive channel metal-oxide semiconductor (PMOS) transistor, and a fabricating method thereof are provided. The semiconductor device includes: a gate insulation layer and a gate electrode, a semiconductor substrate, a spacer formed on side walls of the gate insulation layer and the gate electrode, a lightly doped drain (LDD) area formed on the semiconductor substrate at both sides of the gate electrode, a source/drain area formed on the semiconductor substrate at both sides of the gate electrode, and an oxide-nitride layer formed on the gate electrode and on the source/drain area.

Abstract translation: 提供了诸如正沟道金属氧化物半导体（PMOS）晶体管的半导体器件及其制造方法。 半导体器件包括：栅极绝缘层和栅电极，半导体衬底，形成在栅极绝缘层和栅电极的侧壁上的间隔物，在两侧的半导体衬底上形成的轻掺杂漏极（LDD）区域 栅极电极的两侧形成在半导体基板上的源极/漏极区域以及形成在栅极电极和源极/漏极区域上的氧化物 - 氮化物层。

公开(公告)号：US07851295B2

公开(公告)日：2010-12-14

申请号：US11930624

申请日：2007-10-31

Applicant: Jin Ha Park

Inventor： Jin Ha Park

IPC: H01L21/8238 ,  H01L29/788

CPC classification number: H01L21/28273 ,  H01L27/115 ,  H01L27/11521

Abstract: A flash memory device and a method of manufacturing a flash memory device are provided. The flash memory device includes a gate region on a semiconductor substrate, spacers on sidewalls of the gate region, and a passivation layer between the semiconductor substrate and a portion of each spacer.

Abstract translation: 提供闪速存储器件和制造闪速存储器件的方法。 闪速存储器件包括在半导体衬底上的栅极区域，栅极区域的侧壁上的间隔物，以及半导体衬底和每个间隔物的一部分之间的钝化层。

公开(公告)号：US07723220B2

公开(公告)日：2010-05-25

申请号：US11637359

申请日：2006-12-11

Applicant: Jin Ha Park

Inventor： Jin Ha Park

IPC: H01L21/425

CPC classification number: H01L29/4983 ,  H01L21/31155 ,  H01L29/6656 ,  H01L29/7843

Abstract: A method of forming a compressive channel layer in a PMOS device and a PMOS device having a compressive channel layer are provided. The method includes (a) forming a buffer oxide layer on a silicon semiconductor substrate having a gate oxide layer and a gate electrode thereon, (b) forming a silicon nitride layer on the buffer oxide layer, (c) implanting impurities into the silicon nitride layer, and (d) etching or patterning the silicon nitride layer and the buffer oxide layer into which impurities are implanted to form gate spacers on sidewalls of the gate electrode.

Abstract translation: 提供了在PMOS器件中形成压缩沟道层的方法和具有压缩沟道层的PMOS器件。 该方法包括：（a）在其上具有栅极氧化层和栅电极的硅半导体衬底上形成缓冲氧化物层，（b）在缓冲氧化物层上形成氮化硅层，（c）将杂质注入氮化硅 层，以及（d）蚀刻或图案化氮化硅层和其中注入杂质的缓冲氧化物层，以在栅电极的侧壁上形成栅极间隔物。