公开(公告)号：US08331171B2

公开(公告)日：2012-12-11

申请号：US12843673

申请日：2010-07-26

申请人： Jae Il Kim ,  Jong Chern Lee

发明人： Jae Il Kim ,  Jong Chern Lee

IPC分类号： G11C7/10

CPC分类号： G11C7/10

摘要： A semiconductor memory apparatus includes a first data input/output line configured to transmit data from a first memory bank; a second data input/output line configured to transmit the data from the first memory bank; a first data output section configured to align and output data transmitted through the first data input/output line based on an input/output mode; and a second data output section configured to align and output either data transmitted through the first input/output line or the second data input/output line based on the input/output mode and an address signal.

摘要翻译： 半导体存储装置包括：第一数据输入/输出线，被配置为从第一存储体传输数据; 第二数据输入/输出线，被配置为从所述第一存储体发送所述数据; 第一数据输出部，被配置为基于输入/输出模式对准并输出通过第一数据输入/输出线传输的数据; 以及第二数据输出部分，被配置为基于输入/输出模式和地址信号对准并输出通过第一输入/输出线或第二数据输入/输出线传输的数据。

公开(公告)号：US20110188324A1

公开(公告)日：2011-08-04

申请号：US12843673

申请日：2010-07-26

申请人： Jae Il Kim ,  Jong Chern Lee

发明人： Jae Il Kim ,  Jong Chern Lee

IPC分类号： G11C7/10

CPC分类号： G11C7/10

摘要： A semiconductor memory apparatus includes a first data input/output line configured to transmit data from a first memory bank; a second data input/output line configured to transmit the data from the first memory bank; a first data output section configured to align and output data transmitted through the first data input/output line based on an input/output mode; and a second data output section configured to align and output either data transmitted through the first input/output line or the second data input/output line based on the input/output mode and an address signal.

摘要翻译： 半导体存储装置包括：第一数据输入/输出线，被配置为从第一存储体传输数据; 第二数据输入/输出线，被配置为从所述第一存储体发送所述数据; 第一数据输出部，被配置为基于输入/输出模式对准并输出通过第一数据输入/输出线传输的数据; 以及第二数据输出部分，被配置为基于输入/输出模式和地址信号对准并输出通过第一输入/输出线或第二数据输入/输出线传输的数据。

公开(公告)号：US20110103156A1

公开(公告)日：2011-05-05

申请号：US12648997

申请日：2009-12-29

申请人： Jae Il KIM ,  Jong Chern Lee

发明人： Jae Il KIM ,  Jong Chern Lee

IPC分类号： G11C7/10 ,  G11C7/00

CPC分类号： G11C7/1051 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1078 ,  G11C8/18 ,  G11C2207/002

摘要： A data input/output circuit includes a rank selecting section and a data input/output section. The rank selecting section is selectively connected to one of the first and second ranks in response to a chip selection signal, and outputs data to a connected rank or receives data from the connected rank. The data input/output section outputs the data transmitted from the rank selecting section through a data pad to an external device during a read operation, and outputs the data inputted to the data pad to the rank selecting section during a write operation.

摘要翻译： 数据输入/输出电路包括等级选择部分和数据输入/输出部分。 等级选择部分响应于芯片选择信号选择性地连接到第一和第二等级中的一个，并且将数据输出到连接的等级或从连接的等级接收数据。 在读取操作期间，数据输入/输出部分通过数据焊盘将从等级选择部分发送的数据输出到外部设备，并且在写入操作期间将输入到数据焊盘的数据输出到等级选择部分。

公开(公告)号：US08829933B2

公开(公告)日：2014-09-09

申请号：US12836538

申请日：2010-07-14

申请人： Tae Sik Yun ,  Jong Chern Lee

发明人： Tae Sik Yun ,  Jong Chern Lee

IPC分类号： G01R31/20 ,  H01L21/66 ,  G11C29/00

CPC分类号： H01L22/34 ,  G11C29/006 ,  H01L2924/0002 ,  H01L2924/00

摘要： Various embodiments of a semiconductor apparatus and related methods are disclosed. In one exemplary embodiment, a semiconductor apparatus may include a chip, scribe lanes disposed around the chip, and a probe test logic circuit for conducting a probe test on the chip. The probe test logic circuit is disposed on a portion of the scribe lanes.

摘要翻译： 公开了半导体装置和相关方法的各种实施例。 在一个示例性实施例中，半导体装置可以包括设置在芯片周围的芯片，划线，以及用于在芯片上进行探针测试的探针测试逻辑电路。 探针测试逻辑电路设置在划线的一部分上。

公开(公告)号：US08344783B2

公开(公告)日：2013-01-01

申请号：US12970623

申请日：2010-12-16

申请人： Jae Bum Ko ,  Jong Chern Lee ,  Sang Jin Byeon

发明人： Jae Bum Ko ,  Jong Chern Lee ,  Sang Jin Byeon

IPC分类号： H03H11/26

CPC分类号： H03K5/1506 ,  H03K5/05

摘要： A delay circuit includes: a delay unit configured to receive a clock signal, delay an input signal sequentially by a predetermined time interval, and output a plurality of first delayed signals; and an option unit configured to select one of the plurality of first delayed signals based on one or more select signals, and output a second delayed signal.

摘要翻译： 延迟电路包括：延迟单元，被配置为接收时钟信号，按预定时间间隔顺序地延迟输入信号，并输出多个第一延迟信号; 以及选择单元，被配置为基于一个或多个选择信号来选择所述多个第一延迟信号中的一个，并输出第二延迟信号。

公开(公告)号：US08223523B2

公开(公告)日：2012-07-17

申请号：US12650507

申请日：2009-12-30

申请人： Sin Hyun Jin ,  Jong Chern Lee

发明人： Sin Hyun Jin ,  Jong Chern Lee

IPC分类号： G11C5/02

CPC分类号： G11C5/04 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/00014

摘要： A semiconductor apparatus having a plurality of stacked chips includes: a through silicon via (TSV) configured to couple the plurality of chips together and configured to be coupled in series to a plurality of voltage drop units; a plurality of signal conversion units, each of which is configured to convert a voltage outputted from the voltage drop unit of the corresponding one of the plurality of chips to a digital code signal and provide the digital code signal as chip identification signal of the corresponding one of the plurality of chips; and a plurality of chip selection signal generating units, each of which is configured to compare the chip identification signal with a chip selection identification signal to generate a chip selection signal of the corresponding one of the plurality of chips.

摘要翻译： 具有多个堆叠芯片的半导体装置包括：贯穿硅通孔（TSV），被配置为将多个芯片耦合在一起并且被配置为串联耦合到多个压降单元; 多个信号转换单元，每个信号转换单元被配置为将从多个芯片中的相应一个芯片的电压降单元输出的电压转换为数字代码信号，并将数字代码信号提供为对应的一个芯片识别信号 的多个芯片; 以及多个芯片选择信号生成单元，每个芯片选择信号生成单元被配置为将芯片识别信号与芯片选择识别信号进行比较，以生成多个芯片中相应的一个芯片的芯片选择信号。

公开(公告)号：US20110102065A1

公开(公告)日：2011-05-05

申请号：US12650501

申请日：2009-12-30

申请人： Sin Hyun JIN ,  Jong Chern Lee

发明人： Sin Hyun JIN ,  Jong Chern Lee

IPC分类号： H03H11/40

CPC分类号： H01L24/49 ,  G11C5/04 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/48091 ,  H01L2224/49113 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A semiconductor apparatus having a plurality of stacked chips includes: a plurality of latch units, each of which is disposed in a corresponding one of the plurality of chips and is configured to latch a clock signal and a frequency-divided signal at mutually different points of time to generate an chip identification signal of the corresponding one of the plurality of chips; and a plurality of chip selection signal generating units, each of which is disposed in the corresponding one of the plurality of chips and is configured to compare the chip identification signal of the corresponding one of the plurality of chips with a chip selection identification signal to generate a chip selection signal of the corresponding one of the plurality of chips, wherein the chip selection signal is configured to enable the corresponding one of the plurality of chips when the chip identification signal matches the chip selection identification signal.

摘要翻译： 具有多个堆叠芯片的半导体装置包括：多个锁存单元，每个锁存单元布置在所述多个芯片中的相应一个芯片中，并且被配置为在时钟信号和分频信号的相互不同的点处锁存时钟信号和分频信号 时间来生成多个芯片中的相应一个芯片的芯片识别信号; 以及多个芯片选择信号生成单元，其各自设置在所述多个芯片的对应的一个芯片中，并且被配置为将所述多个芯片中的相应一个芯片的芯片识别信号与芯片选择识别信号进行比较，以生成 所述芯片选择信号被配置为当所述芯片识别信号与所述芯片选择识别信号匹配时，使所述多个芯片中的相应一个芯片能够使能。

公开(公告)号：US20070263465A1

公开(公告)日：2007-11-15

申请号：US11641857

申请日：2006-12-20

申请人： Jong Chern Lee

发明人： Jong Chern Lee

IPC分类号： G11C7/00

CPC分类号： G11C7/1048 ,  G11C7/02

摘要： Disclosed is a precharge circuit of a semiconductor apparatus. The precharge circuit of a semiconductor memory apparatus includes a first precharge unit and a second precharge unit. The first precharge unit applies a first core voltage to a pair of local input/output lines, in response to a first precharge signal, to precharge the pair of local input/output lines. The second precharge unit applies a clamp voltage, which is generated using a first supply voltage, to the pair of local input/output lines, in response to the first precharge signal, to precharge the pair of local input/output lines.

摘要翻译： 公开了一种半导体装置的预充电电路。 半导体存储器装置的预充电电路包括第一预充电单元和第二预充电单元。 第一预充电单元响应于第一预充电信号向一对本地输入/输出线施加第一芯电压，以对该对本地输入/输出线进行预充电。 第二预充电单元响应于第一预充电信号，向一对本地输入/输出线施加使用第一电源电压产生的钳位电压，以对该对本地输入/输出线进行预充电。

公开(公告)号：US09928205B2

公开(公告)日：2018-03-27

申请号：US13162702

申请日：2011-06-17

申请人： Dae Suk Kim ,  Jong Chern Lee ,  Sang Jin Byeon

发明人： Dae Suk Kim ,  Jong Chern Lee ,  Sang Jin Byeon

IPC分类号： G06F13/42 ,  G11C16/20 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  H01L25/065

CPC分类号： G06F13/4247

摘要： A semiconductor apparatus may include a master chip, first to nth slave chips, first to nth slave chip ID generating units, and a master chip ID generating unit. The first to nth slave chip ID generating units are disposed respectively in the first to nth slave chips and connected in series to each other. Each of the first to nth slave chip ID generating units is configured to add a predetermined code value to an mth operation code to generate an (m+1)th operation code. The master chip ID generating unit is disposed in the master chip to generate a variable first operation code in response to a select signal. Here, ‘n’ is an integer that is equal to or greater than 2, and ‘m’ is an integer that is equal to or greater than 1 and equal to or smaller than ‘n’.

公开(公告)号：US08823181B2

公开(公告)日：2014-09-02

申请号：US13604449

申请日：2012-09-05

申请人： Chul Kim ,  Jong Chern Lee

发明人： Chul Kim ,  Jong Chern Lee

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/04 ,  H01L23/02 ,  H01L23/12 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L21/768

CPC分类号： H01L21/76885 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05556 ,  H01L2224/05557 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16013 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/37001 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

摘要： In a semiconductor apparatus, a plurality of semiconductor chips including through-silicon vias are stacked in a vertical direction, wherein the through-silicon via formed in each semiconductor chip protrudes beyond heights of each semiconductor chip.

摘要翻译： 在半导体装置中，包括贯通硅通孔的多个半导体芯片在垂直方向堆叠，其中形成在每个半导体芯片中的贯通硅通孔突出超过每个半导体芯片的高度。