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1.发明授权Z2FET field-effect transistor with a vertical subthreshold slope and with no impact ionization 有权Z2FET场效应晶体管具有垂直亚阈值斜率并且没有电击公开(公告)号：US08581310B2
公开(公告)日：2013-11-12
申请号：US13611841
申请日：2012-09-12
IPC分类号： H01L29/80
CPC分类号： H01L29/808 , H01L29/407 , H01L29/7391 , H01L29/78696
摘要： The transistor comprises first and second source/drain electrodes formed in a semiconductor film by N-doped and P-doped areas, respectively. A polarization voltage is applied between the two source/drain electrodes in order to impose to the P-doped electrode a potential higher than that of the N-doped electrode. The transistor comprises first and second devices for generating a potential barrier in the semiconductor film. The two potential barriers are opposed to the passage of the charge carriers emitted by the first and second source/drain electrodes, respectively. The two potential barriers are shifted with respect to an axis connecting the two source/drain electrodes. The two devices for generating a potential barrier are configured to generate a potential barrier having a variable amplitude and it are electrically connected to the gate and to the counter electrode.
摘要翻译： 晶体管包括分别由N掺杂和P掺杂区域形成在半导体膜中的第一和第二源/漏电极。 在两个源/漏电极之间施加极化电压，以便向P掺杂电极施加比N掺杂电极高的电位。 晶体管包括用于在半导体膜中产生势垒的第一和第二器件。 两个势垒分别与由第一和第二源极/漏极发射的电荷载流子相通。 两个势垒相对于连接两个源极/漏极的轴移动。 用于产生势垒的两个器件被配置为产生具有可变幅度的势垒，并且其电连接到栅极和对电极。
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2.发明授权Transistor of the I-MOS type comprising two independent gates and method of using such a transistor 有权包括两个独立栅极的I-MOS型晶体管和使用这种晶体管的方法公开(公告)号：US07732282B2
公开(公告)日：2010-06-08
申请号：US12085866
申请日：2006-12-01
IPC分类号： H01L21/00
CPC分类号： H01L27/1057 , H01L29/7391
摘要： The transistor comprises a source and a drain separated by a lightly doped intermediate zone. The intermediate zone forms first and second junctions respectively with the source and with the drain. The transistor comprises a first gate to generate an electric field in the intermediate zone, on the same side as the first junction, and a second gate to generate an electric field in the intermediate zone, on the same side as the second junction.
摘要翻译： 晶体管包括由轻掺杂的中间区分隔开的源极和漏极。 中间区域分别与源极和漏极形成第一和第二结。 所述晶体管包括第一栅极，用于在与所述第一接合部相同的一侧产生所述中间区域中的电场，以及在与所述第二接合部相同的一侧在所述中间区域中产生电场的第二栅极。
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3.发明授权Fabrication method of a mixed substrate and use of the substrate for producing circuits 有权混合基板的制造方法和用于制造电路的基板的使用公开(公告)号：US07759175B2
公开(公告)日：2010-07-20
申请号：US12071886
申请日：2008-02-27
IPC分类号： H01L21/02
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/02488 , H01L21/02532 , H01L21/02694 , H01L21/823807 , H01L21/823878 , H01L21/84
摘要： The fabrication method of a mixed substrate comprising a tensile strained silicon-on-insulator portion and a compressive strained germanium-on-insulator portion comprises a first step of producing a strained silicon-on-insulator base substrate comprising first and second tensile strained silicon zones. After the base substrate has been produced, the method comprises the successive steps of masking the first tensile strained silicon zone forming the tensile strained silicon-on-insulator portion of the substrate, of performing germanium enrichment treatment of the second tensile strained silicon zone of the base substrate until a compressive strained germanium layer is obtained forming said compressive strained germanium-on-insulator portion of the substrate, and of removing the masking.
摘要翻译： 包括拉伸应变绝缘体上的部分和压电应变绝缘体上的部分的混合衬底的制造方法包括：第一步骤，制造在绝缘体上的应变基底衬底，其包括第一和第二拉伸应变硅区 。 在制造基底衬底之后，该方法包括以下连续步骤：掩蔽形成衬底的拉伸应变绝缘体上的部分的第一拉伸应变硅区，进行锗的第二拉伸应变硅区的锗富集处理 从而形成压缩的应变锗层，形成所述压电应变绝缘体上的绝缘体上的部分，并且去除掩模。
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4.发明申请Transistor of the I-MOS Type Comprising Two Independent Gates and Method of Using Such a Transistor 有权包含两个独立门的I-MOS型晶体管和使用这种晶体管的方法公开(公告)号：US20090096028A1
公开(公告)日：2009-04-16
申请号：US12085866
申请日：2006-12-01
IPC分类号： H01L27/088
CPC分类号： H01L27/1057 , H01L29/7391
摘要： The transistor comprises a source (1) and a drain (2) separated by a lightly doped intermediate zone (I). The intermediate zone (I) forms first (3) and second (4) junctions respectively with the source (1) and with the drain (2). The transistor comprises a first gate (5) to generate an electric field in the intermediate zone (I), on the same side as the first junction (3), and a second gate (6) to generate an electric field in the intermediate zone (I), on the same side as the second junction (4).
摘要翻译： 晶体管包括由轻掺杂中间区（I）分离的源（1）和漏极（2）。 中间区域（I）分别与源极（1）和漏极（2）形成第一（3）和第二（4）结。 晶体管包括在与第一结（3）相同的一侧在中间区（I）中产生电场的第一栅极（5）和在中间区域中产生电场的第二栅极（6） （I），与第二结（4）相同。
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5.发明申请Fabrication method of a mixed substrate and use of the substrate for producing circuits 有权混合基板的制造方法和用于制造电路的基板的使用公开(公告)号：US20080220594A1
公开(公告)日：2008-09-11
申请号：US12071886
申请日：2008-02-27
IPC分类号： H01L21/321
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/02488 , H01L21/02532 , H01L21/02694 , H01L21/823807 , H01L21/823878 , H01L21/84
摘要： The fabrication method of a mixed substrate comprising a tensile strained silicon-on-insulator portion and a compressive strained germanium-on-insulator portion comprises a first step of producing a strained silicon-on-insulator base substrate comprising first and second tensile strained silicon zones. After the base substrate has been produced, the method comprises the successive steps of masking the first tensile strained silicon zone forming the tensile strained silicon-on-insulator portion of the substrate, of performing germanium enrichment treatment of the second tensile strained silicon zone of the base substrate until a compressive strained germanium layer is obtained forming said compressive strained germanium-on-insulator portion of the substrate, and of removing the masking.
摘要翻译： 包括拉伸应变绝缘体上的部分和压电应变绝缘体上的部分的混合衬底的制造方法包括：第一步骤，制造在绝缘体上的应变基底衬底，其包括第一和第二拉伸应变硅区 。 在制造基底衬底之后，该方法包括以下连续步骤：掩蔽形成衬底的拉伸应变绝缘体上的部分的第一拉伸应变硅区，进行锗的第二拉伸应变硅区的锗富集处理 从而形成压缩的应变锗层，形成所述压电应变绝缘体上的绝缘体上的部分，并且去除掩模。
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