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    Resonant clock distribution for very large scale integrated circuits
    4.
    发明申请
    Resonant clock distribution for very large scale integrated circuits 有权
    大规模集成电路的谐振时钟分配

    公开(公告)号：US20050057286A1

    公开(公告)日：2005-03-17

    申请号：US10898743

    申请日：2004-07-26

    申请人： Ken Shepard ,  Steven Chan

    发明人： Ken Shepard ,  Steven Chan

    IPC分类号： G06F1/10 ,  H03L7/00

    CPC分类号： G06F1/10

    摘要： A circuit for distributing a clock signal in an integrated circuit includes a capacitive clock distribution circuit having at least conductor therein. At least one inductor is formed in a metal layer of the integrated circuit and is coupled to the clock distribution circuit. The inductor, generally in the form of a number of spiral inductors distributed throughout the integrated circuit, provides an inductance value selected to resonate with the capacitive clock distribution circuit. By operating the clock distribution circuit at resonance, power dissipation is reduced while skew and jitter performance can be improved.

    摘要翻译： 用于在集成电路中分配时钟信号的电路包括其中至少具有导体的电容时钟分配电路。 在集成电路的金属层中形成至少一个电感器，并且耦合到时钟分配电路。 通常以分布在整个集成电路中的多个螺旋电感器的形式的电感器提供选择为与电容时钟分配电路谐振的电感值。 通过在谐振时操作时钟分配电路，降低功耗，同时可以提高偏移和抖动性能。