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    Semiconductor memory device having insulation patterns and cell gate patterns
    1.
    发明授权
    Semiconductor memory device having insulation patterns and cell gate patterns 有权
    具有绝缘图案和单元栅极图案的半导体存储器件

    公开(公告)号：US08084819B2

    公开(公告)日：2011-12-27

    申请号：US12650137

    申请日：2009-12-30

    申请人： Jingyun Kim ,  Myoungbum Lee ,  Kihyun Hwang

    发明人： Jingyun Kim ,  Myoungbum Lee ,  Kihyun Hwang

    IPC分类号： H01L27/01 ,  H01L21/4763

    CPC分类号： H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565

    摘要： Semiconductor memory devices and methods of forming semiconductor memory devices are provided. The methods may include forming insulation layers and cell gate layers that are alternately stacked on a substrate, forming an opening by successively patterning through the cell gate layers and the insulation layers, and forming selectively conductive barriers on sidewalls of the cell gate layers in the opening.

    摘要翻译： 提供半导体存储器件和形成半导体存储器件的方法。 所述方法可以包括形成交替层叠在基板上的绝缘层和单元栅极层，通过连续图案化通过单元栅极层和绝缘层形成开口，并且在开口中的单元栅极层的侧壁上选择性地形成导电阻挡层 。

    Semiconductor memory device and method of forming the same
    2.
    发明授权
    Semiconductor memory device and method of forming the same 有权
    半导体存储器件及其形成方法

    公开(公告)号：US08173533B2

    公开(公告)日：2012-05-08

    申请号：US13299855

    申请日：2011-11-18

    申请人： Jingyun Kim ,  Myoungbum Lee ,  Kihyun Hwang

    发明人： Jingyun Kim ,  Myoungbum Lee ,  Kihyun Hwang

    IPC分类号： H01L21/4763 ,  H01L27/01

    CPC分类号： H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565

    摘要： Semiconductor memory devices and methods of forming semiconductor memory devices are provided. The methods may include forming insulation layers and cell gate layers that are alternately stacked on a substrate, forming an opening by successively patterning through the cell gate layers and the insulation layers, and forming selectively conductive barriers on sidewalls of the cell gate layers in the opening.

    摘要翻译： 提供半导体存储器件和形成半导体存储器件的方法。 所述方法可以包括形成交替层叠在基板上的绝缘层和单元栅极层，通过连续图案化通过单元栅极层和绝缘层形成开口，并且在开口中的单元栅极层的侧壁上选择性地形成导电阻挡层 。

    SEMICONDUCTOR MEMORY DEVICE HAVING INSULATION PATTERNS AND CELL GATE PATTERNS
    3.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE HAVING INSULATION PATTERNS AND CELL GATE PATTERNS 有权
    具有绝缘图案和电极栅格图案的半导体存储器件

    公开(公告)号：US20100163968A1

    公开(公告)日：2010-07-01

    申请号：US12650137

    申请日：2009-12-30

    申请人： Jingyun Kim ,  Myoungbum Lee ,  Kihyun Hwang

    发明人： Jingyun Kim ,  Myoungbum Lee ,  Kihyun Hwang

    IPC分类号： H01L29/792 ,  H01L21/336

    CPC分类号： H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565

    摘要： Semiconductor memory devices and methods of forming semiconductor memory devices are provided. The methods may include forming insulation layers and cell gate layers that are alternately stacked on a substrate, forming an opening by successively patterning through the cell gate layers and the insulation layers, and forming selectively conductive barriers on sidewalls of the cell gate layers in the opening.

    摘要翻译： 提供半导体存储器件和形成半导体存储器件的方法。 所述方法可以包括形成交替层叠在基板上的绝缘层和单元栅极层，通过连续图案化通过单元栅极层和绝缘层形成开口，并且在开口中的单元栅极层的侧壁上选择性地形成导电阻挡层 。

    Semiconductor memory devices and methods of forming the same
    4.
    发明授权
    Semiconductor memory devices and methods of forming the same 有权
    半导体存储器件及其形成方法

    公开(公告)号：US08592873B2

    公开(公告)日：2013-11-26

    申请号：US13167858

    申请日：2011-06-24

    申请人： Jung Ho Kim ,  Daehyun Jang ,  Myoungbum Lee ,  Kihyun Hwang ,  Sangryol Yang ,  Yong-Hoon Son ,  Ju-Eun Kim ,  Sunghae Lee ,  Dongwoo Kim ,  JinGyun Kim

    发明人： Jung Ho Kim ,  Daehyun Jang ,  Myoungbum Lee ,  Kihyun Hwang ,  Sangryol Yang ,  Yong-Hoon Son ,  Ju-Eun Kim ,  Sunghae Lee ,  Dongwoo Kim ,  JinGyun Kim

    IPC分类号： H01L29/76

    CPC分类号： H01L27/11582 ,  H01L21/02675 ,  H01L21/30604 ,  H01L21/324 ,  H01L27/11551 ,  H01L27/11578 ,  H01L29/7926

    摘要： Semiconductor devices and methods of forming the same may be provided. The semiconductor devices may include gate patterns and insulation patterns repeatedly and alternatingly stacked on a substrate. The semiconductor devices may also include a through region penetrating the gate patterns and the insulation patterns. The semiconductor devices may further include a channel structure extending from the substrate through the through region. The channel structure may include a first channel pattern having a first shape. The first channel pattern may include a first semiconductor region on a sidewall of a portion of the through region, and a buried pattern dividing the first semiconductor region. The channel structure may also include a second channel pattern having a second shape. The second channel pattern may include a second semiconductor region in the through region. A grain size of the second semiconductor region may be larger than that of the first semiconductor region.

    摘要翻译： 可以提供半导体器件及其形成方法。 半导体器件可以包括在衬底上重复并交替堆叠的栅极图案和绝缘图案。 半导体器件还可以包括穿透栅极图案和绝缘图案的穿透区域。 半导体器件还可以包括从衬底延伸穿过区域的沟道结构。 通道结构可以包括具有第一形状的第一通道图案。 第一沟道图案可以包括贯通区域的一部分的侧壁上的第一半导体区域和分割第一半导体区域的掩埋图案。 通道结构还可以包括具有第二形状的第二通道图案。 第二沟道图案可以包括通孔区域中的第二半导体区域。 第二半导体区域的晶粒尺寸可以大于第一半导体区域的晶粒尺寸。

    Semiconductor memory device and method of forming the same
    5.
    发明授权
    Semiconductor memory device and method of forming the same 有权
    半导体存储器件及其形成方法

    公开(公告)号：US08415742B2

    公开(公告)日：2013-04-09

    申请号：US13442804

    申请日：2012-04-09

    申请人： Jingyun Kim ,  Myoungbum Lee ,  Kihyun Hwang

    发明人： Jingyun Kim ,  Myoungbum Lee ,  Kihyun Hwang

    IPC分类号： H01L27/12 ,  H01L21/4763

    CPC分类号： H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565

    摘要： Semiconductor memory devices and methods of forming semiconductor memory devices are provided. The methods may include forming insulation layers and cell gate layers that are alternately stacked on a substrate, forming an opening by successively patterning through the cell gate layers and the insulation layers, and forming selectively conductive barriers on sidewalls of the cell gate layers in the opening.

    摘要翻译： 提供半导体存储器件和形成半导体存储器件的方法。 所述方法可以包括形成交替层叠在基板上的绝缘层和单元栅极层，通过连续图案化通过单元栅极层和绝缘层形成开口，并且在开口中的单元栅极层的侧壁上选择性地形成导电阻挡层 。

    Semiconductor Memory Device And Method Of Forming The Same
    7.
    发明申请
    Semiconductor Memory Device And Method Of Forming The Same 有权
    半导体存储器件及其形成方法

    公开(公告)号：US20120064681A1

    公开(公告)日：2012-03-15

    申请号：US13299855

    申请日：2011-11-18

    申请人： Jingyun Kim ,  Myoungbum Lee ,  Kihyun Hwang

    发明人： Jingyun Kim ,  Myoungbum Lee ,  Kihyun Hwang

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565

    摘要： Semiconductor memory devices and methods of forming semiconductor memory devices are provided. The methods may include forming insulation layers and cell gate layers that are alternately stacked on a substrate, forming an opening by successively patterning through the cell gate layers and the insulation layers, and forming selectively conductive barriers on sidewalls of the cell gate layers in the opening.

    摘要翻译： 提供半导体存储器件和形成半导体存储器件的方法。 所述方法可以包括形成交替层叠在基板上的绝缘层和单元栅极层，通过连续图案化通过单元栅极层和绝缘层形成开口，并且在开口中的单元栅极层的侧壁上选择性地形成导电阻挡层 。

    Semiconductor Memory Devices And Methods Of Forming The Same
    8.
    发明申请
    Semiconductor Memory Devices And Methods Of Forming The Same 有权
    半导体存储器件及其形成方法

    公开(公告)号：US20110316064A1

    公开(公告)日：2011-12-29

    申请号：US13167858

    申请日：2011-06-24

    申请人： Jung Ho Kim ,  Daehyun Jang ,  Myoungbum Lee ,  Kihyun Hwang ,  Sangryol Yang ,  Yong-Hoon Son ,  Ju-Eun Kim ,  Sunghae Lee ,  Dongwoo Kim ,  JinGyun Kim

    发明人： Jung Ho Kim ,  Daehyun Jang ,  Myoungbum Lee ,  Kihyun Hwang ,  Sangryol Yang ,  Yong-Hoon Son ,  Ju-Eun Kim ,  Sunghae Lee ,  Dongwoo Kim ,  JinGyun Kim

    IPC分类号： H01L29/78

    CPC分类号： H01L27/11582 ,  H01L21/02675 ,  H01L21/30604 ,  H01L21/324 ,  H01L27/11551 ,  H01L27/11578 ,  H01L29/7926

    摘要： Semiconductor devices and methods of forming the same may be provided. The semiconductor devices may include gate patterns and insulation patterns repeatedly and alternatingly stacked on a substrate. The semiconductor devices may also include a through region penetrating the gate patterns and the insulation patterns. The semiconductor devices may further include a channel structure extending from the substrate through the through region. The channel structure may include a first channel pattern having a first shape. The first channel pattern may include a first semiconductor region on a sidewall of a portion of the through region, and a buried pattern dividing the first semiconductor region. The channel structure may also include a second channel pattern having a second shape. The second channel pattern may include a second semiconductor region in the through region. A grain size of the second semiconductor region may be larger than that of the first semiconductor region.

    摘要翻译： 可以提供半导体器件及其形成方法。 半导体器件可以包括在衬底上重复并交替堆叠的栅极图案和绝缘图案。 半导体器件还可以包括穿透栅极图案和绝缘图案的穿透区域。 半导体器件还可以包括从衬底延伸穿过区域的沟道结构。 通道结构可以包括具有第一形状的第一通道图案。 第一沟道图案可以包括贯通区域的一部分的侧壁上的第一半导体区域和分割第一半导体区域的掩埋图案。 通道结构还可以包括具有第二形状的第二通道图案。 第二沟道图案可以包括通孔区域中的第二半导体区域。 第二半导体区域的晶粒尺寸可以大于第一半导体区域的晶粒尺寸。

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FORMING THE SAME
    9.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FORMING THE SAME 审中-公开
    三维半导体存储器件及其形成方法

    公开(公告)号：US20150333084A1

    公开(公告)日：2015-11-19

    申请号：US14810845

    申请日：2015-07-28

    申请人： Yong-Hoon Son ,  Jung Ho Kim ,  Seungjae Baik ,  Myoungbum Lee ,  Kihyun Hwang

    发明人： Yong-Hoon Son ,  Jung Ho Kim ,  Seungjae Baik ,  Myoungbum Lee ,  Kihyun Hwang

    IPC分类号： H01L27/115

    CPC分类号： H01L27/11551 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582

    摘要： Nonvolatile memory devices include a string of nonvolatile memory cells on a substrate. This string of nonvolatile memory cells includes a first vertical stack of nonvolatile memory cells on the substrate and a string selection transistor on the first vertical stack of nonvolatile memory cells. A second vertical stack of nonvolatile memory cells is also provided on the substrate and a ground selection transistor is provided on the second vertical stack of nonvolatile memory cells. This second vertical stack of nonvolatile memory cells is provided adjacent the first vertical stack of nonvolatile memory cells. A conjunction doped semiconductor region is provided in the substrate. This conjunction doped region electrically connects the first vertical stack of nonvolatile memory cells in series with the second vertical stack of nonvolatile memory cells so that these stacks can operate as a single NAND-type string of memory cells.

    摘要翻译： 非易失性存储器件包括在衬底上的一串非易失性存储器单元。 这一串非易失性存储单元包括衬底上的非易失性存储单元的第一垂直堆叠和非易失性存储单元的第一垂直堆叠上的串选择晶体管。 第二垂直堆叠的非易失性存储单元也设置在衬底上，并且在非易失性存储单元的第二垂直堆叠上提供接地选择晶体管。 非易失性存储单元的第二垂直堆叠被提供为与非易失性存储单元的第一垂直堆叠相邻。 在衬底中提供连接掺杂半导体区域。 该连接掺杂区域将非易失性存储器单元的第一垂直堆叠与第二垂直堆叠的非易失性存储器单元电连接，使得这些堆叠可以作为单个NAND型存储器单元串工作。

    Multilayer semiconductor devices with channel patterns having a graded grain structure
    10.
    发明授权
    Multilayer semiconductor devices with channel patterns having a graded grain structure 有权
    具有沟道图案的具有渐变晶粒结构的多层半导体器件

    公开(公告)号：US08507918B2

    公开(公告)日：2013-08-13

    申请号：US13018833

    申请日：2011-02-01

    申请人： Yong-Hoon Son ,  Myoungbum Lee ,  Kihyun Hwang

    发明人： Yong-Hoon Son ,  Myoungbum Lee ,  Kihyun Hwang

    IPC分类号： H01L29/04

    CPC分类号： H01L27/11582

    摘要： Memory devices include a stack of interleaved conductive patterns and insulating patterns disposed on a substrate. A semiconductor pattern passes through the stack of conductive patterns and insulating patterns to contact the substrate, the semiconductor pattern having a graded grain size distribution wherein a mean grain size in a first portion of the semiconductor pattern proximate the substrate is less than a mean grain size in a second portion of the semiconductor pattern further removed from the substrate. The graded grain size distribution may be achieved, for example, by partial laser annealing.

    摘要翻译： 存储器件包括布置在衬底上的交错导电图案和绝缘图案的堆叠。 半导体图形通过导体图案和绝缘图案堆叠以接触衬底，半导体图案具有渐变的晶粒尺寸分布，其中半导体图案的靠近衬底的第一部分中的平均晶粒尺寸小于平均晶粒尺寸 在从衬底进一步去除的半导体图案的第二部分中。 分级粒度分布可以通过例如部分激光退火来实现。