Semiconductor memory device with a capacitor formed therein and a method for forming the same
    1.
    发明申请
    Semiconductor memory device with a capacitor formed therein and a method for forming the same 失效
    其中形成有电容器的半导体存储器件及其形成方法

    公开(公告)号:US20070082413A1

    公开(公告)日:2007-04-12

    申请号:US10478642

    申请日:2002-05-21

    IPC分类号: H01L21/00 H01L21/336

    CPC分类号: H01L27/222 B82Y10/00

    摘要: To integrate a capacitor device (40) into the region of a semiconductor memory device with a particularly small number of process steps, a lower electrode device (43) and an upper electrode device (44) of the capacitor device (40) are provided to be formed directly underneath or directly above the material region (30) which has the memory elements (20), in such a way that as a result at least a part of the material region (30) which has the memory elements (20) functions at least as part of the respective dielectric (45) between the electrode devices (43, 44).

    摘要翻译: 为了以特别少的工艺步骤将电容器器件(40)集成到半导体存储器件的区域中,电容器器件(40)的下电极器件(43)和上电极器件(44)被提供到 直接在具有存储元件(20)的材料区域(30)的正下方或直接形成,使得至少一部分具有存储元件(20)的材料区域(30)起作用 至少作为电极装置(43,44)之间的各个电介质(45)的一部分。

    Semiconductor memory device with a capacitor formed therein and a method for forming the same
    2.
    发明授权
    Semiconductor memory device with a capacitor formed therein and a method for forming the same 失效
    其中形成有电容器的半导体存储器件及其形成方法

    公开(公告)号:US07341875B2

    公开(公告)日:2008-03-11

    申请号:US10478642

    申请日:2002-05-21

    IPC分类号: H01L21/00

    CPC分类号: H01L27/222 B82Y10/00

    摘要: To integrate a capacitor device (40) into the region of a semiconductor memory device with a particularly small number of process steps, a lower electrode device (43) and an upper electrode device (44) of the capacitor device (40) are provided to be formed directly underneath or directly above the material region (30) which has the memory elements (20), in such a way that as a result at least a part of the material region (30) which has the memory elements (20) functions at least as part of the respective dielectric (45) between the electrodes devices (43, 44).

    摘要翻译: 为了以特别少的工艺步骤将电容器器件(40)集成到半导体存储器件的区域中,电容器器件(40)的下电极器件(43)和上电极器件(44)被提供到 直接在具有存储元件(20)的材料区域(30)的正下方或直接形成,使得至少一部分具有存储元件(20)的材料区域(30)起作用 至少作为电极装置(43,44)之间的相应电介质(45)的一部分。

    Passivation of Multi-Layer Mirror for Extreme Ultraviolet Lithography

    公开(公告)号:US20100119981A1

    公开(公告)日:2010-05-13

    申请号:US12692243

    申请日:2010-01-22

    IPC分类号: G03F7/20

    摘要: A reflector structure suitable for extreme ultraviolet lithography (EUVL) is provided. The structure comprises a substrate having a multi-layer reflector. A capping layer is formed over the multi-layer reflector to prevent oxidation. In an embodiment, the capping layer is formed of an inert oxide, such as Al2O3, HfO2, ZrO2, Ta2O5, Y2O3-stabilized ZrO2, or the like. The capping layer may be formed by reactive sputtering in an oxygen environment, by non-reactive sputtering wherein the materials are sputtered directly from the respective oxide targets, by non-reactive sputtering of the metallic layer followed by full or partial oxidation (e.g., by natural oxidation, by oxidation in oxygen-containing plasmas, by oxidation in ozone (O3), or the like), by atomic level deposition (e.g., ALCVD), or the like.

    Method for determining a radiation power and an exposure apparatus

    公开(公告)号:US07417736B2

    公开(公告)日:2008-08-26

    申请号:US10599428

    申请日:2005-03-31

    CPC分类号: G03F7/70558 G03F7/7085

    摘要: Method for determining a mean radiation power P rad 0 _ of electromagnetic radiation of a radiation source, the radiation being intensity-modulated with modulation frequency ω0, in a predetermined time interval. The method provides a reflector designed to reflect electromagnetic radiation of the radiation source and electromagnetic radiation of a test radiation source, irradiates a predetermined area of the reflector with the source electromagnetic radiation, at least partially irradiates the predetermined area of the reflector with electromagnetic radiation of the test radiation source, measures a ω0-modulated power component Ptest,ω0(t) of a reflected test radiation power Ptest(t) of an electromagnetic radiation of the test radiation source, the radiation being reflected from the area, in the predetermined time interval, determines a mean value P test , ω 0 0 _ of the measured ω0-modulated power component Ptest,ω0(t) of the reflected test radiation power Ptest(t) in the predetermined time interval, and determines the mean radiation power P rad 0 _ from the relationship P rad 0 _ = a · P test , ω 0 0 _ , where a is a predetermined constant.

    Method for producing an annular microstructure element
    5.
    发明授权
    Method for producing an annular microstructure element 有权
    环形微结构元件的制造方法

    公开(公告)号:US07316933B2

    公开(公告)日:2008-01-08

    申请号:US11112743

    申请日:2005-04-22

    IPC分类号: H01L21/00

    摘要: An annular microstructure element, in particular an annularly arranged monolayer or multilayer thin film, is formed over a substrate (S), e.g., for use in a magnetoresistive memory. To that end, a masking layer is applied over the substrate. An opening (C) is etched into the masking layer, so that a partial region of the surface is uncovered. The etching operation is performed in such a way that the opening (C) is formed with an overhang (B). The overhang at least partially shades the uncovered surface from an incident particle beam (TS). A particle beam (TS) is directed at the substrate (S) at an oblique angle (α) of incidence. In this case, the substrate (S) is rotated relative to the directed particle beam (TS). From the particle beam, material is thereby deposited annularly on the uncovered surface for the purpose of forming a hole-like microstructure element (R).

    摘要翻译: 在衬底(S)上形成环形微结构元件,特别是环形布置的单层或多层薄膜,例如用于磁阻存储器。 为此,在衬底上施加掩模层。 将开口(C)蚀刻到掩模层中,使得表面的部分区域不被覆盖。 蚀刻操作以使得开口(C)形成有突出部(B)的方式进行。 突出部分至少部分地遮蔽未被覆盖的表面与入射的粒子束(TS)。 粒子束(TS)以倾斜角(α)入射到基底(S)。 在这种情况下,基板(S)相对于定向粒子束(TS)旋转。 为了形成孔状微结构元件(R),从粒子束中,材料环状地沉积在未覆盖的表面上。

    Photolithographic mask having a structure region covered by a thin protective coating of only a few atomic layers and methods for the fabrication of the mask including ALCVD to form the thin protective coating
    6.
    发明授权
    Photolithographic mask having a structure region covered by a thin protective coating of only a few atomic layers and methods for the fabrication of the mask including ALCVD to form the thin protective coating 失效
    具有仅由几个原子层覆盖的薄保护涂层的结构区域的光刻掩模和用于制造掩模的方法,包括ALCVD以形成薄的保护涂层

    公开(公告)号:US07078134B2

    公开(公告)日:2006-07-18

    申请号:US10442739

    申请日:2003-05-21

    IPC分类号: G03F1/14 G03F1/08 G21K5/00

    摘要: A photolithographic mask for patterning a photosensitive material, in particular on a wafer, has at least one structure region for imaging a structure on the photosensitive material, and an absorber structure for absorbing incident radiation. At least one structure region is provided and has at least one thin protective coating of only a few atomic layers made of chemically and mechanically resistive material selected from Al2O3, Ta2O5, ZrO2, and HfO2formed by atomic layer chemical vapor deposition (ALCVD) so that the protective coating constitutes a negligible alteration of nominal or critical dimensions for the structure region, and in which additional absorption or reflection losses are negligibly low. In this way, the photolithographic mask can be cleaned chemically and/or mechanically, without the structure regions being attacked and damaged by the chemical and/or mechanical cleaning media. Furthermore, a plurality of methods are possible for fabricating this photolithographic mask.

    摘要翻译: 用于图案化感光材料,特别是在晶片上的光刻掩模具有用于对感光材料上的结构进行成像的至少一个结构区域和用于吸收入射辐射的吸收体结构。 提供至少一个结构区域,并且具有由化学和机械电阻材料制成的仅几个原子层的至少一个薄保护涂层,其选自Al 2 O 3,Ta 通过原子层化学气相沉积(ALCVD)形成的O 2 O 5,ZrO 2 2和HfO 2 2,使得 保护涂层构成对于结构区域的标称或临界尺寸的可忽略的变化,并且附加的吸收或反射损失可忽略不计。 以这种方式,可以化学和/或机械地清洁光刻掩模,而不会使结构区域被化学和/或机械清洁介质侵蚀和损坏。 此外,制造这种光刻掩模的方法是可能的。

    Photosensitive coating material for a substrate
    7.
    发明申请
    Photosensitive coating material for a substrate 审中-公开
    用于基材的感光涂料

    公开(公告)号:US20060147839A1

    公开(公告)日:2006-07-06

    申请号:US11370388

    申请日:2006-03-06

    IPC分类号: G03C1/76

    摘要: A radiation-sensitive coating material, in addition to a base polymer, has a solvent and a radiation-active substance which forms an acid on irradiation by light (including energetic electrons or ions), a fluorescent substance which alters its fluorescence property subject to a change in the acid content of its surroundings. In a process for exposing a substrate coated with the coating material at least one sensor in the exposure chamber of the exposure apparatus measures the intensity of the change in fluorescence spectrum as a function of time during the exposure operation. From the course of intensity at the time of an individual line of the fluorescence spectrum or the intensity integrated over a wavelength interval it is possible to determine the endpoint of the exposure operation by way of electronic algorithms. Deviations from experimentally determined ideal curves of the intensity course provide information on erroneous functions in the course of coating material application and exposure.

    摘要翻译: 除了基础聚合物之外,辐射敏感性涂层材料具有溶剂和辐射活性物质,其在光照射下(包括能量电子或离子)形成酸,荧光物质改变其荧光性质 改变其周围的酸含量。 在用涂布材料曝光的基材的曝光过程中,曝光装置的曝光室中的至少一个传感器在曝光操作期间测量作为时间的函数的荧光光谱的变化强度。 从荧光光谱的单独行的强度或在波长间隔上积分的强度的过程中,可以通过电子算法确定曝光操作的终点。 与实验确定的强度曲线的偏差提供了涂料应用和曝光过程中错误功能的信息。

    Integrated electrical circuit and method for fabricating it
    8.
    发明授权
    Integrated electrical circuit and method for fabricating it 失效
    集成电路及其制造方法

    公开(公告)号:US07064439B1

    公开(公告)日:2006-06-20

    申请号:US09595860

    申请日:2000-06-16

    IPC分类号: H01L23/48 H01L23/52 H01L29/40

    摘要: An integrated electrical circuit having a plurality of structure planes is described. Electrically active elements are situated on at least one element structure plane, where at least one insulation layer is disposed above the element structure plane. Electrical connecting leads are disposed within and/or above the insulation layer, where at least a portion of the connecting leads contain copper. At least one diffusion blocker is disposed underneath the connecting leads, which diffusion blocker impedes and/or prevents the diffusion of copper. The integrated electrical circuit is configured according to the invention such that the diffusion blocker is configured as a blocker layer which is interrupted only in the region of contact holes and/or connection pieces and that the blocker layer is situated between the element structure plane and the insulation layer.

    摘要翻译: 描述具有多个结构平面的集成电路。 电活性元件位于至少一个元件结构平面上,其中至少一个绝缘层设置在元件结构平面之上。 电连接引线设置在绝缘层内和/或上方,其中至少一部分连接引线包含铜。 至少一个扩散阻挡剂设置在连接引线下方,该扩散阻挡剂阻止和/或防止铜的扩散。 集成电路根据本发明被配置为使得扩散阻挡剂被构造为仅在接触孔和/或连接件的区域中断的阻挡层,并且阻挡层位于元件结构平面和 绝缘层。

    Polyvalent, magnetoresistive write/read memory and method for writing and reading a memory of this type
    9.
    发明授权
    Polyvalent, magnetoresistive write/read memory and method for writing and reading a memory of this type 失效
    用于写入和读取这种类型的存储器的多价,磁阻写/读存储器和方法

    公开(公告)号:US06717843B1

    公开(公告)日:2004-04-06

    申请号:US10089531

    申请日:2002-06-04

    IPC分类号: G11C1100

    摘要: A multivalue magnetoresistive read/write memory and method of writing to and reading from such a memory. The invention has, inter alia, one or more storage cells, each storage cell having two intersecting electric conductors and a layer system comprising magnetic layers located at the intersection of the electric conductors. The memory is characterized in that the layer system is designated as a multilayer system with two or more magnetic layers, wherein at least two of the magnetic layers have a magnetization direction that can be set independently of one another. Further, the magnetization direction of the individual layers may be changed on the basis of the electric current flowing through the electric conductors.

    摘要翻译: 多值磁阻读/写存储器以及写入和读取这种存储器的方法。 本发明尤其具有一个或多个存储单元,每个存储单元具有两个交叉的电导体,以及包括位于电导体的相交处的磁性层的层系统。 存储器的特征在于,层系统被指定为具有两个或更多个磁性层的多层系统,其中至少两个磁性层具有彼此独立设置的磁化方向。 此外,可以基于流过电导体的电流来改变各层的磁化方向。

    Memory cell configuration and method for fabricating it

    公开(公告)号:US06579729B2

    公开(公告)日:2003-06-17

    申请号:US09956164

    申请日:2001-09-19

    IPC分类号: H01L2100

    CPC分类号: H01L27/224 G11C11/16

    摘要: Layers of metallic lines and layers of memory cells are disposed alternately one above the other. The memory cells each have a diode and a memory element connected in series therewith. The memory element has a layer structure with a magnetoresistive effect. The diode has a layer structure containing at least two metal layers and an insulating layer disposed in between. The layer structure of the memory element and the layer structure of the diode are disposed above one another. The metallic lines of a respective one of the layers run parallel to one another. The metallic lines of mutually adjacent layers run transversely with respect to one another.