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1.发明申请公开(公告)号：US20060179264A1
公开(公告)日：2006-08-10
申请号：US11054277
申请日：2005-02-09
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F2212/681
摘要： A method, system and computer program product for optimizing EPN to RPN translation when a data miss occurs. The method, system and computer program product take advantage of the high-likelihood of finding the matching PTE in the first half of the PTEG and utilize early data-coming signals from the L2 cache to prime the data-flow pipe to the D-ERAT arrays and requesting a joint steal cycle for executing the write into the D-ERAT and a restart request for re-dispatching the next-to-complete instruction.
摘要翻译： 一种在数据丢失发生时优化EPN到RPN转换的方法，系统和计算机程序产品。 该方法，系统和计算机程序产品利用在PTEG的前半部分找到匹配的PTE的高似然性，并利用来自L2缓存的早期数据来信号将数据流管道引导到D-ERAT 阵列并请求执行对D-ERAT的写入的联合窃取循环以及重新发送下一条完整指令的重新启动请求。
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2.发明申请公开(公告)号：US20080104599A1
公开(公告)日：2008-05-01
申请号：US11969988
申请日：2008-01-07
IPC分类号： G06F9/46
CPC分类号： G06F12/1027 , G06F2212/681
摘要： A method, system and computer program product for optimizing EPN to RPN translation when a data miss occurs. The method, system and computer program product take advantage of the high-likelihood of finding the matching PTE in the first half of the PTEG and utilize early data-coming signals from the L2 cache to prime the data-flow pipe to the D-ERAT arrays and requesting a joint steal cycle for executing the write into the D-ERAT and a restart request for re-dispatching the next-to-complete instruction.
摘要翻译： 一种在数据丢失发生时优化EPN到RPN转换的方法，系统和计算机程序产品。 该方法，系统和计算机程序产品利用在PTEG的前半部分找到匹配的PTE的高似然性，并利用来自L2缓存的早期数据来信号将数据流管道引导到D-ERAT 阵列并请求执行对D-ERAT的写入的联合窃取循环以及重新发送下一条完整指令的重新启动请求。
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3.发明申请Auxiliary mechanism to manage instruction restart and restart coming in a lookahead processor 有权辅助机制，用于管理指令重新启动和重新启动进入前瞻处理器公开(公告)号：US20060184822A1
公开(公告)日：2006-08-17
申请号：US11055844
申请日：2005-02-11
IPC分类号： G06F11/00
CPC分类号： G06F9/3861 , G06F9/3842 , G06F11/141
摘要： A management system that controls a restart interface in a data processing system. The management system switches control of the interface from a distributed network managed by the caches to the management system. The management system is capable of detecting errors and seizing control of the interface in order to remedy any errors that occur within the interface.
摘要翻译： 控制数据处理系统中的重启界面的管理系统。 管理系统将接口控制从高速缓存管理的分布式网络切换到管理系统。 管理系统能够检测错误并占用接口的控制，以补救接口内发生的任何错误。
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4.发明申请Method, apparatus, and computer program product for sharing data in a cache among threads in an SMT processor 有权用于在SMT处理器的线程之间共享缓存中的数据的方法，装置和计算机程序产品公开(公告)号：US20060184741A1
公开(公告)日：2006-08-17
申请号：US11055820
申请日：2005-02-11
IPC分类号： G06F12/00
CPC分类号： G06F12/0842 , G06F12/084 , G06F12/0862
摘要： A method, apparatus, and computer program product are disclosed in a data processing system for sharing data in a cache among multiple threads in a simultaneous multi-threaded (SMT) processor. The SMT processor executes multiple threads concurrently during each clock cycle. The cache is dynamically allocated for use among the multiple threads. Portions of the cache are capable of being designated to store private data that is used exclusively by only a first one of the threads. The portions of the cache are capable of being designated to store shared data that can be used by any one of the multiple threads. The size of the portions can be changed dynamically during execution of the threads.
摘要翻译： 在用于在同时多线程（SMT）处理器中的多个线程之间的高速缓存中共享数据的数据处理系统中公开了一种方法，装置和计算机程序产品。 SMT处理器在每个时钟周期内同时执行多个线程。 动态分配缓存以在多个线程之间使用。 高速缓存的一部分能够被指定为仅存储第一个线程专用的专用数据。 高速缓存的部分能够被指定为存储可由多个线程中的任何一个使用的共享数据。 在执行线程期间，可以动态地更改部分的大小。
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5.发明申请公开(公告)号：US20060184739A1
公开(公告)日：2006-08-17
申请号：US11055818
申请日：2005-02-11
IPC分类号： G06F12/00
CPC分类号： G06F9/383 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3851 , G06F9/3857 , G06F9/3861 , G06F12/0897
摘要： A method and system for maintaining a best-case demand redispatch of an instruction to allow for maximizing the time a rejected thread may execute in lookahead execution mode, while maintaining the smallest L1 cache miss penalty supported by the memory subsystem. In response to a demand miss, a load/store unit sends a fetch request to the next level cache. The cache line of the demand miss is examined to identify the critical sector. Once the critical sector is identified, a best-case data return time is determined based on the fastest time the next level cache is able to return the critical sector of the cache line. The load/store unit then sends a speculative warning to the dispatch unit to coincide with the best-case data return, wherein the speculative warning prepares the dispatch unit to resend the instruction for execution as soon as data is available to the processor core.
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6.发明申请Mechanism and apparatus allowing an N-way set associative cache, implementing a hybrid pseudo-LRU replacement algorithm, to have N L1 miss fetch requests simultaneously inflight regardless of their congruence class 有权允许N路组关联高速缓存的机制和装置，实现混合伪LRU替换算法，以使N L1未命中提取请求同时运行，而不管其一致等级公开(公告)号：US20060179227A1
公开(公告)日：2006-08-10
申请号：US11054293
申请日：2005-02-09
IPC分类号： G06F12/00
CPC分类号： G06F12/0859 , G06F12/124 , G06F12/125 , G06F12/127
摘要： A method, system, and computer program product for supporting multiple fetch requests to the same congruence class in an n-way set associative cache. Responsive to receiving an incoming fetch instruction at a load/store unit, outstanding valid fetch entries in the n-way set associative cache that have the same cache congruence class as the incoming fetch instruction are identified. SetIDs in used by these identified outstanding valid fetch entries are determined. A resulting setID is assigned to the incoming fetch instruction based on the identified setIDs, wherein the resulting setID assigned is a setID not currently in use by the outstanding valid fetch entries. The resulting setID for the incoming fetch instruction is written in a corresponding entry in the n-way set associative cache.
摘要翻译： 一种方法，系统和计算机程序产品，用于在n路组关联高速缓存中支持对同一个同余类的多个提取请求。 响应于在加载/存储单元处接收到传入的取指令，识别n路组关联高速缓冲存储器中具有与传入获取指令相同的高速缓存一致类的未完成的有效提取条目。 确定这些识别的未完成的有效提取条目使用的SetID。 所得到的setID被分配给基于所识别的setID的传入获取指令，其中分配的所得到的setID是未被提交的有效提取条目当前未使用的setID。 用于传入提取指令的结果setID写入n路组关联高速缓存中的相应条目。
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