公开(公告)号：US20050092415A1

公开(公告)日：2005-05-05

申请号：US10696620

申请日：2003-10-29

申请人： Johan Dahlberg ,  Laurent Domenico Colantonio ,  Walter Allen

发明人： Johan Dahlberg ,  Laurent Domenico Colantonio ,  Walter Allen

IPC分类号： B60C3/04 ,  B60C13/00 ,  B60C17/00 ,  B60B21/02 ,  B60B21/04 ,  B60C3/00

CPC分类号： B60C3/04 ,  B60C17/0009 ,  B60C17/0018 ,  Y10T29/49494

摘要： A self-supporting pneumatic tire is molded in such a manner that ride comfort is improved, durability is increased, and a greater run-flat capability can be achieved. The self-supporting run-flat tire is molded such that the molded bead base width is equal or less than the rim width of the intended rim upon which the tire is to be mounted. By molding the tire with a bead width less than or equal to the rim width, the sidewall inserts are not subjected to additional stress during and after inflation of the tire and the strain energy is more evenly distributed through the sidewall pillar construction.

摘要翻译： 自支撑充气轮胎以提高乘坐舒适度，耐久性提高的方式模制，并且可以实现更大的跑平能力。 自支撑漏气保用轮胎被模制成使得模制胎圈基座宽度等于或小于要安装轮胎的预期轮辋的轮辋宽度。 通过使胎圈宽度小于或等于轮辋宽度的轮胎成型，胎侧插入件在轮胎充气期间和充气后不会受到额外的应力，并且应变能更均匀地分布在侧壁支柱结构中。

公开(公告)号：US20060130951A1

公开(公告)日：2006-06-22

申请号：US11017123

申请日：2004-12-20

申请人： Marc Hedo ,  Johan Dahlberg ,  Walter Allen ,  Laurent Colantonio ,  Filomeno Corvasce

发明人： Marc Hedo ,  Johan Dahlberg ,  Walter Allen ,  Laurent Colantonio ,  Filomeno Corvasce

IPC分类号： B60C3/06

CPC分类号： B60C11/0083 ,  B29D30/0601 ,  B29D2030/201 ,  B60C3/06 ,  B60C17/0009 ,  B60C17/0018 ,  Y10T152/10504

摘要： A pneumatic tire is capable of operation during underinflated condition and the construction of sidewalls are configured to compensate for negative cambers acting upon the tire. The inboard side of the tire is softened in comparison to the outboard side of the tire. This is achieved by either forming an asymmetrical tire in either the tire profile or the internal construction.

摘要翻译： 充气轮胎能够在欠充气状态下操作，并且侧壁的构造被构造成补偿作用在轮胎上的负弯矩。 轮胎的内侧与轮胎的外侧相比软化。 这可以通过在轮胎轮廓或内部结构中形成不对称轮胎来实现。

公开(公告)号：US07949851B2

公开(公告)日：2011-05-24

申请号：US11966919

申请日：2007-12-28

申请人： Walter Allen ,  Sunil Atri ,  Robert France

发明人： Walter Allen ,  Sunil Atri ,  Robert France

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F12/1027 ,  G06F2212/7201

摘要： Systems and/or methods that facilitate PBA and LBA translations associated with a memory component(s) are presented. A memory controller component facilitates determining which memory component, erase block, page, and data block contains a PBA in which a desired LBA and/or associated data is stored. The memory controller component facilitates control of performance of calculation functions, table look-up functions, and/or search functions to locate the desired LBA. The memory controller component generates a configuration sequence based in part on predefined optimization criteria to facilitate optimized performance of translations. The memory controller component and/or associated memory component(s) can be configured so that the translation attributes are determined in a desired order using the desired translation function(s) to determine a respective translation attribute based in part on the predefined optimization criteria. The LBA to PBA translations can be performed in parallel by memory components.

摘要翻译： 呈现促进与存储器组件相关联的PBA和LBA转换的系统和/或方法。 存储器控制器组件有助于确定哪个存储器组件，擦除块，页面和数据块包含存储期望的LBA和/或相关联的数据的PBA。 存储器控制器组件便于控制计算功能，表查找功能和/或搜索功能的性能，以定位所需的LBA。 内存控制器组件部分地基于预定义的优化标准生成配置顺序，以促进翻译的优化性能。 存储器控制器组件和/或相关联的存储器组件可以被配置为使得使用期望的转换功能以期望的顺序确定翻译属性，以部分地基于预定义的优化标准来确定相应的翻译属性。 LBA到PBA转换可以由存储器组件并行执行。

公开(公告)号：US20090161430A1

公开(公告)日：2009-06-25

申请号：US11963286

申请日：2007-12-21

申请人： Walter Allen ,  Robert France ,  Sunil Atri

发明人： Walter Allen ,  Robert France ,  Sunil Atri

IPC分类号： G11C16/04 ,  G11C29/00

CPC分类号： G11C29/76

摘要： Systems and methods that facilitate bad block management in a memory device that comprises nonvolatile memory are presented. One or more memory blocks of a memory device are each associated with one or more additional, dedicated bits that facilitate indicating whether the associated memory block is defective. These additional bits, called bad block bits, can be stored in a hardware-based storage mechanism within the memory device. Once a defect is detected in a memory block, at least one of the associated bad block bits can be set to indicate that the memory block is defective. If at least one of the bad block bits associated with a memory block indicates a memory block is defective, access to the memory block can be prevented.

摘要翻译： 介绍了在包括非易失性存储器的存储器件中促进坏块管理的系统和方法。 存储器设备的一个或多个存储器块都与一个或多个附加的专用位相关联，这些专用位便于指示相关联的存储器块是否有缺陷。 称为坏块位的这些附加位可以存储在存储器件内的基于硬件的存储机制中。 一旦在存储器块中检测到缺陷，则可以将相关联的坏块位中的至少一个设置为指示存储块有缺陷。 如果与存储块相关联的至少一个坏块比特指示存储块是有缺陷的，则可以防止对存储块的访问。

公开(公告)号：US08854758B2

公开(公告)日：2014-10-07

申请号：US11419279

申请日：2006-05-19

申请人： Walter Allen ,  Robert Alan Reid

发明人： Walter Allen ,  Robert Alan Reid

IPC分类号： G11B5/09 ,  G11B20/18

CPC分类号： G11B20/1833 ,  G11B2020/1826 ,  G11B2220/2516

摘要： A method and apparatus for storing a disk drive media defect table or list. Defect table entries for a subject disk track are stored on the subject track and retrieved for determining defective sectors only when the subject track is accessed for a data read or write operation.

摘要翻译： 一种用于存储磁盘驱动器介质缺陷表或列表的方法和装置。 目标磁盘轨道的缺陷表条目被存储在主题轨道上，并且只有当对象轨道被访问用于数据读取或写入操作时才被检索用于确定缺陷扇区。

公开(公告)号：US08239611B2

公开(公告)日：2012-08-07

申请号：US11966923

申请日：2007-12-28

申请人： Walter Allen ,  Robert France

发明人： Walter Allen ,  Robert France

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/1036 ,  G06F2212/7205

摘要： Systems and methods that can facilitate more optimized relocation of data associated with a memory are presented. In addition to a memory controller component, a memory manager component can be employed to increase available processing resources to facilitate more optimal execution of higher level functions. Higher level functions can be delegated to the memory manager component to allow execution of these higher level operations with reduced or no load on the memory controller component resources. A uni-bus or multi-bus architecture can be employed to further optimize data relocation operations. A first bus can be utilized for data access operations including read, write, erase, refresh, or combinations thereof, among others, while a second bus can be designated for higher level operations including data compaction, error code correction, wear leveling, or combinations thereof, among others.

摘要翻译： 提出了可以促进与存储器相关联的数据的更优化重定位的系统和方法。 除了存储器控制器组件之外，可以采用存储器管理器组件来增加可用的处理资源，以便更好地执行更高级别的功能。 可以将较高级别的功能委派给内存管理器组件，以允许在内存控制器组件资源上减少或无负载地执行这些更高级别的操作。 可以采用单总线或多总线架构来进一步优化数据重定位操作。 第一总线可以用于数据访问操作，包括读取，写入，擦除，刷新或其组合等，而第二总线可被指定用于更高级操作，包括数据压缩，错误代码校正，损耗均衡或组合 其中。

公开(公告)号：US20090164696A1

公开(公告)日：2009-06-25

申请号：US11963306

申请日：2007-12-21

申请人： Walter Allen ,  Sunil Atri ,  Joseph Khatami

发明人： Walter Allen ,  Sunil Atri ,  Joseph Khatami

IPC分类号： G06F12/06

CPC分类号： G06F12/0246 ,  G06F2212/7201

摘要： Systems and/or methods that facilitate accessing data to/from a memory are presented. An electronic memory component can operate with reduced data access times by eliminating/reducing the use of logical block addressing and employing physical block addressing. Data access is thereby directly associated with the physical location of the stored bits and the need to translate between a logical address and the physical address is reduced or eliminated. This can be even more efficient under asymmetric data access patterns. Further, legacy support for logical block addressing can be included to provide backward compatibility, mixed mode operation, or complimentary mode operation.

摘要翻译： 介绍了有助于从存储器访问数据的系统和/或方法。 电子存储器组件可以通过消除/减少使用逻辑块寻址并采用物理块寻址来减少数据访问时间。 因此，数据访问与所存储的比特的物理位置直接相关联，并且减少或消除了在逻辑地址和物理地址之间进行转换的需要。 这在非对称数据访问模式下可以更有效率。 此外，可以包括对逻辑块寻址的传统支持以提供向后兼容性，混合模式操作或补充模式操作。

公开(公告)号：US07193798B2

公开(公告)日：2007-03-20

申请号：US11034133

申请日：2005-01-12

申请人： James Byrd ,  Walter Allen

发明人： James Byrd ,  Walter Allen

IPC分类号： G11B5/09

CPC分类号： G11B20/10481 ,  G11B20/10009 ,  G11B20/18 ,  G11B20/1803 ,  G11B20/1833

摘要： One or more bits are added to the embedded repeatable runout correction (ERRC) bit pattern of a servo field so that errors in ERRC bit patterns can be detected and in certain cases corrected. If four bits are added, a single bit error in an ERRC bit pattern can be detected and corrected. If five bits are added, two bit errors in the ERRC bit pattern can be detected. In accordance with the preferred embodiment, the invention uses a single encode table and a single decode table to encode the ERRC pattern to be written to the disk and to decode the ERRC pattern read back from the disk.

摘要翻译： 一个或多个比特被添加到伺服字段的嵌入式可重复跳动校正（ERRC）比特模式中，使得可以检测ERRC比特模式中的错误并且在某些情况下被校正。 如果添加了四位，则可以检测和校正ERRC位模式中的单个位错误。 如果添加了5位，则可以检测ERRC位模式中的两位错误。 根据优选实施例，本发明使用单个编码表和单个解码表对要写入盘的ERRC图案进行编码，并解码从盘回读的ERRC图案。

公开(公告)号：US20060016536A1

公开(公告)日：2006-01-26

申请号：US10896580

申请日：2004-07-21

申请人： Paul Maxwell ,  Sebastian Fontaine ,  Walter Allen ,  Daniel Beha ,  Brian Digman

发明人： Paul Maxwell ,  Sebastian Fontaine ,  Walter Allen ,  Daniel Beha ,  Brian Digman

IPC分类号： B60C11/13

CPC分类号： B60C11/11 ,  B60C11/12 ,  B60C11/13 ,  B60C2011/1338 ,  Y10S152/03 ,  Y10S152/902

摘要： A pneumatic tire with a tread has at least two axially adjacent tread elements, the elements being separated by a groove and each element having opposing lateral sides. Connecting the axially adjacent tread elements is at least one traction biting element. The biting element has three continuous portions. The first portion extends along the lateral side of the first tread element. The second portion extends through the separating groove. The third portion extends along the lateral side of the second tread element. Each biting element forms at least two distinct edges along the lateral sides of each tread element and two distinct edges in the separating grooves.

摘要翻译： 具有胎面的充气轮胎具有至少两个轴向相邻的胎面元件，所述元件由凹槽分隔，并且每个元件具有相对的横向侧面。 连接轴向相邻的胎面元件是至少一个牵引咬合元件。 咬合元件具有三个连续部分。 第一部分沿着第一胎面元件的侧面延伸。 第二部分延伸穿过分离槽。 第三部分沿着第二踏面元件的侧面延伸。 每个咬合元件沿着每个胎面元件的侧面形成至少两个不同的边缘，并且在分离槽中形成两个不同的边缘。

公开(公告)号：US07953919B2

公开(公告)日：2011-05-31

申请号：US11963306

申请日：2007-12-21

申请人： Walter Allen ,  Sunil Atri ,  Joseph Khatami

发明人： Walter Allen ,  Sunil Atri ,  Joseph Khatami

IPC分类号： G06F12/06 ,  G06F13/00

CPC分类号： G06F12/0246 ,  G06F2212/7201

摘要： Systems and/or methods that facilitate accessing data to/from a memory are presented. An electronic memory component can operate with reduced data access times by eliminating/reducing the use of logical block addressing and employing physical block addressing. Data access is thereby directly associated with the physical location of the stored bits and the need to translate between a logical address and the physical address is reduced or eliminated. This can be even more efficient under asymmetric data access patterns. Further, legacy support for logical block addressing can be included to provide backward compatibility, mixed mode operation, or complimentary mode operation.

摘要翻译： 介绍了有助于从存储器访问数据的系统和/或方法。 电子存储器组件可以通过消除/减少使用逻辑块寻址并采用物理块寻址来减少数据访问时间。 因此，数据访问与所存储的比特的物理位置直接相关联，并且减少或消除了在逻辑地址和物理地址之间进行转换的需要。 这在非对称数据访问模式下可以更有效率。 此外，可以包括对逻辑块寻址的传统支持以提供向后兼容性，混合模式操作或补充模式操作。