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公开(公告)号：US20090058493A1
公开(公告)日：2009-03-05
申请号：US12197506
申请日：2008-08-25
IPC分类号： H03L5/00
CPC分类号： H03K3/356113
摘要： An electronic device with a supply voltage level converter converts a signal from a first low supply voltage level to a second high supply voltage level includes; a first pair of cross coupled MOS transistors compliant with the second supply voltage level, each having a source coupled to the second supply voltage level and providing complementary output signals at respective drains; driven by a second pair of common gate MOS transistors compliant with the second supply voltage; driven by a third pair of common gate MOS transistors compliant with the first voltage level; and driven by first and second inverters coupled in a chain and supplied by the first supply voltage level, each having an output connected to the source of a transistor in a third pair.
摘要翻译： 具有电源电压电平转换器的电子设备将来自第一低电源电压电平的信号转换为第二高电源电压电平包括： 符合第二电源电压电平的第一对交叉耦合MOS晶体管，每一个具有耦合到第二电源电压电平的源极，并在相应的漏极处提供互补的输出信号; 由符合第二电源电压的第二对公共栅极MOS晶体管驱动; 由符合第一电压电平的第三对公共栅极MOS晶体管驱动; 并由耦合在链中并由第一电源电压电平提供的第一和第二反相器驱动，每个具有连接到第三对晶体管的源极的输出。
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公开(公告)号：US20080272831A1
公开(公告)日：2008-11-06
申请号：US12061325
申请日：2008-04-02
IPC分类号： G05F1/10
CPC分类号： H03L7/0896 , H02M3/07 , H03F2203/45028 , H03F2203/45326
摘要： A charge pump CMOS circuit comprises a differential input stage with two parallel circuit branches. Each of the parallel circuit branches has a diode-connected MOS transistor connected in series with a complementary input MOS transistor. There is a common tail current source for both circuit branches. The diode-connected MOS transistors each have their gate/drain node connected to corresponding current sources. The charge pump CMOS circuit is suitable for use in an oscillator.
摘要翻译： 电荷泵CMOS电路包括具有两个并联电路分支的差分输入级。 每个并联电路分支具有与互补输入MOS晶体管串联连接的二极管连接的MOS晶体管。 两个电路分支都有一个共同的尾电流源。 二极管连接的MOS晶体管的栅极/漏极节点连接到相应的电流源。 电荷泵CMOS电路适用于振荡器。
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公开(公告)号：US20120286833A1
公开(公告)日：2012-11-15
申请号：US13005264
申请日：2011-01-12
IPC分类号： H03L7/00
CPC分类号： H03K17/223 , G06F1/24 , H03K17/302 , H03K2217/0036
摘要： An integrated circuit provides a power on reset signal with respect to a supply voltage level supplying the electronic device. The integrated circuit comprises a bias current generating stage having a first current mirror and an output stage having first, second and third series connected MOS transistors. A connection between the second MOS transistor and the third MOS transistor forms a POR output node. A gate of the second MOS transistor and a gate of the third MOS transistor are coupled to each other and to the first current mirror. This allows a current through the third MOS transistor when the supply voltage is higher than a first MOS transistor threshold and a current through the second MOS transistor only when the supply voltage is greater than or equal to the sum of the first MOS transistor threshold and a second MOS transistor threshold voltage.
摘要翻译： 集成电路相对于提供电子设备的电源电压电平提供上电复位信号。 集成电路包括具有第一电流镜和具有第一，第二和第三串联MOS晶体管的输出级的偏置电流产生级。 第二MOS晶体管和第三MOS晶体管之间的连接形成POR输出节点。 第二MOS晶体管的栅极和第三MOS晶体管的栅极彼此耦合并耦合到第一电流镜。 当电源电压高于第一MOS晶体管阈值时，允许通过第三MOS晶体管的电流，以及仅当电源电压大于或等于第一MOS晶体管阈值和 第二MOS晶体管阈值电压。
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4.发明授权Method and device for controlling a successive approximation register analog to digital converter 有权用于控制逐次逼近寄存器模数转换器的方法和装置公开(公告)号：US07786920B2
公开(公告)日：2010-08-31
申请号：US12204301
申请日：2008-09-04
IPC分类号： H03M1/38
CPC分类号： H03M1/1023 , H03M1/468
摘要： A method for controlling a successive approximation register analog to digital converter comprising connecting a first side of a capacitor to a first comparator input, during a sampling phase connecting the first side of a capacitor to an input and connecting a second side of the capacitor to a mid-voltage, following the sampling phase disconnecting the first side of the capacitor from the input and disconnecting the second side of the capacitor from the mid-voltage and autozeroing the comparator.
摘要翻译： 一种用于控制逐次逼近寄存器模数转换器的方法，包括在将电容器的第一侧连接到输入并将电容器的第二侧连接到一个电容器的采样阶段期间将电容器的第一侧连接到第一比较器输入端 中间电压，采样相位将电容器的第一侧与输入端断开，并将电容器的第二侧与中间电压断开并自动调零比较器。
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公开(公告)号：US08373459B2
公开(公告)日：2013-02-12
申请号：US13005264
申请日：2011-01-12
IPC分类号： H03L7/00
CPC分类号： H03K17/223 , G06F1/24 , H03K17/302 , H03K2217/0036
摘要： An integrated circuit provides a power on reset signal with respect to a supply voltage level supplying the electronic device. The integrated circuit comprises a bias current generating stage having a first current mirror and an output stage having first, second and third series connected MOS transistors. A connection between the second MOS transistor and the third MOS transistor forms a POR output node. A gate of the second MOS transistor and a gate of the third MOS transistor are coupled to each other and to the first current mirror. This allows a current through the third MOS transistor when the supply voltage is higher than a first MOS transistor threshold and a current through the second MOS transistor only when the supply voltage is greater than or equal to the sum of the first MOS transistor threshold and a second MOS transistor threshold voltage.
摘要翻译： 集成电路相对于提供电子设备的电源电压电平提供上电复位信号。 集成电路包括具有第一电流镜和具有第一，第二和第三串联MOS晶体管的输出级的偏置电流产生级。 第二MOS晶体管和第三MOS晶体管之间的连接形成POR输出节点。 第二MOS晶体管的栅极和第三MOS晶体管的栅极彼此耦合并耦合到第一电流镜。 当电源电压高于第一MOS晶体管阈值时，允许通过第三MOS晶体管的电流，以及仅当电源电压大于或等于第一MOS晶体管阈值和 第二MOS晶体管阈值电压。
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公开(公告)号：US07893734B2
公开(公告)日：2011-02-22
申请号：US12247398
申请日：2008-10-08
IPC分类号： H03L7/00
CPC分类号： H03K17/223 , G06F1/24 , H03K17/302 , H03K2217/0036
摘要： An integrated circuit provides a power on reset signal with respect to a supply voltage level supplying the electronic device. The integrated circuit comprises a bias current generating stage having a first current mirror and an output stage having first, second and third series connected MOS transistors. A connection between the second MOS transistor and the third MOS transistor forms a POR output node. A gate of the second MOS transistor and a gate of the third MOS transistor are coupled to each other and to the first current mirror. This allows a current through the third MOS transistor when the supply voltage is higher than a first MOS transistor threshold and a current through the second MOS transistor only when the supply voltage is greater than or equal to the sum of the first MOS transistor threshold and a second MOS transistor threshold voltage.
摘要翻译： 集成电路相对于提供电子设备的电源电压电平提供上电复位信号。 集成电路包括具有第一电流镜和具有第一，第二和第三串联MOS晶体管的输出级的偏置电流产生级。 第二MOS晶体管和第三MOS晶体管之间的连接形成POR输出节点。 第二MOS晶体管的栅极和第三MOS晶体管的栅极彼此耦合并耦合到第一电流镜。 当电源电压高于第一MOS晶体管阈值时，允许通过第三MOS晶体管的电流，以及仅当电源电压大于或等于第一MOS晶体管阈值和 第二MOS晶体管阈值电压。
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公开(公告)号：US20090121754A1
公开(公告)日：2009-05-14
申请号：US12247398
申请日：2008-10-08
IPC分类号： H03K17/22
CPC分类号： H03K17/223 , G06F1/24 , H03K17/302 , H03K2217/0036
摘要： An integrated circuit provides a power on reset signal with respect to a supply voltage level supplying the electronic device. The integrated circuit comprises a bias current generating stage having a first current mirror and an output stage having first, second and third series connected MOS transistors. A connection between the second MOS transistor and the third MOS transistor forms a POR output node. A gate of the second MOS transistor and a gate of the third MOS transistor are coupled to each other and to the first current mirror. This allows a current through the third MOS transistor when the supply voltage is higher than a first MOS transistor threshold and a current through the second MOS transistor only when the supply voltage is greater than or equal to the sum of the first MOS transistor threshold and a second MOS transistor threshold voltage.
摘要翻译： 集成电路相对于提供电子设备的电源电压电平提供上电复位信号。 集成电路包括具有第一电流镜和具有第一，第二和第三串联MOS晶体管的输出级的偏置电流产生级。 第二MOS晶体管和第三MOS晶体管之间的连接形成POR输出节点。 第二MOS晶体管的栅极和第三MOS晶体管的栅极彼此耦合并耦合到第一电流镜。 当电源电压高于第一MOS晶体管阈值时，允许通过第三MOS晶体管的电流，以及仅当电源电压大于或等于第一MOS晶体管阈值和 第二MOS晶体管阈值电压。
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8.发明申请Method and Device for Controlling a Successive Approximation Register Analog to Digital Converter 有权用于控制连续近似寄存器模数转换器的方法和装置公开(公告)号：US20090066556A1
公开(公告)日：2009-03-12
申请号：US12204301
申请日：2008-09-04
IPC分类号： H03M1/00
CPC分类号： H03M1/1023 , H03M1/468
摘要： A method for controlling a successive approximation register analog to digital converter comprising connecting a first side of a capacitor to a first comparator input, during a sampling phase connecting the first side of a capacitor to an input and connecting a second side of the capacitor to a mid-voltage, following the sampling phase disconnecting the first side of the capacitor from the input and disconnecting the second side of the capacitor from the mid-voltage and autozeroing the comparator.
摘要翻译： 一种用于控制逐次逼近寄存器模数转换器的方法，包括在将电容器的第一侧连接到输入并将电容器的第二侧连接到一个电容器的采样阶段期间将电容器的第一侧连接到第一比较器输入端 中间电压，采样相位将电容器的第一侧与输入端断开，并将电容器的第二侧与中间电压断开并自动调零比较器。
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公开(公告)号：US07525394B2
公开(公告)日：2009-04-28
申请号：US11618218
申请日：2006-12-29
CPC分类号： H03K3/0231 , H03K3/354
摘要： An ultra low power relaxation CMOS oscillator for low frequency clock generation comprises a current source and a pair of capacitors that are alternatingly charged by the current source and discharged by thyristor-based inverters being used as comparators. No separate bias currents are needed.
摘要翻译： 用于低频时钟产生的超低功率弛豫CMOS振荡器包括电流源和一对电容器，其被电流源交替地充电并且被用作比较器的基于晶闸管的反相器放电。 不需要单独的偏置电流。
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10.发明申请公开(公告)号：US20090096433A1
公开(公告)日：2009-04-16
申请号：US12196379
申请日：2008-08-22
申请人： Johannes Gerber , Vadim V. Ivanov , Ruediger Kuhn
发明人： Johannes Gerber , Vadim V. Ivanov , Ruediger Kuhn
IPC分类号： G05F1/00
CPC分类号： G05F1/56
摘要： An electronic device has an LDO regulator for varying loads. The LDO regulator includes a primary supply node coupled to a primary voltage supply. An output node provides a secondary supply voltage and a load current. A bias current source generates a bias current. A gain stage coupled to the bias current source increases the maximum available load current. The gain stage includes a first MOS transistor biased in weak inversion coupled to a current mirror which mirrors the drain current through the first MOS transistor to the output node. The gate-source voltage of the first MOS transistor increases in response to a decreasing secondary supply voltage level at the output node to increase the available load current.
摘要翻译： 电子设备具有用于变化负载的LDO调节器。 LDO调节器包括耦合到初级电压源的主要供电节点。 输出节点提供二次电源电压和负载电流。 偏置电流源产生偏置电流。 耦合到偏置电流源的增益级增加最大可用负载电流。 增益级包括偏置在弱反相中的第一MOS晶体管，耦合到电流镜，其将通过第一MOS晶体管的漏极电流反射到输出节点。 第一MOS晶体管的栅极 - 源极电压响应于输出节点处的二次电源电压降低而增加可用负载电流。
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