摘要:
A power-gated electronic device and a method of operating the same is provided. The power-gated electronic device comprises a low drop out voltage power supply (LDO), an auxiliary power supply and at least one electronic domain having a power gate. The LDO provides a supply voltage to the at least one electronic domain which is coupled to a supply rail of the LDO via a switch, acting as a power gate. The auxiliary power supply comprises at least one current source which is coupled to the electronic domain via an auxiliary switch acting as an auxiliary power gate. The auxiliary power supply is configured to control the auxiliary switch as a function of a voltage difference between a reference voltage and the auxiliary supply voltage.
摘要:
An electronic device includes an integrated circuit with a FRAM memory and an integrated capacitor connected between a power supply for the FRAM memory and ground. The integrated capacitor has a capacitance sufficient to store the charge necessary for a complete read-and-write-back cycle of the FRAM memory. When granting read-access to the FRAM memory, the FRAM memory is supplied by the integrated capacitor which is then disconnected from the integrated circuit power supply. Upon receiving a request for a read-access to the FRAM memory, a charge detector detects whether the internal capacitor is sufficiently charged for a complete read-and-write-back cycle of the FRAM memory. Read-access to the FRAM memory is only granted if the internal capacitor is sufficiently charged and disconnected from the power supply. An alternative embodiment alternately charges and powers the FRAM from two integrated capacitors.
摘要:
An electronic device includes an integrated circuit with a FRAM memory and an integrated capacitor connected between a power supply for the FRAM memory and ground. The integrated capacitor has a capacitance sufficient to store the charge necessary for a complete read-and-write-back cycle of the FRAM memory. When granting read-access to the FRAM memory, the FRAM memory is supplied by the integrated capacitor. Upon receiving a request for a read-access to the FRAM memory, a charge detector detects whether the internal capacitor is sufficiently charged for a complete read-and-write-back cycle of the FRAM memory. Read-access to the FRAM memory is only granted if the internal capacitor is sufficiently charged. An alternative embodiment alternately charges and powers the FRAM from two integrated capacitors.
摘要:
An integrated circuit provides a power on reset signal with respect to a supply voltage level supplying the electronic device. The integrated circuit comprises a bias current generating stage having a first current mirror and an output stage having first, second and third series connected MOS transistors. A connection between the second MOS transistor and the third MOS transistor forms a POR output node. A gate of the second MOS transistor and a gate of the third MOS transistor are coupled to each other and to the first current mirror. This allows a current through the third MOS transistor when the supply voltage is higher than a first MOS transistor threshold and a current through the second MOS transistor only when the supply voltage is greater than or equal to the sum of the first MOS transistor threshold and a second MOS transistor threshold voltage.
摘要:
An integrated circuit provides a power on reset signal with respect to a supply voltage level supplying the electronic device. The integrated circuit comprises a bias current generating stage having a first current mirror and an output stage having first, second and third series connected MOS transistors. A connection between the second MOS transistor and the third MOS transistor forms a POR output node. A gate of the second MOS transistor and a gate of the third MOS transistor are coupled to each other and to the first current mirror. This allows a current through the third MOS transistor when the supply voltage is higher than a first MOS transistor threshold and a current through the second MOS transistor only when the supply voltage is greater than or equal to the sum of the first MOS transistor threshold and a second MOS transistor threshold voltage.
摘要:
An integrated circuit provides a power on reset signal with respect to a supply voltage level supplying the electronic device. The integrated circuit comprises a bias current generating stage having a first current mirror and an output stage having first, second and third series connected MOS transistors. A connection between the second MOS transistor and the third MOS transistor forms a POR output node. A gate of the second MOS transistor and a gate of the third MOS transistor are coupled to each other and to the first current mirror. This allows a current through the third MOS transistor when the supply voltage is higher than a first MOS transistor threshold and a current through the second MOS transistor only when the supply voltage is greater than or equal to the sum of the first MOS transistor threshold and a second MOS transistor threshold voltage.
摘要:
A method for controlling a successive approximation register analog to digital converter comprising connecting a first side of a capacitor to a first comparator input, during a sampling phase connecting the first side of a capacitor to an input and connecting a second side of the capacitor to a mid-voltage, following the sampling phase disconnecting the first side of the capacitor from the input and disconnecting the second side of the capacitor from the mid-voltage and autozeroing the comparator.
摘要:
An electronic device generates a current with a predetermined temperature coefficient. The circuit comprises a temperature coefficient (TC) component receiving a bias current, a differential amplifier providing a buffered output voltage based on the voltage across the TC component and a resistor receiving an TC current based on the differential amplifier output voltage. The differential amplifier has a predetermined input related offset which decreases the voltage drop across the resistor. The temperature coefficient component could have either a negative temperature component (NTC) or a positive temperature component (PTC).
摘要:
A method of switching a low dropout regulator includes determining an actual active time of a power request from an electronic device; enabling the low dropout regulator in response to said power request at a time corresponding to a start of the actual active time of the power request for an active enabled time having a duration at least the same as the actual active time and long enough to sufficiently settle the output voltage of the low dropout regulator; and disabling the low dropout regulator. In embodiments, the active enabled time is prolonged beyond the actual active time of the power request for all or at least some power requests. An electronic device includes circuits for controlling the switching of a low dropout in the described manner.
摘要:
The present invention relates to controlling the refresh rate of the reference voltage on a sampling capacitor (Csamp). A comparator (COMP) compares the voltage on a first capacitor (C1) with the voltage on a second capacitor (C2). These capacitors have the capacitance of the sampling capacitor (Csamp). Upon each refresh the first capacitor (C1) samples a first voltage (Va) and the second capacitor samples a lower second voltage (Vb). The first capacitor (C1) is discharged at a first current Ia via a first leakage current source (D1). The second capacitor (C2) is discharged at a second current Ib via a second leakage current source (D2). The comparator (COMP) triggers a refresh when the voltages equal. The first current Ia is preferably an integer N times the second current Ib.