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1.发明申请APPARATUS AND METHOD FOR IMPLEMENTING REFRESHLESS SINGLE TRANSISTOR CELL eDRAM FOR HIGH PERFORMANCE MEMORY APPLICATIONS 审中-公开用于实现高性能存储器应用的无刷单晶振子电池的装置和方法公开(公告)号：US20090144507A1
公开(公告)日：2009-06-04
申请号：US11950015
申请日：2007-12-04
IPC分类号： G06F12/08
CPC分类号： G06F12/0893 , G06F12/0891 , Y02D10/13
摘要： An apparatus for implementing a refreshless, embedded dynamic random access memory (eDRAM) cache device includes a cache structure having a cache tag array associated with a DRAM data cache with a plurality of cache lines, the cache tag array having an address tag, a valid bit and an access bit corresponding to each of the plurality of cache lines; and each access bit configured to indicate whether the corresponding cache line has been accessed as a result of a read or a write operation during a defined assessment period, the defined assessment period being smaller than retention time of data in the DRAM data cache. For any of the cache lines that have not been accessed during the defined assessment period, the individual valid bit associated therewith is set to a logic state that indicates the data in the associated cache line is invalid.
摘要翻译： 一种用于实现无刷嵌入式动态随机存取存储器（eDRAM）高速缓存设备的装置包括具有与具有多个高速缓存线的DRAM数据高速缓存相关联的高速缓存标签阵列的高速缓存结构，高速缓存标签阵列具有地址标签，有效的 位和对应于所述多个高速缓存行中的每一条的存取位; 并且每个访问位被配置为指示在定义的评估周期期间作为读取或写入操作的结果是否已经访问了相应的高速缓存行，所述定义的评估周期小于DRAM数据高速缓存中的数据的保留时间。 对于在定义的评估周期期间未被访问的任何高速缓存行，将与其相关联的单个有效位设置为指示相关联的高速缓存行中的数据无效的逻辑状态。
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2.发明申请STRUCTURE FOR IMPLEMENTING REFRESHLESS SINGLE TRANSISTOR CELL eDRAM FOR HIGH PERFORMANCE MEMORY APPLICATIONS 审中-公开用于实现高性能存储器应用的无刷单晶片单元的结构公开(公告)号：US20090144504A1
公开(公告)日：2009-06-04
申请号：US12116234
申请日：2008-05-07
IPC分类号： G06F12/00
CPC分类号： G06F12/0893
摘要： A design structure embodied in a machine readable medium used in a design process includes a cache structure having a cache tag array associated with a eDRAM data cache comprising a plurality of cache lines, the cache tag array having an address tag, a valid bit and an access bit corresponding to each of the plurality of cache lines; and each access bit configured to indicate whether the corresponding cache line has been accessed as a result of a read or a write operation during a defined assessment period, which is smaller than retention time of data in the DRAM data cache; wherein, for any of the cache lines not accessed as a result of a read or a write operation during the defined assessment period, the individual valid bit associated therewith is set to a logic state that indicates the data in the associated cache line is invalid.
摘要翻译： 体现在设计过程中使用的机器可读介质中的设计结构包括具有与包括多个高速缓存线的eDRAM数据高速缓存相关联的高速缓存标签阵列的高速缓存结构，高速缓存标签阵列具有地址标签，有效位和 对应于所述多个高速缓存行中的每一个的存取位; 并且每个访问位被配置为指示在定义的评估周期期间作为读取或写入操作的结果是否已经访问了相应的高速缓存行，其小于DRAM数据高速缓存中的数据的保留时间; 其中，对于在定义的评估周期期间作为读取或写入操作的结果未被访问的任何高速缓存行，将与其相关联的各个有效位设置为指示相关联的高速缓存行中的数据无效的逻辑状态。
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3.发明申请METHOD AND SYSTEM FOR IMPLEMENTING DYNAMIC REFRESH PROTOCOLS FOR DRAM BASED CACHE 有权用于实现基于DRAM的缓存的动态刷新协议的方法和系统公开(公告)号：US20090144506A1
公开(公告)日：2009-06-04
申请号：US11949904
申请日：2007-12-04
申请人： John E. Barth, JR. , Philip G. Emma , Erik L. Hedberg , Hillery C. Hunter , Peter A. Sandon , Vijayalakshmi Srinivasan , Arnold S. Tran
发明人： John E. Barth, JR. , Philip G. Emma , Erik L. Hedberg , Hillery C. Hunter , Peter A. Sandon , Vijayalakshmi Srinivasan , Arnold S. Tran
IPC分类号： G06F12/08
CPC分类号： G06F12/0893 , Y02D10/13
摘要： A method for implementing dynamic refresh protocols for DRAM based cache includes partitioning a DRAM cache into a refreshable portion and a non-refreshable portion, and assigning incoming individual cache lines to one of the refreshable portion and the non-refreshable portion of the cache based on a usage history of the cache lines. Cache lines corresponding to data having a usage history below a defined frequency are assigned to the refreshable portion of the cache, and cache lines corresponding to data having a usage history at or above the defined frequency are assigned to the non-refreshable portion of the cache.
摘要翻译： 一种用于实现基于DRAM的高速缓存的动态刷新协议的方法包括将DRAM高速缓存划分为可刷新部分和不可刷新部分，以及基于以下方式将输入的各个高速缓存行分配到高速缓存的可刷新部分和不可刷新部分之一： 高速缓存行的使用历史。 对应于具有低于定义频率的使用历史的数据的高速缓存行被分配给高速缓存的可刷新部分，并且与具有等于或高于定义频率的使用历史的数据相对应的高速缓存行被分配给高速缓存的不可刷新部分 。
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公开(公告)号：US20090193186A1
公开(公告)日：2009-07-30
申请号：US12019818
申请日：2008-01-25
申请人： John E. Barth, JR. , Philip G. Emma , Hillery C. Hunter , Vijayalakshmi Srinivasan , Arnold S. Tran
发明人： John E. Barth, JR. , Philip G. Emma , Hillery C. Hunter , Vijayalakshmi Srinivasan , Arnold S. Tran
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0862 , Y02D10/13
摘要： An embedded DRAM (eDRAM) having multi-use refresh cycles is described. In one embodiment, there is a multi-level cache memory system that comprises a pending write queue configured to receive pending prefetch operations from at least one of the levels of cache. A prefetch queue is configured to receive prefetch operations for at least one of the levels of cache. A refresh controller is configured to determine addresses within each level of cache that are due for a refresh. The refresh controller is configured to assert a refresh write-in signal to write data supplied from the pending write queue specified for an address due for a refresh rather than refresh existing data. The refresh controller asserts the refresh write-in signal in response to a determination that there is pending data to supply to the address specified to have the refresh. The refresh controller is further configured to assert a refresh read-out signal to send refreshed data to the prefetch queue of a higher level of cache as a prefetch operation in response to a determination that the refreshed data is useful.
摘要翻译： 描述了具有多次使用刷新周期的嵌入式DRAM（eDRAM）。 在一个实施例中，存在多级高速缓冲存储器系统，其包括被配置为从高速缓存的至少一个级别接收未决的预取操作的等待写入队列。 预取队列被配置为接收至少一个缓存级别的预取操作。 刷新控制器被配置为确定要刷新到期的每个高速缓存级别内的地址。 刷新控制器被配置为断言刷新写入信号以写入从针对刷新而不是刷新现有数据的地址指定的等待写入队列提供的数据。 刷新控制器响应于确定有未决数据提供给被指定为刷新的地址，来确定刷新写入信号。 刷新控制器还被配置为响应于确定刷新的数据是有用的，将更新读出信号断言以将更新的数据发送到较高级别的高速缓存的预取队列作为预取操作。
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5.发明申请公开(公告)号：US20130262792A1
公开(公告)日：2013-10-03
申请号：US13431108
申请日：2012-03-27
申请人： John E. Barth, JR. , Joab D. Henderson , Ryan J. Pennington , Anuwat Saetow , Robert B. Tremaine , Kenneth L. Wright
发明人： John E. Barth, JR. , Joab D. Henderson , Ryan J. Pennington , Anuwat Saetow , Robert B. Tremaine , Kenneth L. Wright
IPC分类号： G06F12/00
CPC分类号： G06F1/3275 , Y02D10/13 , Y02D10/14
摘要： An embodiment is a method includes writing a first set of memory device parameters to a first mode register in a memory device, wherein the first set of memory device parameters correspond to a first frequency, monitoring selected parameters for the memory system while the memory device operates at the first frequency and predicting a second frequency that the memory device will operate at subsequent to the first frequency, the predicting being based on the monitored selected parameters. The method further includes writing a second set of memory device parameters to second mode register in the memory device, receiving a frequency change request at a memory controller associated with the memory device, the frequency change request to operate at a new frequency and updating the first mode register with the second set of memory device parameters from the second mode register responsive to the new frequency being equal to the second frequency.
摘要翻译： 实施例是一种方法，包括将第一组存储器件参数写入存储器件中的第一模式寄存器，其中第一组存储器件参数对应于第一频率，在存储器件操作期间监视存储器系统的选定参数 在第一频率处，并且预测存储器设备将在第一频率之后操作的第二频率，所述预测基于所监视的所选择的参数。 该方法还包括将第二组存储器件参数写入存储器件中的第二模式寄存器，在与存储器件相关联的存储器控制器处接收频率改变请求，频率改变请求以新频率操作并更新第一 模式寄存器，响应于新频率等于第二频率，来自第二模式寄存器的第二组存储器件参数。
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公开(公告)号：US20110267916A1
公开(公告)日：2011-11-03
申请号：US12770976
申请日：2010-04-30
申请人： John E. Barth, JR.
发明人： John E. Barth, JR.
IPC分类号： G11C5/14
CPC分类号： G11C11/4091
摘要： A direct sense memory array architecture and method of operation includes a plurality of memory cells where a bit-line restore voltage level is optimized to reduce memory cell leakage during a first inactive period, and a bit-line preset voltage level is optimized for signal sensing during a second active period. The architecture includes a sense head having of a pair of cross coupled gated inverters. Each of the gated inverters is responsive to a first and second gate control signal which can independently gate a power supply to the inverter circuit within each gated inverter. During the second active period, a first gated inverter senses the data state on the first bit-line, and a second gated inverter performs a preset and write-back function on the first bit-line.
摘要翻译： 直接读出存储器阵列结构和操作方法包括多个存储器单元，其中位线恢复电压电平被优化以在第一非活动时段期间减少存储器单元泄漏，并且位线预设电压电平被优化用于信号感测 在第二个活跃期间。 该架构包括具有一对交叉耦合门控反相器的感测头。 每个门控逆变器响应于第一和第二门控制信号，该第一和第二门控制信号可以独立地对每个门控逆变器内的逆变器电路的电源供电。 在第二活动期间，第一选通逆变器检测第一位线上的数据状态，第二门控反相器在第一位线上执行预置和回写功能。
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公开(公告)号：US20110177659A1
公开(公告)日：2011-07-21
申请号：US13075552
申请日：2011-03-30
IPC分类号： H01L21/336
CPC分类号： H01L29/78615
摘要： A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a body contact disposed under the body/channel region and in the insulator layer. The body contact electrically connects with and contacts with the body/channel region of the semiconductor device and the substrate, to thereby form an ohmic contact and to eliminate floating body effects.
摘要翻译： 公开了半导体结构。 半导体结构包括有源半导体层，具有设置在有源半导体层顶部的栅极的半导体器件以及设置在有源半导体层内的源极和漏极区域以及主体/沟道区域，具有第一和第二 所述第一侧与所述有源半导体层相邻，与所述绝缘体层的第二侧相邻配置的基板，设置在所述主体/沟道区域的下方以及所述绝缘体层的主体接触部。 体接触与半导体器件和衬底的主体/沟道区域电连接并与其接触，从而形成欧姆接触并消除浮体效应。
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公开(公告)号：US20100001788A1
公开(公告)日：2010-01-07
申请号：US12168136
申请日：2008-07-06
CPC分类号： H02M3/07
摘要： A system to evaluate charge pump output may include a comparator to compare a charge pump output voltage to a reference voltage to generate a comparison result. The system may also include a divider to divide down a clock signal. The system may further include a logical conjunction unit to operate on the comparison result and the divided down clock signal.
摘要翻译： 用于评估电荷泵输出的系统可以包括比较器，用于将电荷泵输出电压与参考电压进行比较以产生比较结果。 该系统还可以包括用于分频时钟信号的分频器。 该系统还可以包括对比较结果和划分的下降时钟信号进行操作的逻辑连接单元。
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公开(公告)号：US20130285193A1
公开(公告)日：2013-10-31
申请号：US13457601
申请日：2012-04-27
CPC分类号： H01L28/40 , H01L21/84 , H01L27/1203 , H01L28/91 , H01L29/66181 , H01L29/945
摘要： A structure forming a metal-insulator-metal (MIM) trench capacitor is disclosed. The structure comprises a multi-layer substrate having a metal layer and at least one dielectric layer. A trench is etched into the substrate, passing through the metal layer. The trench is lined with a metal material that is in contact with the metal layer, which comprises a first node of a capacitor. A dielectric material lines the metal material in the trench. The trench is filled with a conductor. The dielectric material that lines the metal material separates the conductor from the metal layer and the metal material lining the trench. The conductor comprises a second node of the capacitor.
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公开(公告)号：US20100157698A1
公开(公告)日：2010-06-24
申请号：US12343554
申请日：2008-12-24
申请人： John E. Barth, JR.
发明人： John E. Barth, JR.
IPC分类号： G11C7/06
CPC分类号： G11C7/065 , G11C7/067 , G11C11/4091
摘要： According to an embodiment of the invention, a sense amplifier for, e.g., an array of DRAM data storage cells includes one or more amplifier stages connected together in series. The amplifier stages together form the sense amplifier for the DRAM array. Each amplifier stage includes an isolation capacitor to reduce to a relatively small value any mismatch between the threshold voltages of the transistors within each amplifier stage. A bitline from the DRAM array of memory cells connects to the first amplifier stage. An output from the last amplifier stage connects to a write back switch, the output of which connects to the bitline at the input of the first amplifier stage.
摘要翻译： 根据本发明的实施例，用于例如DRAM数据存储单元的阵列的读出放大器包括串联连接在一起的一个或多个放大器级。 放大器级一起形成用于DRAM阵列的读出放大器。 每个放大器级包括隔离电容器，以将每个放大器级内的晶体管的阈值电压之间的失配降至相对较小的值。 存储器单元的DRAM阵列的位线连接到第一放大器级。 来自最后一个放大器级的输出端连接到写回开关，其回输开关在第一放大器级的输入处连接到位线。
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