公开(公告)号：US20090144507A1

公开(公告)日：2009-06-04

申请号：US11950015

申请日：2007-12-04

申请人： John E. Barth, JR. ,  Erik L. Hedberg ,  Robert M. Houle ,  Hillery C. Hunter ,  Peter A. Sandon

发明人： John E. Barth, JR. ,  Erik L. Hedberg ,  Robert M. Houle ,  Hillery C. Hunter ,  Peter A. Sandon

IPC分类号： G06F12/08

CPC分类号： G06F12/0893 ,  G06F12/0891 ,  Y02D10/13

摘要： An apparatus for implementing a refreshless, embedded dynamic random access memory (eDRAM) cache device includes a cache structure having a cache tag array associated with a DRAM data cache with a plurality of cache lines, the cache tag array having an address tag, a valid bit and an access bit corresponding to each of the plurality of cache lines; and each access bit configured to indicate whether the corresponding cache line has been accessed as a result of a read or a write operation during a defined assessment period, the defined assessment period being smaller than retention time of data in the DRAM data cache. For any of the cache lines that have not been accessed during the defined assessment period, the individual valid bit associated therewith is set to a logic state that indicates the data in the associated cache line is invalid.

摘要翻译： 一种用于实现无刷嵌入式动态随机存取存储器（eDRAM）高速缓存设备的装置包括具有与具有多个高速缓存线的DRAM数据高速缓存相关联的高速缓存标签阵列的高速缓存结构，高速缓存标签阵列具有地址标签，有效的 位和对应于所述多个高速缓存行中的每一条的存取位; 并且每个访问位被配置为指示在定义的评估周期期间作为读取或写入操作的结果是否已经访问了相应的高速缓存行，所述定义的评估周期小于DRAM数据高速缓存中的数据的保留时间。 对于在定义的评估周期期间未被访问的任何高速缓存行，将与其相关联的单个有效位设置为指示相关联的高速缓存行中的数据无效的逻辑状态。

公开(公告)号：US20090144504A1

公开(公告)日：2009-06-04

申请号：US12116234

申请日：2008-05-07

申请人： John E. Barth, JR. ,  Erik L. Hedberg ,  Robert M. Houle ,  Hillery C. Hunter ,  Peter A. Sandon

发明人： John E. Barth, JR. ,  Erik L. Hedberg ,  Robert M. Houle ,  Hillery C. Hunter ,  Peter A. Sandon

IPC分类号： G06F12/00

CPC分类号： G06F12/0893

摘要： A design structure embodied in a machine readable medium used in a design process includes a cache structure having a cache tag array associated with a eDRAM data cache comprising a plurality of cache lines, the cache tag array having an address tag, a valid bit and an access bit corresponding to each of the plurality of cache lines; and each access bit configured to indicate whether the corresponding cache line has been accessed as a result of a read or a write operation during a defined assessment period, which is smaller than retention time of data in the DRAM data cache; wherein, for any of the cache lines not accessed as a result of a read or a write operation during the defined assessment period, the individual valid bit associated therewith is set to a logic state that indicates the data in the associated cache line is invalid.

摘要翻译： 体现在设计过程中使用的机器可读介质中的设计结构包括具有与包括多个高速缓存线的eDRAM数据高速缓存相关联的高速缓存标签阵列的高速缓存结构，高速缓存标签阵列具有地址标签，有效位和 对应于所述多个高速缓存行中的每一个的存取位; 并且每个访问位被配置为指示在定义的评估周期期间作为读取或写入操作的结果是否已经访问了相应的高速缓存行，其小于DRAM数据高速缓存中的数据的保留时间; 其中，对于在定义的评估周期期间作为读取或写入操作的结果未被访问的任何高速缓存行，将与其相关联的各个有效位设置为指示相关联的高速缓存行中的数据无效的逻辑状态。

公开(公告)号：US08024513B2

公开(公告)日：2011-09-20

申请号：US11949904

申请日：2007-12-04

申请人： John E. Barth, Jr. ,  Philip G. Emma ,  Erik L. Hedberg ,  Hillery C. Hunter ,  Peter A. Sandon ,  Vijayalakshmi Srinivasan ,  Arnold S. Tran

发明人： John E. Barth, Jr. ,  Philip G. Emma ,  Erik L. Hedberg ,  Hillery C. Hunter ,  Peter A. Sandon ,  Vijayalakshmi Srinivasan ,  Arnold S. Tran

IPC分类号： G06F12/00

CPC分类号： G06F12/0893 ,  Y02D10/13

摘要： A method for implementing dynamic refresh protocols for DRAM based cache includes partitioning a DRAM cache into a refreshable portion and a non-refreshable portion, and assigning incoming individual cache lines to one of the refreshable portion and the non-refreshable portion of the cache based on a usage history of the cache lines. Cache lines corresponding to data having a usage history below a defined frequency are assigned to the refreshable portion of the cache, and cache lines corresponding to data having a usage history at or above the defined frequency are assigned to the non-refreshable portion of the cache.

摘要翻译： 一种用于实现基于DRAM的高速缓存的动态刷新协议的方法包括将DRAM高速缓存划分为可刷新部分和不可刷新部分，以及基于以下方式将输入的各个高速缓存行分配到高速缓存的可刷新部分和不可刷新部分之一： 高速缓存行的使用历史。 对应于具有低于定义频率的使用历史的数据的缓存线被分配给高速缓存的可刷新部分，并且与具有等于或高于定义频率的使用历史的数据相对应的高速缓存行被分配给高速缓存的不可刷新部分 。

公开(公告)号：US20090144506A1

公开(公告)日：2009-06-04

申请号：US11949904

申请日：2007-12-04

申请人： John E. Barth, JR. ,  Philip G. Emma ,  Erik L. Hedberg ,  Hillery C. Hunter ,  Peter A. Sandon ,  Vijayalakshmi Srinivasan ,  Arnold S. Tran

发明人： John E. Barth, JR. ,  Philip G. Emma ,  Erik L. Hedberg ,  Hillery C. Hunter ,  Peter A. Sandon ,  Vijayalakshmi Srinivasan ,  Arnold S. Tran

IPC分类号： G06F12/08

CPC分类号： G06F12/0893 ,  Y02D10/13

摘要： A method for implementing dynamic refresh protocols for DRAM based cache includes partitioning a DRAM cache into a refreshable portion and a non-refreshable portion, and assigning incoming individual cache lines to one of the refreshable portion and the non-refreshable portion of the cache based on a usage history of the cache lines. Cache lines corresponding to data having a usage history below a defined frequency are assigned to the refreshable portion of the cache, and cache lines corresponding to data having a usage history at or above the defined frequency are assigned to the non-refreshable portion of the cache.

摘要翻译： 一种用于实现基于DRAM的高速缓存的动态刷新协议的方法包括将DRAM高速缓存划分为可刷新部分和不可刷新部分，以及基于以下方式将输入的各个高速缓存行分配到高速缓存的可刷新部分和不可刷新部分之一： 高速缓存行的使用历史。 对应于具有低于定义频率的使用历史的数据的高速缓存行被分配给高速缓存的可刷新部分，并且与具有等于或高于定义频率的使用历史的数据相对应的高速缓存行被分配给高速缓存的不可刷新部分 。

公开(公告)号：US08108609B2

公开(公告)日：2012-01-31

申请号：US12126499

申请日：2008-05-23

申请人： John E. Barth ,  Philip G. Emma ,  Erik L. Hedberg ,  Hillery C. Hunter ,  Peter A. Sandon ,  Vijayalakshmi Srinivasan ,  Arnold S. Tran

发明人： John E. Barth ,  Philip G. Emma ,  Erik L. Hedberg ,  Hillery C. Hunter ,  Peter A. Sandon ,  Vijayalakshmi Srinivasan ,  Arnold S. Tran

IPC分类号： G06F12/00

CPC分类号： G06F12/0893 ,  G06F2212/304 ,  Y02D10/13

摘要： A hardware description language (HDL) design structure embodied on a machine-readable data storage medium includes elements that when processed in a computer aided design system generates a machine executable representation of a device for implementing dynamic refresh protocols for DRAM based cache. The HDL design structure further includes a DRAM cache partitioned into a refreshable portion and a non-refreshable portion; and a cache controller configured to assign incoming individual cache lines to one of the refreshable portion and the non-refreshable portion of the cache based on a usage history of the cache lines; wherein cache lines corresponding to data having a usage history below a defined frequency are assigned by the controller to the refreshable portion of the cache, and cache lines corresponding to data having a usage history at or above the defined frequency are assigned to the non-refreshable portion of the cache.

摘要翻译： 体现在机器可读数据存储介质上的硬件描述语言（HDL）设计结构包括当在计算机辅助设计系统中处理时生成用于实现基于DRAM的高速缓存的动态刷新协议的设备的机器可执行表示的元件。 HDL设计结构还包括划分为可刷新部分和不可刷新部分的DRAM高速缓存; 以及高速缓存控制器，被配置为基于所述高速缓存行的使用历史将输入的各个高速缓存行分配给所述高速缓存的可刷新部分和不可刷新部分之一; 其中对应于具有低于定义频率的使用历史的数据的高速缓存行被控制器分配给高速缓存的可刷新部分，并且与具有等于或高于定义频率的使用历史的数据相对应的高速缓存行被分配给不可刷新 部分缓存。

公开(公告)号：US20090144492A1

公开(公告)日：2009-06-04

申请号：US12126499

申请日：2008-05-23

申请人： John E. Barth ,  Philip G. Emma ,  Erik L. Hedberg ,  Hillery C. Hunter ,  Peter A. Sandon ,  Vijayalakshmi Srinivasan ,  Arnold S. Tran

发明人： John E. Barth ,  Philip G. Emma ,  Erik L. Hedberg ,  Hillery C. Hunter ,  Peter A. Sandon ,  Vijayalakshmi Srinivasan ,  Arnold S. Tran

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0893 ,  G06F2212/304 ,  Y02D10/13

摘要： A hardware description language (HDL) design structure embodied on a machine-readable data storage medium includes elements that when processed in a computer aided design system generates a machine executable representation of a device for implementing dynamic refresh protocols for DRAM based cache. The HDL design structure further includes a DRAM cache partitioned into a refreshable portion and a non-refreshable portion; and a cache controller configured to assign incoming individual cache lines to one of the refreshable portion and the non-refreshable portion of the cache based on a usage history of the cache lines; wherein cache lines corresponding to data having a usage history below a defined frequency are assigned by the controller to the refreshable portion of the cache, and cache lines corresponding to data having a usage history at or above the defined frequency are assigned to the non-refreshable portion of the cache.

摘要翻译： 体现在机器可读数据存储介质上的硬件描述语言（HDL）设计结构包括当在计算机辅助设计系统中处理时生成用于实现基于DRAM的高速缓存的动态刷新协议的设备的机器可执行表示的元件。 HDL设计结构还包括划分为可刷新部分和不可刷新部分的DRAM高速缓存; 以及高速缓存控制器，被配置为基于所述高速缓存行的使用历史将输入的各个高速缓存行分配给所述高速缓存的可刷新部分和不可刷新部分之一; 其中对应于具有低于定义频率的使用历史的数据的高速缓存行被控制器分配给高速缓存的可刷新部分，并且与具有等于或高于定义频率的使用历史的数据相对应的高速缓存行被分配给不可刷新 部分缓存。

公开(公告)号：US06574763B1

公开(公告)日：2003-06-03

申请号：US09473886

申请日：1999-12-28

申请人： Claude L. Bertin ,  Erik L. Hedberg ,  Russell J. Houghton ,  William R. Tonti

发明人： Claude L. Bertin ,  Erik L. Hedberg ,  Russell J. Houghton ,  William R. Tonti

IPC分类号： G01R3128

CPC分类号： G01R31/287

摘要： A burn-in process is provided for a memory array having redundant bits and addressable storage locations. The burn-in process includes the steps of raising the temperature of the memory array to a pre-determined temperature, testing all bits in the array, detecting faulty bits and operable bits, replacing faulty bits with redundant operable bits, correcting any defects in the array in-situ, and lowering the temperature of the memory array to ambient temperature to complete the burn-in process. An apparatus for carrying out the above process is provided that includes a test circuit for generating a test pattern and for applying the test pattern to the memory array so as to test all bits within the memory array. A comparison circuit, coupled to the test circuit and adapted to couple to the memory array, compares an actual response and an expected response of the memory array to the test pattern and detects faulty and operable bits based thereon. A failed address buffer register, coupled to the comparison circuit and to the test circuit, stores an address of each addressable storage location that has a faulty bit. Sparing control logic, coupled to the failed address buffer register and adapted to couple to the memory array, reads out each address stored by the failed address buffer register and replaces each faulty bit with a redundant operable bit.

摘要翻译： 为具有冗余位和可寻址存储位置的存储器阵列提供老化过程。 老化过程包括以下步骤：将存储器阵列的温度升高到预定温度，测试阵列中的所有位，检测故障位和可操作位，用冗余的可操作位代替故障位，校正在 阵列原位，并将存储器阵列的温度降低到环境温度以完成老化过程。 提供了一种用于执行上述处理的装置，其包括用于生成测试图案并将测试图案应用于存储器阵列的测试电路，以便测试存储器阵列内的所有位。 耦合到测试电路并且适于耦合到存储器阵列的比较电路将存储器阵列的实际响应和预期响应与测试模式进行比较，并基于此检测故障和可操作的位。 耦合到比较电路和测试电路的故障地址缓冲寄存器存储具有错误位的每个可寻址存储位置的地址。 冗余控制逻辑耦合到故障地址缓冲寄存器并适于耦合到存储器阵列，读出由故障地址缓冲寄存器存储的每个地址，并用冗余可操作位替换每个故障位。

公开(公告)号：US5969997A

公开(公告)日：1999-10-19

申请号：US942825

申请日：1997-10-02

申请人： Michael P. Clinton ,  Marc R. Faucher ,  Erik L. Hedberg ,  Mark W. Kellogg ,  Wilbur D. Pricer

发明人： Michael P. Clinton ,  Marc R. Faucher ,  Erik L. Hedberg ,  Mark W. Kellogg ,  Wilbur D. Pricer

IPC分类号： G11C11/41 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  G11C15/00

CPC分类号： G11C11/409 ,  G11C11/407

摘要： A high speed Random Access Memory (RAM) array device includes several logical banks, each of which can be uniquely addressed. Each of these logical banks contains a unique memory array segment and associated page register, the latter serving as a temporary storage location during high-speed page hit operations. To reduce latency during an initial page hit, further array optimization is realized by segmenting each logical bank into two segments with one, smaller segment, comprising a faster random access memory (FRAM) for storing initial data in a data stream. A high speed page register connects the FRAM directly to a multiplexer/demultiplexer connected to the device I/O ports bypassing an internal bus protocol such that the initial data can be transferred between the FRAM and the I/O ports faster thereby improving page-hit latency. Hence, segmenting the logical banks to include only a small high speed segment results in a performance gain approaching what could be achieved by implementing the entire memory device with a high speed FRAM, but at much lower cost.

摘要翻译： 高速随机存取存储器（RAM）阵列器件包括几个逻辑存储体，每个逻辑存储体可以被唯一地寻址。 这些逻辑组中的每一个包含唯一的存储器阵列段和相关联的页寄存器，后者在高速页命中操作期间用作临时存储位置。 为了在初始页面命中期间减少延迟，通过将每个逻辑存储体分割成具有一个较小段的两个段来实现进一步的阵列优化，其包括用于在数据流中存储初始数据的更快的随机存取存储器（FRAM）。 高速页寄存器将FRAM直接连接到绕过内部总线协议的设备I / O端口连接的多路复用器/解复用器，从而可以更快地在FRAM和I / O端口之间传输初始数据，从而提高页命中率 潜伏。 因此，将逻辑存储体分割为仅包含小的高速段导致通过以高速FRAM实现整个存储器件而可以以低得多的成本实现可达到的性能增益。

公开(公告)号：US5561622A

公开(公告)日：1996-10-01

申请号：US120993

申请日：1993-09-13

申请人： Claude L. Bertin ,  Wayne J. Howell ,  Erik L. Hedberg ,  Howard L. Kalter ,  Gordon A. Kelley, Jr.

发明人： Claude L. Bertin ,  Wayne J. Howell ,  Erik L. Hedberg ,  Howard L. Kalter ,  Gordon A. Kelley, Jr.

IPC分类号： G11C5/00 ,  H01L25/065 ,  G11C5/06 ,  H01L23/02

CPC分类号： H01L25/0657 ,  G11C5/06 ,  H01L2224/48091 ,  H01L2225/0651 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06596 ,  H01L2924/10253

摘要： An integrated memory cube structure and method of fabrication wherein stacked semiconductor memory chips are integrated by a controlling logic chip such that a more powerful memory architecture is defined with the functional appearance of a single, higher level memory chip. A memory/logic cube is formed having N memory chips and at least one logic chip, with each memory chip of the cube having M memory devices. The controlling logic chip coordinates external communication with the N memory chips such that a single memory chip architecture with N.times.M memory devices appears at the cube's I/O pins. A corresponding fabrication technique includes an approach for facilitating metallization patterning on the side surface of the memory subunit.

摘要翻译： 一种集成的存储立方体结构和制造方法，其中堆叠的半导体存储器芯片由控制逻辑芯片集成，使得更强大的存储器架构被定义为单个更高级存储器芯片的功能外观。 形成具有N个存储器芯片和至少一个逻辑芯片的存储器/逻辑立方体，其中立方体的每个存储器芯片具有M个存储器件。 控制逻辑芯片协调与N个存储器芯片的外部通信，使得具有NxM存储器件的单个存储器芯片架构出现在立方体的I / O引脚处。 相应的制造技术包括用于在存储器子单元的侧表面上促进金属化图案化的方法。

公开(公告)号：US5173906A

公开(公告)日：1992-12-22

申请号：US576646

申请日：1990-08-31

申请人： Jeffrey H. Dreibelbis ,  Erik L. Hedberg ,  John G. Petrovick, Jr.

发明人： Jeffrey H. Dreibelbis ,  Erik L. Hedberg ,  John G. Petrovick, Jr.

IPC分类号： G01R31/28 ,  G06F11/22 ,  G06F11/27 ,  G06F15/78 ,  G11C29/10 ,  G11C29/12 ,  G11C29/16 ,  G11C29/38 ,  G11C29/44 ,  H01L27/10

CPC分类号： G11C29/16 ,  G06F11/27 ,  G11C29/44 ,  G11C29/10 ,  G11C29/38

摘要： A built-in, i.e., on-chip, self-test system for a VLSI logic or memory module. A deterministic data pattern generator is provided on the VLSI chip, and operates to test a chip module and provide a fail/no-fail result, along with data identifying where the fail occurred. This location data is captured and made available for subsequent utilization. The built-in test circuitry is programmable, and is provided with a looping capability to provide enhanced burn-in testing, for example.