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公开(公告)号：US06815129B1
公开(公告)日：2004-11-09
申请号：US09669958
申请日：2000-09-26
申请人： John E. Bjorkholm , Daniel G. Stearns , Eric M. Gullikson , Daniel A. Tichenor , Scott D. Hector
发明人： John E. Bjorkholm , Daniel G. Stearns , Eric M. Gullikson , Daniel A. Tichenor , Scott D. Hector
IPC分类号： G03F900
CPC分类号： G03F7/705 , G03F7/70433 , G03F7/70941
摘要： A method for compensating for flare-induced critical dimensions (CD) changes in photolithography. Changes in the flare level results in undesirable CD changes. The method when used in extreme ultraviolet (EUV) lithography essentially eliminates the unwanted CD changes. The method is based on the recognition that the intrinsic level of flare for an EUV camera (the flare level for an isolated sub-resolution opaque dot in a bright field mask) is essentially constant over the image field. The method involves calculating the flare and its variation over the area of a patterned mask that will be imaged and then using mask biasing to largely eliminate the CD variations that the flare and its variations would otherwise cause. This method would be difficult to apply to optical or DUV lithography since the intrinsic flare for those lithographies is not constant over the image field.
摘要翻译： 用于补偿光刻中闪耀引起的临界尺寸（CD）变化的方法。 闪光水平的变化导致不良CD变化。 当用于极紫外（EUV）光刻技术时，该方法基本上消除了不必要的CD变化。 该方法基于这样的认识：对于EUV摄像机（对于明场掩模中的隔离的子分辨率不透明点的闪光级别）的本征水平在图像场上基本上是恒定的。 该方法包括计算闪耀及其在将被成像的图案化掩模的面积上的变化，然后使用掩模偏置来大大消除闪光及其变化否则将导致的CD变化。 这种方法将难以应用于光学或DUV光刻，因为用于这些平版印刷的本征闪光在图像场上不是恒定的。
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2.发明授权Reflective mask useful for transferring a pattern using extreme ultra violet (EUV) radiation and method of making the same 有权用于使用极紫外（EUV）辐射转印图案的反射罩及其制造方法公开(公告)号：US07282307B2
公开(公告)日：2007-10-16
申请号：US10872057
申请日：2004-06-18
申请人： Scott D. Hector , Sang-In Han
发明人： Scott D. Hector , Sang-In Han
IPC分类号： G03F1/00
摘要： An EUV mask (10, 309) includes an opening (26) that helps to attenuate and phase shift extreme ultraviolet radiation using a subtractive rather than additive method. A first embedded layer (20) and a second embedded layer (21) may be provided between a lower multilayer reflective stack (14) and an upper multilayer reflective stack (22) to ensure an appropriate and accurate depth of the opening (26), while allowing for defect inspection of the EUV mask (10, 309) and optional defect repair. An optional ARC layer (400) may be deposited in region (28) to reduce the amount of reflection within dark region (28). Alternately, a single embedded layer of hafnium oxide, zirconium oxide, tantalum silicon oxide, tantalum oxide, or the like, may be used in place of embedded layers (20, 21). Optimal thicknesses and locations of the various layers are described.
摘要翻译： EUV掩模（10,309）包括有助于使用减法而不是加法方法衰减和相移极紫外辐射的开口（26）。 第一嵌入层（20）和第二嵌入层（21）可以设置在下多层反射叠层（14）和上层多层反射叠层（22）之间，以确保开口（26）的适当且准确的深度， 同时允许对EUV面罩（10,309）的缺陷检查和可选的缺陷修复。 可以在区域（28）中沉积可选的ARC层（400）以减少暗区域（28）内的反射量。 或者，可以使用氧化铪，氧化锆，氧化钽，氧化钽等的单个嵌入层来代替嵌入层（20,21）。 描述各层的最佳厚度和位置。
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公开(公告)号：US20090158229A1
公开(公告)日：2009-06-18
申请号：US11958605
申请日：2007-12-18
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5081
摘要： A method of area compaction for integrated circuit layout design comprises determining physical extent boundaries for each layer of at least first circuit and second circuit building blocks. Determining physical extent boundaries includes determining for each respective layer of the first circuit and second circuit building blocks (i) a used portion and (ii) a free portion. The used portion corresponds to a functional portion of the respective circuit building block and the free portion corresponds to a non-functional portion of the respective circuit building block. The method further includes establishing packing keys with respect to the determined physical extent boundaries of each layer of the first circuit and second circuit building blocks, respectively. The packing keys define an interlocking characteristic for packing compaction of the corresponding first circuit or second circuit building block with another circuit building block.
摘要翻译： 集成电路布局设计的面积压缩方法包括确定至少第一电路和第二电路构建块的每层的物理范围边界。 确定物理范围边界包括确定第一电路的每个相应层和第二电路构建块（i）使用部分和（ii）自由部分。 所使用的部分对应于各个电路构建块的功能部分，并且自由部分对应于各个电路构建块的非功能部分。 该方法还包括分别相对于第一电路和第二电路构建块的每层的确定的物理范围边界建立包装密钥。 包装键限定了相应的第一电路或第二电路构建块与另一个电路构建块的压实的互锁特性。
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4.发明授权Attenuated phase shift mask for extreme ultraviolet lithography and method therefore 有权因此，用于极紫外光刻的衰减相移掩模和方法公开(公告)号：US06986974B2
公开(公告)日：2006-01-17
申请号：US10688589
申请日：2003-10-16
申请人： Sang-In Han , Scott D. Hector , Pawitter Mangat
发明人： Sang-In Han , Scott D. Hector , Pawitter Mangat
IPC分类号： G01F9/00
摘要： Methods and apparatus are provided for extreme ultraviolet phase shift masks. The apparatus comprises a substrate, a reflectance region, and an attenuating phase shifter. The reflectance region overlies the substrate. The attenuating phase shifter overlies the reflectance region. The attenuating phase shifter includes a plurality of openings that expose portions of the reflectance region. The attenuating phase shifter attenuates radiation through a combination of absorption and destructive interference. The method comprises projecting radiation having a wavelength less than 40 nanometers towards a mask having a plurality of openings through an attenuating phase shifter. The plurality of openings expose a reflectance region in the mask. The attenuating phase shifter is less than 700 angstroms thick. Radiation impinging on the reflectance region exposed by said plurality of openings is reflected whereas radiation impinging on the attenuating phase shifter is attenuated and shifted in phase. The attenuating phase shifter attenuates using absorption and destructive interference.
摘要翻译： 为极紫外相移掩模提供了方法和装置。 该装置包括基板，反射区域和衰减移相器。 反射区域覆盖基板。 衰减移相器覆盖反射区域。 衰减移相器包括暴露反射区域的部分的多个开口。 衰减移相器通过吸收和相消干扰的组合衰减辐射。 该方法包括通过衰减移相器将具有小于40纳米波长的辐射投射到具有多个开口的掩模。 多个开口暴露掩模中的反射区域。 衰减移相器的厚度小于700埃。 照射在由所述多个开口暴露的反射区域上的辐射被反射，而入射到衰减移相器上的辐射被衰减并相位移动。 衰减移相器使用吸收和相消干涉衰减。
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公开(公告)号：US06673520B2
公开(公告)日：2004-01-06
申请号：US09939184
申请日：2001-08-24
申请人： Sang-in Han , Pawitter Mangat , James R. Wasson , Scott D. Hector
发明人： Sang-in Han , Pawitter Mangat , James R. Wasson , Scott D. Hector
IPC分类号： G03F700
摘要： A desired pattern is formed in a photoresist layer that overlies a semiconductor wafer using a reflective mask. This mask is formed by consecutively depositing a reflective layer, an absorber layer and an anti-reflective (ARC) layer. The ARC layer is patterned according to the desired pattern. The ARC layer is inspected to find areas in which the desired pattern is not achieved. The ARC layer is then repaired to achieve the desired pattern with the absorber layer protecting the reflective layer. The desired pattern is transferred to the absorber layer to reveal the reflective portion of mask. Radiation is reflected off the reflective mask to the semiconductor wafer to expose the photoresist layer overlying the semiconductor wafer with the desired pattern.
摘要翻译： 在使用反射掩模覆盖在半导体晶片上的光致抗蚀剂层中形成期望的图案。 该掩模通过连续沉积反射层，吸收层和抗反射（ARC）层形成。 根据所需的图案对ARC层进行图案化。 检查ARC层以找到未实现所需图案的区域。 然后修复ARC层以实现期望的图案，其中吸收层保护反射层。 将期望的图案转移到吸收层以露出掩模的反射部分。 辐射从反射掩模反射到半导体晶片，以以期望的图案露出覆盖半导体晶片的光致抗蚀剂层。
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公开(公告)号：US06352803B1
公开(公告)日：2002-03-05
申请号：US09587836
申请日：2000-06-06
申请人： William Man-Wai Tong , John S. Taylor , Scott D. Hector , Pawitter J. S. Mangat , Alan R. Stivers , Patrick G. Kofron , Matthew A. Thompson
发明人： William Man-Wai Tong , John S. Taylor , Scott D. Hector , Pawitter J. S. Mangat , Alan R. Stivers , Patrick G. Kofron , Matthew A. Thompson
IPC分类号： G03F900
摘要： A process for creating a mask substrate involving depositing: 1) a coating on one or both sides of a low thermal expansion material EUVL mask substrate to improve defect inspection, surface finishing, and defect levels; and 2) a high dielectric coating, on the backside to facilitate electrostatic chucking and to correct for any bowing caused by the stress imbalance imparted by either other deposited coatings or the multilayer coating of the mask substrate. An film, such as TaSi, may be deposited on the front side and/or back of the low thermal expansion material before the material coating to balance the stress. The low thermal expansion material with a silicon overlayer and a silicon and/or other conductive underlayer enables improved defect inspection and stress balancing.
摘要翻译： 一种用于产生掩模基板的方法，包括沉积：1）在低热膨胀材料EUVL掩模基板的一侧或两侧上的涂层，以改善缺陷检查，表面光洁度和缺陷水平; 和2）在背面的高电介质涂层，以便于静电吸附并且校正由其它沉积涂层或掩模基底的多层涂层赋予的应力不平衡引起的任何弯曲。 在材料涂覆之前，诸如TaSi的膜可以沉积在低热膨胀材料的前侧和/或背面以平衡应力。 具有硅覆盖层和硅和/或其它导电底层的低热膨胀材料能够改善缺陷检查和应力平衡。
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公开(公告)号：US07904869B2
公开(公告)日：2011-03-08
申请号：US11958605
申请日：2007-12-18
IPC分类号： G06F9/455
CPC分类号： G06F17/5068 , G06F17/5081
摘要： A method of area compaction for integrated circuit layout design comprises determining physical extent boundaries for each layer of at least first circuit and second circuit building blocks. Determining physical extent boundaries includes determining for each respective layer of the first circuit and second circuit building blocks (i) a used portion and (ii) a free portion. The used portion corresponds to a functional portion of the respective circuit building block and the free portion corresponds to a non-functional portion of the respective circuit building block. The method further includes establishing packing keys with respect to the determined physical extent boundaries of each layer of the first circuit and second circuit building blocks, respectively. The packing keys define an interlocking characteristic for packing compaction of the corresponding first circuit or second circuit building block with another circuit building block.
摘要翻译： 集成电路布局设计的面积压缩方法包括确定至少第一电路和第二电路构建块的每层的物理范围边界。 确定物理范围边界包括确定第一电路的每个相应层和第二电路构建块（i）使用部分和（ii）自由部分。 所使用的部分对应于各个电路构建块的功能部分，并且自由部分对应于各个电路构建块的非功能部分。 该方法还包括分别相对于第一电路和第二电路构建块的每层的确定的物理范围边界建立包装密钥。 包装键限定了相应的第一电路或第二电路构建块与另一个电路构建块的压实的互锁特性。
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公开(公告)号：US06492067B1
公开(公告)日：2002-12-10
申请号：US09454674
申请日：1999-12-03
IPC分类号： G03F900
CPC分类号： G03F1/64 , G03F7/70983
摘要： A removable pellicle for a lithographic mask that provides active and robust particle protection, and which utilizes a traditional pellicle and two deployments of thermophoretic protection to keep particles off the mask. The removable pellicle is removably attached via a retaining structure to the mask substrate by magnetic attraction with either contacting or non-contacting magnetic capture mechanisms. The pellicle retaining structural is composed of an anchor piece secured to the mask substrate and a frame member containing a pellicle. The anchor piece and the frame member are in removable contact or non-contact by the magnetic capture or latching mechanism. In one embodiment, the frame member is retained in a floating (non-contact) relation to the anchor piece by magnetic levitation. The frame member and the anchor piece are provided with thermophoretic fins which are interdigitated to prevent particles from reaching the patterned area of the mask. Also, the anchor piece and mask are maintained at a higher temperature than the frame member and pellicle which also prevents particles from reaching the patterned mask area by thermophoresis. The pellicle can be positioned over the mask to provide particle protection during mask handling, inspection, and pumpdown, but which can be removed manually or robotically for lithographic use of the mask.
摘要翻译： 用于光刻掩模的可移除防护薄膜，其提供有效和坚固的颗粒保护，并且其利用传统的防护薄膜和两个部署热保护性保护以将颗粒保持在掩模上。 通过接触或非接触磁捕获机构的磁吸引，可除去的防护薄膜组件通过保持结构可拆卸地附接到掩模基板。 防护薄膜保持结构由固定到掩模基板的锚固件和包含防护薄膜的框架构件组成。 锚固件和框架构件通过磁捕获或锁定机构可拆卸地接触或非接触。 在一个实施例中，框架构件通过磁悬浮保持与锚固件的浮动（非接触）关系。 框架构件和锚固件设置有散热鳍片，其被交错以防止颗粒到达掩模的图案化区域。 此外，锚固件和掩模保持在比框架构件和防护薄膜更高的温度，其也通过热泳来防止颗粒到达图案化掩模区域。 防护薄膜组件可以位于掩模上方，以在掩模处理，检查和抽吸期间提供颗粒保护，但是可以手动或机器人地去除防护薄膜以用于掩模的光刻使用。
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9.发明授权Method for forming a lithographic mask used for patterning semiconductor die 失效用于形成用于图案化半导体管芯的光刻掩模的方法
公开(公告)号：US6001513A
公开(公告)日：1999-12-14
申请号：US97801
申请日：1998-06-16
申请人： Scott D. Hector
发明人： Scott D. Hector
CPC分类号： G03F7/704 , G03F1/76 , G03F7/2053 , G03F7/2059 , G03F7/70466 , G03F7/70475
摘要： A method of forming a lithographic mask, including exposing an energy beam on a first selected spot (118) on the patterning layer of a mask substrate, within a selected portion (117) on the patterning layer, and exposing an energy beam on a second selected spot (122) on the patterning layer. The selected portion corresponds to a lithographic feature (116) and has a boundary (128) including a plurality of boundary segments defining a polygon. The energy beam is exposed on the first selected spot (118) at a first dosage, and at the second selected spot (122) at a second dosage that does not equal the first dosage. According to the present invention, a lithographic feature (116) is provided on the lithographic mask and includes a serif (126), a portion of which is provided by altering the dosage level at the second selected spot.
摘要翻译： 一种形成光刻掩模的方法，包括在图案化层上的选定部分（117）内将能量束暴露在掩模衬底的图案化层上的第一选定点（118）上，并且在第二位置上暴露能量束 所选择的点（122）在图案层上。 所选择的部分对应于光刻特征（116）并且具有包括限定多边形的多个边界段的边界（128）。 能量束以第一剂量暴露在第一选定点（118）上，在第二选定点（122）以不等于第一剂量的第二剂量暴露。 根据本发明，光刻特征（116）设置在光刻掩模上，并且包括衬线（126），其一部分通过改变第二选定点处的剂量水平来提供。
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