公开(公告)号：US6049483A

公开(公告)日：2000-04-11

申请号：US368453

申请日：1999-08-03

申请人： John F. Schreck ,  David J. McElroy ,  Brian W. Huber

发明人： John F. Schreck ,  David J. McElroy ,  Brian W. Huber

IPC分类号： G11C5/14 ,  G11C16/12 ,  G11C16/14

CPC分类号： G11C16/14 ,  G11C16/12 ,  G11C5/145

摘要： Circuits for applying a programming voltage and erase voltage to memory cells in a nonvolatile memory device are disclosed. The reverse breakdown of p-n junctions within the memory cells is prevented by providing a clamping p-n junction in the path used to apply the program or erase voltage to the memory cells. The clamping p-n junction will breakdown before the p-n junctions within the memory cells, protecting the memory cells from the adverse effects of a reverse breakdown condition.

摘要翻译： 公开了用于向非易失性存储器件中的存储单元施加编程电压和擦除电压的电路。 通过在用于将编程或擦除电压施加到存储器单元的路径中提供钳位p-n结来防止存储器单元内的p-n结的反向击穿。 钳位p-n结将在存储器单元内的p-n结之前击穿，从而保护存储单元不受反向故障条件的不利影响。

公开(公告)号：US08379469B2

公开(公告)日：2013-02-19

申请号：US13361630

申请日：2012-01-30

申请人： Brian W. Huber ,  Jason M. Brown

发明人： Brian W. Huber ,  Jason M. Brown

IPC分类号： G11C7/00

CPC分类号： G11C7/12 ,  G11C11/4094

摘要： Some embodiments include apparatus and methods having a memory cell included in a device, a control line configured to receive a control signal to access the memory cell, and a first line configured to transfer information to and from the memory cell. The control signal has a first level during a first time interval and a second level during a second time interval of a memory operation. The apparatus and methods also include a module configured to reduce difference between a value of a voltage on the second line and a value of a voltage on a node of the device during a first time portion of the second time interval. Additional apparatus and methods are disclosed.

摘要翻译： 一些实施例包括具有包括在设备中的存储器单元的设备和方法，被配置为接收控制信号以访问存储器单元的控制线以及被配置为向存储单元传送信息和从存储单元传送信息的第一线。 控制信号在第一时间间隔期间具有第一电平，在存储器操作的第二时间间隔期间具有第二电平。 该装置和方法还包括被配置为在第二时间间隔的第一时间部分期间减小第二线路上的电压值与装置的节点上的电压值之间的差异的模块。 公开了附加的装置和方法。

公开(公告)号：US06791862B2

公开(公告)日：2004-09-14

申请号：US10339503

申请日：2003-01-09

申请人： Craig T. Salling ,  Brian W. Huber

发明人： Craig T. Salling ,  Brian W. Huber

IPC分类号： G11C1122

CPC分类号： H01L27/11502 ,  G11C11/22 ,  H01L27/11585 ,  H01L27/1159 ,  H01L29/78391

摘要： Depletion-mode ferroelectric transistors are adapted for use as non-volatile memory cells. Various embodiments are described having a diode interposed between the bit line and a source/drain region of the transistor for added margin against read disturb. Various additional embodiments are described having an array architecture such that two memory cells sharing the same bit line also share the same program line. Using this configuration, non-selected cells are readily supplied with gate/source voltages sufficient to maintain the cells in a deactivated state during read and write operations on selected cells.

摘要翻译： 耗尽型铁电晶体管适合用作非易失性存储单元。 描述了具有夹在晶体管的位线和源极/漏极区之间的二极管的各种实施例，用于增加读取干扰的余量。 描述具有阵列架构的各种附加实施例，使得共享相同位线的两个存储器单元也共享相同的程序行。 使用这种配置，非选择的单元容易地被提供有足够的栅极/源极电压，以便在对所选择的单元的读取和写入操作期间将单元维持在去激活状态。

公开(公告)号：US06462989B1

公开(公告)日：2002-10-08

申请号：US09870088

申请日：2001-05-30

申请人： Brian W. Huber

发明人： Brian W. Huber

IPC分类号： G11C1606

CPC分类号： G11C7/1057 ,  G11C7/1051

摘要： A technique is provided for reducing changes in the amount of a bias voltage that is applied to a device in an integrated circuit due to local changes on a bus providing the reference for the bias voltage signal. Local transients on the reference bus may occur due to the inductance of the integrated circuit packaging. To prevent the local transients from affecting the amount of bias applied to a device, the local bias signal is allowed to move common mode with the local reference signal by isolating the local bias signal from the bias source. The technique also provides for disabling the isolation of the local bias signal from the bias source in response to a control signal.

摘要翻译： 提供了一种技术，用于减少由于提供偏置电压信号的参考的总线上的局部变化而施加到集成电路中的器件的偏置电压的量的变化。 由于集成电路封装的电感，基准总线上的局部瞬变可能会发生。 为了防止局部瞬变影响施加到器件的偏置量，允许局部偏置信号通过将偏置源与局部偏置信号隔离而与局部参考信号移动共模。 该技术还提供了响应于控制信号禁止来自偏置源的局部偏置信号的隔离。

公开(公告)号：US06442096B2

公开(公告)日：2002-08-27

申请号：US09876646

申请日：2001-06-07

申请人： Brian W. Huber

发明人： Brian W. Huber

IPC分类号： G11C800

CPC分类号： G11C11/4087 ,  G11C7/1018 ,  G11C8/04

摘要： Improved methods and structures are provided that allow for fast access of a memory device. Embodiments of a structure include a memory device that comprises a decode logic circuitry that decodes an address. The memory device also includes a counter circuitry coupled to the decode logic circuitry that generates a counter value based on the decoded address. Other embodiments of a structure include a compare circuit that determines whether a page count is complete in a memory structure. The compare circuit includes a holding circuitry that includes a number of latches for holding an encoded version of a memory address. The compare circuit also includes a multiplexing circuitry coupled to the holding circuitry. The multiplexing circuitry receives the encoded version of the memory address from the holding circuitry and a decoded version of the memory address from a decoder, such that the multiplexing circuitry uses the encoded version to select one bit of the decoded version of the memory address to determine whether the page count is complete for the memory structure. Embodiments of the present invention also includes methods, other structures as well as systems incorporating such structures all formed according to the methods provided in this application.

摘要翻译： 提供了改进的方法和结构，其允许快速访问存储器设备。 结构的实施例包括存储器件，其包括解码地址的解码逻辑电路。 存储器件还包括耦合到解码逻辑电路的计数器电路，其基于解码的地址生成计数器值。 结构的其他实施例包括确定存储器结构中页数是否完成的比较电路。 比较电路包括保持电路，该保持电路包括用于保持存储器地址的编码版本的多个锁存器。 比较电路还包括耦合到保持电路的复用电路。 多路复用电路从保持电路接收存储器地址的编码版本和来自解码器的存储器地址的解码版本，使得复用电路使用编码版本来选择存储器地址的解码版本的一个位以确定 内存结构的页数是否完整。 本发明的实施例还包括方法，其他结构以及结合这种结构的系统，其全部根据本申请中提供的方法形成。

公开(公告)号：US06380800B1

公开(公告)日：2002-04-30

申请号：US09475164

申请日：1999-12-30

申请人： Brian W. Huber

发明人： Brian W. Huber

IPC分类号： H03B100

CPC分类号： H02M1/12 ,  G11C5/145 ,  H02M3/07

摘要： A method and apparatus for filtering an output voltage of a charge pump to reduce peak values which cause stress. A charge pump generates a pumped voltage which is filtered by an RC filter, for example a one or two Pi filter. The filter reduces the peak values of pump output voltage while reducing the amount of capacitance (and corresponding die size) required.

摘要翻译： 一种用于对电荷泵的输出电压进行滤波以减少引起应力的峰值的方法和装置。 电荷泵产生被RC滤波器过滤的泵浦电压，例如一个或两个Pi滤波器。 滤波器可减少泵输出电压的峰值，同时减少所需的电容量（和相应的管芯尺寸）。

公开(公告)号：US06219294B1

公开(公告)日：2001-04-17

申请号：US09482575

申请日：2000-01-13

申请人： Brian W. Huber ,  Mansour Fardad ,  Roger D. Norwood

发明人： Brian W. Huber ,  Mansour Fardad ,  Roger D. Norwood

IPC分类号： G11C700

CPC分类号： G11C5/143 ,  G11C7/06 ,  G11C8/08 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4091

摘要： A DRAM memory device having two sets of power buses is provided. Each set includes a first bus having a first potential and a second bus having a second potential, both of which are required to activate a row of memory within a bank of memory. A first row is activated while it is connected to the first set of buses. If it is detected that the activation of a second row connected to the first set of buses will cause a power bump when it is time to deactivate the first row, the first row is switched over to the second set of buses prior to the activation of the second row. The first row can be precharged with the voltages from the second set of buses and the second row can be activated with the voltages from the first set of buses. Thus, the first row can be precharged without being adversely effected by the power bump on the first set of buses which improves the pause performance of the DRAM.

摘要翻译： 提供具有两组电源总线的DRAM存储器件。 每个集合包括具有第一电位的第一总线和具有第二电位的第二总线，两者都需要激活存储器组内的一行存储器。 第一行在连接到第一组总线时被激活。 如果检测到当连接到第一组总线的第二行的激活将在停止第一行的时间时引起功率凸起，则在激活第一行之前将第一行切换到第二组总线 第二行。 可以利用来自第二组总线的电压对第一行进行预充电，并且可以利用来自第一组总线的电压来激活第二行。 因此，第一行可以被预充电而不受第一组总线上的功率凸块的不利影响，这提高了DRAM的暂停性能。

公开(公告)号：US20120127808A1

公开(公告)日：2012-05-24

申请号：US13361630

申请日：2012-01-30

申请人： Brian W. Huber ,  Jason M. Brown

发明人： Brian W. Huber ,  Jason M. Brown

IPC分类号： G11C7/00

CPC分类号： G11C7/12 ,  G11C11/4094

摘要： Some embodiments include apparatus and methods having a memory cell included in a device, a control line configured to receive a control signal to access the memory cell, and a first line configured to transfer information to and from the memory cell. The control signal has a first level during a first time interval and a second level during a second time interval of a memory operation. The apparatus and methods also include a module configured to reduce difference between a value of a voltage on the second line and a value of a voltage on a node of the device during a first time portion of the second time interval. Additional apparatus and methods are disclosed.

摘要翻译： 一些实施例包括具有包括在设备中的存储器单元的设备和方法，被配置为接收控制信号以访问存储器单元的控制线以及被配置为向存储单元传送信息和从存储单元传送信息的第一线。 控制信号在第一时间间隔期间具有第一电平，在存储器操作的第二时间间隔期间具有第二电平。 该装置和方法还包括被配置为在第二时间间隔的第一时间部分期间减小第二线路上的电压值与装置的节点上的电压值之间的差异的模块。 公开了附加的装置和方法。

公开(公告)号：US07529318B2

公开(公告)日：2009-05-05

申请号：US11271544

申请日：2005-11-10

申请人： Brian W. Huber

发明人： Brian W. Huber

IPC分类号： H04L27/00

CPC分类号： G11C7/1084 ,  G11C7/1078

摘要： A circuit and method reduces noise signals coupled to a reference voltage used by a digital differential input receiver having an input that is coupled to an input/output terminal. The circuit and method selectively isolates the reference voltage from the input/output terminal to which output signals are selectively applied. The isolation occurs responsive to detecting that an output signal is being applied to the input/output terminal so that transitions of the output signal are not coupled through the input receiver to generate noise in the reference voltage. In one embodiment, the isolation is provided by placing an isolation circuit between the input receiver and either the input/output terminal or a source of the reference voltage. In another embodiment, the isolation is provided by selectively biasing the input receiver so that coupling of output signal transitions through the input receiver is substantially reduced.

公开(公告)号：US06944043B2

公开(公告)日：2005-09-13

申请号：US10339041

申请日：2003-01-09

申请人： Craig T. Salling ,  Brian W. Huber

发明人： Craig T. Salling ,  Brian W. Huber

IPC分类号： G11C11/22 ,  H01L21/8246 ,  H01L27/115

CPC分类号： H01L27/11502 ,  G11C11/22 ,  H01L27/11585 ,  H01L27/1159 ,  H01L29/78391

摘要： Depletion-mode ferroelectric transistors are adapted for use as non-volatile memory cells. Various embodiments are described having a diode interposed between the bit line and a source/drain region of the transistor for added margin against read disturb. Various additional embodiments are described having an array architecture such that two memory cells sharing the same bit line also share the same program line. Using this configuration, non-selected cells are readily supplied with gate/source voltages sufficient to maintain the cells in a deactivated state during read and write operations on selected cells.

摘要翻译： 耗尽型铁电晶体管适合用作非易失性存储单元。 描述了具有夹在晶体管的位线和源极/漏极区之间的二极管的各种实施例，用于增加读取干扰的余量。 描述具有阵列架构的各种附加实施例，使得共享相同位线的两个存储器单元也共享相同的程序行。 使用这种配置，非选择的单元容易地被提供有足够的栅极/源极电压，以便在对所选择的单元的读取和写入操作期间将单元维持在去激活状态。