公开(公告)号：US6049483A

公开(公告)日：2000-04-11

申请号：US368453

申请日：1999-08-03

申请人： John F. Schreck ,  David J. McElroy ,  Brian W. Huber

发明人： John F. Schreck ,  David J. McElroy ,  Brian W. Huber

IPC分类号： G11C5/14 ,  G11C16/12 ,  G11C16/14

CPC分类号： G11C16/14 ,  G11C16/12 ,  G11C5/145

摘要： Circuits for applying a programming voltage and erase voltage to memory cells in a nonvolatile memory device are disclosed. The reverse breakdown of p-n junctions within the memory cells is prevented by providing a clamping p-n junction in the path used to apply the program or erase voltage to the memory cells. The clamping p-n junction will breakdown before the p-n junctions within the memory cells, protecting the memory cells from the adverse effects of a reverse breakdown condition.

摘要翻译： 公开了用于向非易失性存储器件中的存储单元施加编程电压和擦除电压的电路。 通过在用于将编程或擦除电压施加到存储器单元的路径中提供钳位p-n结来防止存储器单元内的p-n结的反向击穿。 钳位p-n结将在存储器单元内的p-n结之前击穿，从而保护存储单元不受反向故障条件的不利影响。

公开(公告)号：US5412603A

公开(公告)日：1995-05-02

申请号：US239008

申请日：1994-05-06

申请人： John F. Schreck ,  Cetin Kaya ,  David J. McElroy

发明人： John F. Schreck ,  Cetin Kaya ,  David J. McElroy

IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C7/00

CPC分类号： G11C16/30 ,  G11C16/12 ,  G11C16/16

摘要： The drain-to-source voltage and current for programming a selected nonvolatile memory cell 10 are achieved efficiently by pumping the source 11 of a selected cell 11 to a voltage less than the voltage VSS at the reference-voltage terminal of the memory cell array while, at the same time, pumping the drain 12 of the selected cell 10 to a voltage greater than the voltage VCC, which may be 3 V, at the supply-voltage terminal of the memory cell array. The cell substrate W2 is pumped to a voltage close to the voltage of the source 11 and, optionally, below the voltage of the source 11. One or more simple charge-pump circuits convert the output of the voltage supply VCC to a source-drain voltage and current capable of programming the selected nonvolatile cell 10 by hot carrier injection.

摘要翻译： 通过将所选择的单元11的源极11泵送到小于存储单元阵列的参考电压端子处的电压VSS的电压来有效地实现用于对选定的非易失性存储单元10进行编程的漏极到源极电压和电流，同时 同时，在存储单元阵列的电源电压端将泵浦所选单元10的漏极12的电压大于可以为3V的电压VCC。 电池基板W2被泵浦到接近源极11的电压的电压，并且可选地低于源11的电压。一个或多个简单的电荷泵电路将电压源VCC的输出转换为源极 - 漏极 能够通过热载流子注入对所选择的非易失性电池10进行编程的电压和电流。

公开(公告)号：US5313432A

公开(公告)日：1994-05-17

申请号：US790122

申请日：1991-11-12

申请人： Sung-Wei Lin ,  John F. Schreck ,  Phat C. Truong ,  David J. McElroy ,  Harvey J. Stiegler ,  Benjamin H. Ashmore, Jr. ,  Manzur Gill

发明人： Sung-Wei Lin ,  John F. Schreck ,  Phat C. Truong ,  David J. McElroy ,  Harvey J. Stiegler ,  Benjamin H. Ashmore, Jr. ,  Manzur Gill

IPC分类号： G11C5/02 ,  G11C8/12 ,  G11C16/04 ,  G11C16/08 ,  G11C16/12 ,  G11C16/06

CPC分类号： G11C16/0416 ,  G11C16/08 ,  G11C16/12 ,  G11C5/025 ,  G11C8/12

摘要： A wordline-decode system of a nonvolatile memory array is split into three smaller decoding subsystems (a Read-Mode Decode Subsystem, a Program/Erase-Mode Decode Subsystem and a Segment-Select Decoder Subsystem). The segmented array has small bitline capacitance and requires few input connections to each decoding subsystem. The Read-Mode Decoder circuitry and the Program/Erase-Mode Decoder circuitry are separated, allowing the Read-Mode Decoder circuitry to be desired for high speed access and allowing the Program/Erase-Mode Decoder circuitry to be desired for high voltage operation. Buried-bitline segment-select transistors reduce the area required for those transistors. Erasing may be performed after first checking each row of a segment to determine the present of any over-erased cells. Programming may be performed by allowing the common source-column lines of the selected segment to float and by placing preselected voltages on the appropriate wordline and drain-column line.

摘要翻译： 非易失性存储器阵列的字线解码系统被分成三个较小的解码子系统（读模式解码子系统，程序/擦除模式解码子系统和段选择解码器子系统）。 分段阵列具有小的位线电容，并且需要几个输入连接到每个解码子系统。 读模式解码器电路和编程/擦除模式解码器电路分开，允许读模式解码器电路用于高速访问，并允许对高电压操作进行编程/擦除模式解码器电路。 掩埋位线段选择晶体管减少了那些晶体管所需的面积。 可以在首先检查段的每一行以确定任何过度擦除的单元的存在之后执行擦除。 可以通过允许所选段的公共源列线浮动并且将预选的电压放置在适当的字线和漏极 - 列线上来执行编程。

公开(公告)号：US5313427A

公开(公告)日：1994-05-17

申请号：US763105

申请日：1991-09-20

申请人： John F. Schreck ,  David J. McElroy ,  Pradeep L. Shah

发明人： John F. Schreck ,  David J. McElroy ,  Pradeep L. Shah

IPC分类号： H01L21/8247 ,  G11C16/02 ,  G11C16/16 ,  H01L27/115 ,  G11C16/06 ,  G11C11/34

CPC分类号： G11C16/16

摘要： A nonvolatile memory has pairs of cells in which each cell includes a control gate, a floating gate and a source/drain diffusion. A first cell in each of the pairs is producible to have one value of floating-gate to diffusion capacitance. A second cell in each of the pairs is producible to have a second value of floating-gate to diffusion capacitance different from the first value. The memory includes a first circuit for applying a first erasing pulse to the control gates and the diffusions of the first cells of the pairs and includes a second circuit for applying a second erasing pulse to the control gates and the diffusions of the second cells of the pairs. The first erasing pulse is adjustable to have a different magnitude than the second erasing pulse in order to narrow the margin of erased threshold voltages and thereby compensate for misalignment.

摘要翻译： 非易失性存储器具有成对的单元，其中每个单元包括控制栅极，浮置栅极和源极/漏极扩散。 每对中的第一个单元可以产生一个浮动栅扩散电容的值。 每对中的第二单元可以产生具有不同于第一值的扩散电容的浮置栅极的第二值。 存储器包括用于将第一擦除脉冲施加到控制栅极的第一电路和对的第一单元的扩散，并且包括用于将第二擦除脉冲施加到控制栅极的第二电路和第二电路的扩散 对。 第一擦除脉冲可调整以具有与第二擦除脉冲不同的幅度，以便缩小擦除阈值电压的余量，从而补偿未对准。

公开(公告)号：US5287315A

公开(公告)日：1994-02-15

申请号：US057435

申请日：1993-05-07

申请人： John F. Schreck ,  Debra J. Dolby ,  David J. McElroy ,  Eddie H. Breashears ,  John H. MacPeak

发明人： John F. Schreck ,  Debra J. Dolby ,  David J. McElroy ,  Eddie H. Breashears ,  John H. MacPeak

IPC分类号： G11C16/28 ,  G11C29/00 ,  G11C7/02 ,  G11C11/34

CPC分类号： G11C29/78 ,  G11C16/28

摘要： A structure and method for improving the sense margin of nonvolatile memories is disclosed. An improvement to the sense margin of nonvolatile memories is accomplished by improving the margin both for "ones" at low control gate voltage Vcc and for "zeros" at high control gate voltage Vcc. Improvement in sensing at low control gate voltages Vcc is accomplished by skewing the sense amplifier response characteristics by forming the channel length of the reference memory cell to have a longer channel length than the memory cells of the array.

摘要翻译： 公开了一种用于改善非易失性存储器的检测边缘的结构和方法。 通过改善在低控制栅极电压Vcc下的“一个”和在高控制栅极电压Vcc下的“零”的裕度来实现对非易失性存储器的感测边缘的改进。 在低控制栅极电压Vcc下的感测改善通过使参考存储器单元的沟道长度形成具有比阵列的存储单元更长的沟道长度的方式来使读出放大器响应特性偏斜来实现。

公开(公告)号：US07903488B2

公开(公告)日：2011-03-08

申请号：US12498541

申请日：2009-07-07

申请人： David J. McElroy ,  Stephen L. Casper

发明人： David J. McElroy ,  Stephen L. Casper

IPC分类号： G11C7/00

CPC分类号： G11C11/4091 ,  G11C7/065 ,  G11C7/12 ,  G11C11/4094 ,  G11C2207/005

摘要： Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices couple or decouple bias voltage from corresponding digit lines coupled to the sense amplifiers. By coupling and decoupling voltage from the digit lines, the time interval between refresh operations can be increased.

摘要翻译： 在DRAM器件内提供电压耦合/去耦装置，用于改善读出放大器的偏置感测，从而改善刷新性能。 电压耦合/解耦装置将耦合到读出放大器的相应数字线耦合或去耦偏置电压。 通过从数字线耦合和解耦电压，可以提高刷新操作之间的时间间隔。

公开(公告)号：US06757202B2

公开(公告)日：2004-06-29

申请号：US10233871

申请日：2002-08-29

申请人： David J. McElroy ,  Stephen L. Casper

发明人： David J. McElroy ,  Stephen L. Casper

IPC分类号： G11C1604

CPC分类号： G11C11/4091 ,  G11C7/065 ,  G11C7/12 ,  G11C11/4094 ,  G11C2207/005

摘要： Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices couple or decouple bias voltage from corresponding digit lines coupled to the sense amplifiers. By coupling and decoupling voltage from the digit lines, the time interval between refresh operations can be increased.

摘要翻译： 在DRAM器件内提供电压耦合/去耦装置，用于改善读出放大器的偏置感测，从而改善刷新性能。 电压耦合/解耦装置将耦合到读出放大器的相应数字线耦合或去耦偏置电压。 通过从数字线耦合和解耦电压，可以提高刷新操作之间的时间间隔。

公开(公告)号：US5641701A

公开(公告)日：1997-06-24

申请号：US413291

申请日：1995-03-30

申请人： Hideyuki Fukuhara ,  Yoichi Miyai ,  David J. McElroy

发明人： Hideyuki Fukuhara ,  Yoichi Miyai ,  David J. McElroy

IPC分类号： H01L21/302 ,  H01L21/461 ,  H01L21/768 ,  H01L21/82 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L21/76886 ,  H01L2224/48463

摘要： A method for fabricating a semiconductor device includes the steps of: forming fuses (40) and conductive pads (46) above a semiconductor substrate (43); depositing a layer of cap oxide (44) over the fuses and the conductive pads; sintering the cap oxide; etching back the layer of cap oxide until the top surface of an insulator (42) over the fuses and the top surfaces of the conductive pads are exposed; performing electrical tests (48) by way of the conductive pads; trimming (50) at least a part of the fuses with a laser beam; depositing a silicon nitride layer (52) overall; depositing a mask coating over the silicon nitride; patterning the mask coating (54) to expose the conductive pads; and etching the mask coating and the silicon nitride layer to expose the conductive pads.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：在半导体衬底（43）的上方形成熔丝（40）和导电焊盘（46）; 在保险丝和导电垫上方沉积一层氧化碳（44）; 烧结氧化膜; 蚀刻覆盖氧化物层，直到熔丝上方的绝缘体（42）的顶表面和导电焊盘的顶表面露出; 通过导电垫执行电测试（48）; 用激光束修剪（50）至少一部分保险丝; 整个沉积氮化硅层（52）; 在氮化硅上沉积掩模涂层; 图案化掩模涂层（54）以暴露导电焊盘; 并蚀刻掩模涂层和氮化硅层以暴露导电焊盘。

公开(公告)号：US5523249A

公开(公告)日：1996-06-04

申请号：US364529

申请日：1994-12-23

申请人： Manzur Gill ,  David J. McElroy ,  Sung-Wei Lin ,  Inn K. Lee

发明人： Manzur Gill ,  David J. McElroy ,  Sung-Wei Lin ,  Inn K. Lee

IPC分类号： H01L21/8247

CPC分类号： H01L27/11521

摘要： An electrically-erasable, electrically-programmable, read-only-memory cell array is formed in pairs at a face of a semiconductor substrate (22). Each memory cell includes a source region (11) and a drain region (12), with a corresponding channel region between. A Fowler-Nordheim tunnel-window (13a) is located over the source line (17) connected to source (11). A floating gate (13) includes a tunnel-window section. A control gate (14) is disposed over the floating gate (13), insulated by an intervening inter-level dielectric (27). The floating gate (13) and the control gate (14) include a channel section (Ch). The channel section (Ch) is used as a self-alignment implant mask for the source (11) and drain (12) regions, such that the channel-junction edges are aligned with the corresponding edges of the channel section (Ch). The memory cell is programmed by hot-carrier injection from the channel to the floating gate (13), and erased by Fowler-Nordheim tunneling from the floating gate (13) through the tunnel window (13a) to the source-line (17 ). The program and erase regions of the cells are physically separate from each other, and the characteristics, including the oxides, of each of those regions may be made optimum independently from each other.

摘要翻译： 在半导体衬底（22）的表面上成对地形成电可擦除的电可编程的只读存储单元阵列。 每个存储单元包括源极区域（11）和漏极区域（12），其间具有相应的沟道区域。 福勒 - 诺德海姆隧道窗口（13a）位于连接到源（11）的源极线（17）上。 浮动门（13）包括隧道窗部分。 控制栅极（14）设置在浮置栅极（13）上，由中间层间电介质（27）绝缘。 浮动栅极（13）和控制栅极（14）包括通道部分（Ch）。 通道部分（Ch）用作源（11）和漏极（12）区域的自对准注入掩模，使得沟道结边缘与通道部分（Ch）的相应边缘对齐。 存储单元通过从通道的热载流子注入到浮动栅极（13）进行编程，并由Fowler-Nordheim从浮动栅极（13）通过隧道窗口（13a）到源极线（17）的隧道擦除， 。 单元的程序和擦除区域在物理上彼此分离，并且这些区域中的每一个的特性，包括氧化物可以彼此独立地最优化。

公开(公告)号：US5110753A

公开(公告)日：1992-05-05

申请号：US576887

申请日：1990-09-04

申请人： Manzur Gill ,  David J. McElroy

发明人： Manzur Gill ,  David J. McElroy

IPC分类号： H01L27/115

CPC分类号： H01L27/115

摘要： A contact-free floating-gate non-volatile memory cell array and process with silicided NSAG bitlines and with source/drain regions buried beneath relatively thick silicon oxide. The bitlines have a relatively small resistance, eliminating the need for parallel metallic conductors with numerous bitline contacts. The array has relatively small bitline capacitance and may be constructed having relatively small dimensions. Isolation between wordlines and between bitlines is by thick field oxide. Wordlines may be formed from silicided polycrystalline or other material with low resistivity. Coupling of programming and erasing voltages to the floating gate is improved by extending the gates over the thick field oxide and perhaps by using an insulator with relatively high dielectric constant between the control gate and the floating gate. The resulting structure is a dense cross-point array of progammable memory cells.

摘要翻译： 一个无接触的浮栅非易失性存储单元阵列和具有硅化NSAG位线的工艺，以及埋在相对厚的氧化硅之下的源/漏区。 位线具有相对较小的电阻，消除了对具有大量位线触点的并行金属导体的需要。 阵列具有相对小的位线电容，并且可以构造成具有相对较小的尺寸。 字线之间和位线之间的隔离是通过厚场氧化物。 字线可以由具有低电阻率的硅化多晶或其它材料形成。 通过将栅极扩展到厚场氧化物上并且可能通过在控制栅极和浮置栅极之间使用具有相对高的介电常数的绝缘体来改善编程和擦除电压到浮栅的耦合。 所得到的结构是可程序记忆单元的密集交叉点阵列。