公开(公告)号：US06300658B1

公开(公告)日：2001-10-09

申请号：US09368073

申请日：1999-08-03

申请人： John JianShi Wang ,  Kent Kuohua Chang ,  Hao Fang ,  Lu You

发明人： John JianShi Wang ,  Kent Kuohua Chang ,  Hao Fang ,  Lu You

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L21/76837 ,  H01L27/115

摘要： The present invention provides a method for reducing the gate aspect ratio of a flash memory device. The method includes forming a tunnel oxide layer on a substrate; forming a polysilicon layer on the tunnel oxide layer; forming an insulating layer on the polysilicon layer; forming a control gate layer on the polysilicon layer; etching at least the tunnel oxide layer, the insulating layer, and the control gate layer to form at least two stack structures; forming a plurality of spacers at sides of the at least two stack structures; and filling at least one gap between the at least two stack structures with an oxide, where the control gate layer provides a gate aspect ratio which allows for a maximum step coverage by the oxide. In a preferred embodiment, the method uses nickel silicide instead of the conventional tungsten silicide in the control gate layers of the cells of the device. Nickel silicide has higher conductivity than conventional silicides, thus a thinner layer of nickel silicide may be used without sacrificing performance. Nickel silicide also has a lower barrier height for holes, thus maintaining a low contact resistance. With a thinner nickel silicide layer, the gate aspect ratio of the cells are lowered, allowing for a maximum step coverage by the gap-filling oxide. The reliability of the device is thus improved.

摘要翻译： 本发明提供一种降低闪速存储器件的栅极纵横比的方法。 该方法包括在衬底上形成隧道氧化物层; 在隧道氧化层上形成多晶硅层; 在所述多晶硅层上形成绝缘层; 在所述多晶硅层上形成控制栅极层; 至少蚀刻隧道氧化物层，绝缘层和控制栅极层以形成至少两个堆叠结构; 在所述至少两个堆叠结构的侧面处形成多个间隔物; 以及用所述氧化物填充所述至少两个堆叠结构之间的至少一个间隙，其中所述控制栅极层提供允许所述氧化物的最大阶跃覆盖的栅极纵横比。 在优选实施例中，该方法在装置的电池的控制栅极层中使用硅化镍代替常规的硅化钨。 硅化镍具有比常规硅化物更高的导电性，因此可以使用更薄的硅化镍层而不牺牲性能。 硅化镍也具有较低的孔的阻挡高度，因此保持低的接触电阻。 利用更薄的硅化镍层，电池的栅极纵横比降低，允许通过间隙填充氧化物的最大阶梯覆盖。 因此提高了装置的可靠性。

公开(公告)号：US06410949B1

公开(公告)日：2002-06-25

申请号：US09774327

申请日：2001-01-31

申请人： John JianShi Wang ,  Kent Kuohua Chang ,  Hao Fang

发明人： John JianShi Wang ,  Kent Kuohua Chang ,  Hao Fang

IPC分类号： H01L218242

摘要： The present invention provides a method for monitoring for a second gate over etch in a flash memory device. The method includes providing at least one select transistor stack structure in the core area of the substrate and at least one monitor structure in the monitor area of the substrate; determining a thickness of a select gate layer of the at least one monitor structure; and determining if a second gate over etch occurred upon the thickness of the select gate layer of the at least one monitor structure. The select gate layer of the monitor structure is the same select gate layer of the select transistor stack structure. The select gate thickness of the select transistor stack structure may be determined by measuring the thickness at the monitor structure. This measurement is possible at the monitor area because the monitor structures are placed far enough apart to support measuring instruments. With the method in accordance with the present invention, a second gate over etch and its extent can be monitored without destroying the device. The method requires less time than conventional monitoring methods and is also less costly.

公开(公告)号：US06323047B1

公开(公告)日：2001-11-27

申请号：US09368247

申请日：1999-08-03

申请人： John JianShi Wang ,  Kent Kuohua Chang ,  Hao Fang

发明人： John JianShi Wang ,  Kent Kuohua Chang ,  Hao Fang

IPC分类号： H01L2166

CPC分类号： H01L27/11526 ,  H01L21/32137 ,  H01L22/34 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11531

摘要： The present invention provides a method for monitoring for a second gate over etch in a flash memory device. The method includes providing at least one select transistor stack structure in the core area of the substrate and at least one monitor structure in the monitor area of the substrate; determining a thickness of a select gate layer of the at least one monitor structure; and determining if a second gate over etch occurred upon the thickness of the select gate layer of the at least one monitor structure. The select gate layer of the monitor structure is the same select gate layer of the select transistor stack structure. The select gate thickness of the select transistor stack structure may be determined by measuring the thickness at the monitor structure. This measurement is possible at the monitor area because the monitor structures are placed far enough apart to support measuring instruments. With the method in accordance with the present invention, a second gate over etch and its extent can be monitored without destroying the device. The method requires less time than conventional monitoring methods and is also less costly.

公开(公告)号：US06376309B2

公开(公告)日：2002-04-23

申请号：US09811288

申请日：2001-03-16

申请人： John JianShi Wang ,  Kent Kuohua Chang ,  Hao Fang ,  Lu You

发明人： John JianShi Wang ,  Kent Kuohua Chang ,  Hao Fang ,  Lu You

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L21/76837 ,  H01L27/115

摘要： The present invention provides a method for reducing the gate aspect ratio of a flash memory device. The method includes forming a tunnel oxide layer on a substrate; forming a polysilicon layer on the tunnel oxide layer; forming an insulating layer on the polysilicon layer; forming a control gate layer on the polysilicon layer; etching at least the tunnel oxide layer, the insulating layer, and the control gate layer to form at least two stack structures; forming a plurality of spacers at sides of the at least two stack structures; and filling at least one gap between the at least two stack structures with an oxide, where the control gate layer provides a gate aspect ratio which allows for a maximum step coverage by the oxide. In a preferred embodiment, the method uses nickel silicide instead of the conventional tungsten silicide in the control gate layers of the cells of the device. Nickel silicide has higher conductivity than conventional silicides, thus a thinner layer of nickel silicide may be used without sacrificing performance. Nickel silicide also has a lower barrier height for holes, thus maintaining a low contact resistance. With a thinner nickel silicide layer, the gate aspect ratio of the cells are lowered, allowing for a maximum step coverage by the gap-filling oxide. The reliability of the device is thus improved.

摘要翻译： 本发明提供一种降低闪速存储器件的栅极纵横比的方法。 该方法包括在衬底上形成隧道氧化物层; 在隧道氧化层上形成多晶硅层; 在所述多晶硅层上形成绝缘层; 在所述多晶硅层上形成控制栅极层; 至少蚀刻隧道氧化物层，绝缘层和控制栅极层以形成至少两个堆叠结构; 在所述至少两个堆叠结构的侧面处形成多个间隔物; 以及用所述氧化物填充所述至少两个堆叠结构之间的至少一个间隙，其中所述控制栅极层提供允许所述氧化物的最大阶跃覆盖的栅极纵横比。 在优选实施例中，该方法在装置的电池的控制栅极层中使用硅化镍代替常规的硅化钨。 硅化镍具有比常规硅化物更高的导电性，因此可以使用更薄的硅化镍层而不牺牲性能。 硅化镍也具有较低的孔的阻挡高度，因此保持低的接触电阻。 利用更薄的硅化镍层，电池的栅极纵横比降低，允许通过间隙填充氧化物的最大阶梯覆盖。 因此提高了装置的可靠性。

公开(公告)号：US06362049B1

公开(公告)日：2002-03-26

申请号：US09435213

申请日：1999-11-05

申请人： Salvatore F. Cagnina ,  Hao Fang ,  John Jianshi Wang ,  Kent Kuohua Chang ,  Masaatzi Higashitani

发明人： Salvatore F. Cagnina ,  Hao Fang ,  John Jianshi Wang ,  Kent Kuohua Chang ,  Masaatzi Higashitani

IPC分类号： H01L21336

CPC分类号： H01L27/11526 ,  H01L27/11546

摘要： A semiconductor process for fabricating NAND type flash memory devices in a first embodiment includes step which can be performed on a production line which manufactures NOR type flash memory products. A NAND flash memory fabrication process according to a second embodiment simplifies the process and uses fewer masks, thus reducing costs and errors to produce higher yields.

摘要翻译： 在第一实施例中用于制造NAND型闪速存储器件的半导体工艺包括可以在制造NOR型闪存产品的生产线上执行的步骤。 根据第二实施例的NAND闪存制造工艺简化了处理并且使用较少的掩模，从而降低成本和错误以产生更高的产量。

公开(公告)号：US06235586B1

公开(公告)日：2001-05-22

申请号：US09352801

申请日：1999-07-13

申请人： Kenneth Wo-Wai Au ,  Kent Kuohua Chang ,  Hao Fang

发明人： Kenneth Wo-Wai Au ,  Kent Kuohua Chang ,  Hao Fang

IPC分类号： H01L218247

CPC分类号： H01L27/115 ,  H01L27/11517 ,  H01L27/11521 ,  H01L27/11524

摘要： In one embodiment, the present invention relates to a method of forming a NAND type flash memory device, involving the steps of growing a first oxide layer over at least a portion of a substrate, the substrate including a flash memory cell area and a select gate area; removing a portion of the first oxide layer in the flash memory cell area of the substrate; growing a second oxide layer over at least a portion of the substrate in the flash memory cell area and over at least a portion of the a first oxide layer in the select gate area; depositing a first in situ doped amorphous silicon layer over at least a portion of the second oxide layer, the first in situ doped amorphous silicon layer having a thickness from about 400 Å to about 1,000 Å; depositing a dielectric layer over at least a portion of the first in situ doped amorphous silicon layer; depositing a second doped amorphous silicon layer over at least a portion of the dielectric layer; and forming a flash memory cell in the flash memory cell area of the substrate and a select gate transistor in the select gate area substrate, the flash memory cell comprising the second oxide layer, the first in situ doped amorphous silicon layer, the dielectric layer, and the second doped amorphous silicon layer, and the select gate transistor comprising the first oxide layer, second oxide layer, the first in situ doped amorphous silicon layer, the dielectric layer, and the second doped amorphous silicon layer.

摘要翻译： 在一个实施例中，本发明涉及一种形成NAND型快闪存储器件的方法，包括以下步骤：在衬底的至少一部分上生长第一氧化物层，所述衬底包括闪存单元区域和选择栅极 区; 去除衬底的闪存单元区域中的第一氧化物层的一部分; 在所述闪存单元区域中的所述衬底的至少一部分上以及所述选择栅极区域中的所述第一氧化物层的至少一部分上生长第二氧化物层; 在所述第二氧化物层的至少一部分上沉积第一原位掺杂的非晶硅层，所述第一原位掺杂的非晶硅层具有从约至在的厚度; 在第一原位掺杂的非晶硅层的至少一部分上沉积介电层; 在所述电介质层的至少一部分上沉积第二掺杂非晶硅层; 以及在所述衬底的所述闪存单元区域中形成快闪存储器单元，以及在所述选择栅极区域衬底中形成选择栅极晶体管，所述闪存单元包括所述第二氧化物层，所述第一原位掺杂非晶硅层，所述介电层， 和第二掺杂非晶硅层，选择栅晶体管包括第一氧化物层，第二氧化物层，第一原位掺杂非晶硅层，介电层和第二掺杂非晶硅层。

公开(公告)号：US5994239A

公开(公告)日：1999-11-30

申请号：US993343

申请日：1997-12-18

申请人： Kent Kuohua Chang ,  Hao Fang ,  Ken Au ,  David Chi

发明人： Kent Kuohua Chang ,  Hao Fang ,  Ken Au ,  David Chi

IPC分类号： H01L21/762 ,  H01L21/00

CPC分类号： H01L21/28273 ,  H01L21/76202 ,  H01L27/11521

摘要： Polystringers that cause NAND-type memory core cells to malfunction are removed. A SiON layer, tungsten silicide layer, second polysilicon layer, ONO dielectric, and first polysilicon layer are successively removed from between NAND-type flash memory core cells leaving ONO fence that shields some first polysilicon layer material from removal. Next, the device is exposed to oxygen gas in a high temperature environment to oxidize the surface of the device, and in particular to remove the polystringers.

摘要翻译： 导致NAND型存储器核心单元发生故障的聚束器被去除。 从NAND型闪速存储器核心单元之间连续地去除SiON层，硅化钨层，第二多晶硅层，ONO电介质和第一多晶硅层，留下ONO栅栏，屏蔽了一些第一多晶硅层材料的去除。 接下来，该装置在高温环境中暴露于氧气以氧化装置的表面，并且特别是去除多边形。

公开(公告)号：US06218689B1

公开(公告)日：2001-04-17

申请号：US09369638

申请日：1999-08-06

申请人： Kent Kuohua Chang ,  Kenneth Wo-Wai Au ,  Hao Fang

发明人： Kent Kuohua Chang ,  Kenneth Wo-Wai Au ,  Hao Fang

IPC分类号： H01L2976

CPC分类号： H01L27/11521 ,  H01L27/11524

摘要： The present invention provides a method and a NAND-type flash memory device. The method includes forming a select gate oxide layer in a select transistor area of a substrate and a tunnel oxide layer in a memory cell area of the substrate; forming a doped amorphous silicon layer on the select gate oxide layer and the tunnel oxide layer, the doped amorphous silicon layer having a dopant level which simultaneously avoids a select transistor word line high resistance problem and a charge gain/charge loss problem; forming an insulating layer on the doped amorphous silicon layer; forming a control gate layer on the insulating layer; and etching at least the doped amorphous silicon layer, the insulating layer, and the control gate layer to form at least one memory cell stack structure and at least one select transistor stack structure. In a preferred embodiment, the polysilicon layer which forms both the floating gate of the flash memory cell and the select gate of the select transistor of the device is doped with between approximately 5×1018 and 8×1019 ions/cm3 of phosphorus. With this dopant level, the contact resistance of the select transistor's control gate is low, thus keeping the word line resistivity of the device low. Simultaneously, contamination of the tunnel oxide of the flash memory cell by the dopant is limited, allowing for the interface between the floating gate and the tunnel oxide to be smooth, which prevents charge gain/loss problems. Thus, the reliability of the device is increased.

摘要翻译： 本发明提供了一种方法和NAND型闪速存储器件。 该方法包括在衬底的选择晶体管区域和衬底的存储单元区域中形成选择栅极氧化物层和隧道氧化物层; 在选择栅极氧化物层和隧道氧化物层上形成掺杂非晶硅层，掺杂非晶硅层具有同时避免选择晶体管字线高电阻问题和电荷增益/电荷损失问题的掺杂剂水平; 在所述掺杂非晶硅层上形成绝缘层; 在所述绝缘层上形成控制栅极层; 以及至少蚀刻所述掺杂的非晶硅层，所述绝缘层和所述控制栅极层，以形成至少一个存储单元堆叠结构和至少一个选择晶体管堆叠结构。 在优选实施例中，形成闪存单元的浮动栅极和器件的选择晶体管的选择栅极的多晶硅层掺杂有大约5×1018和8×1019离子/ cm3的磷。 利用该掺杂剂水平，选择晶体管的控制栅极的接触电阻低，从而保持器件的字线电阻率低。 同时，掺杂剂对闪存单元的隧道氧化物的污染是有限的，允许浮置栅极和隧道氧化物之间的界面平滑，这防止了电荷增益/损耗问题。 因此，装置的可靠性增加。

公开(公告)号：US06072191A

公开(公告)日：2000-06-06

申请号：US991299

申请日：1997-12-16

申请人： Tho Le La ,  John Jianshi Wang ,  Hao Fang

发明人： Tho Le La ,  John Jianshi Wang ,  Hao Fang

IPC分类号： H01L21/66 ,  H01L21/768 ,  H01L23/544 ,  H01L23/58 ,  H01L21/4763

CPC分类号： H01L22/34 ,  H01L21/76801 ,  H01L22/12

摘要： A method of measuring the thickness of a dielectric layer above a plurality of structures of differing types within a semiconductor chip. The method comprises the steps of: forming a plurality of monitor boxes on a semiconductor chip such that each of said plurality of monitor boxes represents a structure type within the semiconductor chip and has substantially the same step height as one of a plurality of differing structure types; forming a dielectric layer over the semiconductor chip; and measuring a thickness of the dielectric layer above at least one of the plurality of monitor boxes, wherein said thickness represents a thickness of the dielectric layer above a structure of the structure type represented by the monitor box.Also disclosed is a semiconductor chip that allows for accurate dielectric thickness measurements. The chip comprises: a plurality of structures of differing types located on a surface within the semiconductor chip; and a plurality of monitor boxes, located on said surface within the semiconductor chip, upon which measurements of dielectric thickness can be made, wherein each of the plurality of monitor boxes represents a structure type within the semiconductor chip.

摘要翻译： 一种在半导体芯片内测量不同类型的多个结构之上的电介质层的厚度的方法。 该方法包括以下步骤：在半导体芯片上形成多个监视盒，使得所述多个监视盒中的每一个表示半导体芯片内的结构类型，并具有与多种不同结构类型之一基本相同的台阶高度 ; 在所述半导体芯片上形成介电层; 以及测量所述多个监视盒中的至少一个上的所述电介质层的厚度，其中所述厚度表示所述电介质层的厚度，所述电介质层在由所述监视盒所表示的结构类型的结构之上。 还公开了允许精确的电介质厚度测量的半导体芯片。 芯片包括：位于半导体芯片内的表面上的不同类型的多个结构; 以及位于半导体芯片内的所述表面上的多个监视器盒，可以在其上进行介电厚度的测量，其中多个监视盒中的每一个表示半导体芯片内的结构类型。

公开(公告)号：US5994780A

公开(公告)日：1999-11-30

申请号：US991052

申请日：1997-12-16

申请人： John Jianshi Wang ,  Hao Fang

发明人： John Jianshi Wang ,  Hao Fang

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76816 ,  H01L23/5226 ,  H01L2924/0002 ,  Y10S438/911

摘要： A semiconductor device having multiple layers uses different size contacts at different layer in order in order to simplify the manufacturing process and the depth of etching required. Contact sizes are selected based on the responsiveness of the material to the etching process. Where a deep etch is required, a larger contact is used. A shallower etch through similar material uses a smaller contact to slow the etching process. As a result, the etches can complete at about the same time. The technique can be employed to etch any number of contacts. An intermediate size contact can be used where the material to be etched results in a slower etching process. A plurality of contact sizes can be used depending on the depths of etching required and the characteristics of material to be etched, so that the etching for all the contacts completes at substantially the same time.

摘要翻译： 具有多个层的半导体器件按顺序在不同层上使用不同尺寸的触点，以简化制造工艺和所需的蚀刻深度。 触点尺寸是根据材料对蚀刻工艺的响应性来选择的。 在需要深刻蚀时，使用较大的接触。 通过类似材料的较浅蚀刻使用更小的接触来减缓蚀刻工艺。 因此，蚀刻可以在大约相同的时间完成。 该技术可用于蚀刻任何数量的触点。 可以使用中等尺寸的接触件，其中待蚀刻的材料导致较慢的蚀刻工艺。 可以根据所需的蚀刻深度和要蚀刻的材料的特性来使用多个接触尺寸，使得所有触点的蚀刻基本上同时完成。