公开(公告)号：US06362049B1

公开(公告)日：2002-03-26

申请号：US09435213

申请日：1999-11-05

申请人： Salvatore F. Cagnina ,  Hao Fang ,  John Jianshi Wang ,  Kent Kuohua Chang ,  Masaatzi Higashitani

发明人： Salvatore F. Cagnina ,  Hao Fang ,  John Jianshi Wang ,  Kent Kuohua Chang ,  Masaatzi Higashitani

IPC分类号： H01L21336

CPC分类号： H01L27/11526 ,  H01L27/11546

摘要： A semiconductor process for fabricating NAND type flash memory devices in a first embodiment includes step which can be performed on a production line which manufactures NOR type flash memory products. A NAND flash memory fabrication process according to a second embodiment simplifies the process and uses fewer masks, thus reducing costs and errors to produce higher yields.

摘要翻译： 在第一实施例中用于制造NAND型闪速存储器件的半导体工艺包括可以在制造NOR型闪存产品的生产线上执行的步骤。 根据第二实施例的NAND闪存制造工艺简化了处理并且使用较少的掩模，从而降低成本和错误以产生更高的产量。

公开(公告)号：US06355522B1

公开(公告)日：2002-03-12

申请号：US09263699

申请日：1999-03-05

申请人： Kent Kuohua Chang ,  John Jianshi Wang ,  Yuesong He

发明人： Kent Kuohua Chang ,  John Jianshi Wang ,  Yuesong He

IPC分类号： H01L21336

CPC分类号： H01L21/28273 ,  H01L29/42324

摘要： In one embodiment, the present invention relates to a method of forming a flash memory cell, involving the steps of forming a tunnel oxide on a substrate; forming a first polysilicon layer over the tunnel oxide by chemical vapor deposition using a silicon containing gas and a mixture of a phosphorus containing gas and a carrier gas, the first polysilicon layer having a thickness from about 800 Å to about 1,000 Å; forming an insulating layer over the first polysilicon layer, the insulating layer comprising a first oxide layer over the first polysilicon layer, a nitride layer over the first oxide layer, and a second oxide layer over the nitride layer; forming a second polysilicon layer over the insulating layer; forming a tungsten silicide layer over the second polysilicon layer by chemical vapor deposition using WF6 and SiH2Cl2; etching at least the first polysilicon layer, the second polysilicon layer, the insulating layer, and the tungsten silicide layer thereby defining at least one stacked gate structure; and forming a source region and a drain region in the substrate, thereby forming at least one memory cell.

摘要翻译： 在一个实施例中，本发明涉及一种形成闪速存储器单元的方法，包括在衬底上形成隧道氧化物的步骤; 通过使用含硅气体和含磷气体和载气的混合物通过化学气相沉积在隧道氧化物上形成第一多晶硅层，第一多晶硅层具有约800至约的厚度; 在所述第一多晶硅层上形成绝缘层，所述绝缘层包括所述第一多晶硅层上的第一氧化物层，所述第一氧化物层上的氮化物层和所述氮化物层上的第二氧化物层; 在所述绝缘层上形成第二多晶硅层; 通过使用WF 6和SiH 2 Cl 2的化学气相沉积在第二多晶硅层上形成硅化钨层; 至少蚀刻第一多晶硅层，第二多晶硅层，绝缘层和硅化钨层，从而限定至少一个堆叠栅极结构; 以及在衬底中形成源区和漏区，由此形成至少一个存储单元。

公开(公告)号：US06281078B1

公开(公告)日：2001-08-28

申请号：US08993344

申请日：1997-12-18

申请人： Kent Kuohua Chang ,  Yuesong He ,  John Jianshi Wang ,  Ken Au

发明人： Kent Kuohua Chang ,  Yuesong He ,  John Jianshi Wang ,  Ken Au

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115

摘要： Polystringers that cause NAND-type memory core cells to malfunction are covered by ONO fence material. ONO fence is removed so that polystringers may then be removed more readily. A SiON layer, tungsten silicide layer, second polysilicon layer, ONO dielectric, and first polysilicon layer are successively removed from between NAND-type flash memory core cells leaving ONO fence that shields some first polysilicon layer material from removal. The device is next exposed to an hydrogen-fluoride solution to remove oxide-based materials, particularly ONO fence. Thereafter, the polystringers are exposed and may thus be removed more readily.

摘要翻译： 导致NAND型存储器核心单元故障的Polystringers被ONO栅栏材料覆盖。 ONO围栏被移除，从而可以更容易地去除多边形。 从NAND型闪速存储器核心单元之间连续地去除SiON层，硅化钨层，第二多晶硅层，ONO电介质和第一多晶硅层，留下ONO栅栏，屏蔽了一些第一多晶硅层材料的去除。 然后将该装置暴露于氟化氢溶液以除去氧化物基材料，特别是ONO栅栏。 此后，暴露多股线，因此可以更容易地被去除。

公开(公告)号：US06180454B2

公开(公告)日：2001-01-30

申请号：US09430765

申请日：1999-10-29

申请人： Kent Kuohua Chang ,  John Jianshi Wang ,  Wei-Wen Ou

发明人： Kent Kuohua Chang ,  John Jianshi Wang ,  Wei-Wen Ou

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524

摘要： In one embodiment, the present invention relates to a method of forming a flash memory device involving the steps of forming a gate oxide layer on a substrate; forming a first poly layer over the gate oxide layer; forming an insulating layer over the first poly layer, the insulating layer comprising a first oxide layer over the first poly layer, a nitride layer over the first oxide layer, and a second oxide layer over the nitride layer; forming a second poly layer over the insulating layer; forming a tungsten silicide layer over the second poly layer; etching a portion of the tungsten silicide layer and the second poly layer, wherein in the etched portion at least about 20% of the second poly is not etched, thereby partially defining at least one stacked gate structure; etching at least a portion of the insulating layer and the unetched portion of the second poly layer thereby defining at least one select gate transistor structure; forming an interlayer dielectric layer over the select gate transistor structure and substrate; etching a contact hole through the interlayer dielectric layer to the first poly layer; and filling the contact hole with a conductive material to thereby form a flash memory device.

摘要翻译： 在一个实施例中，本发明涉及一种形成闪存器件的方法，该器件包括以下步骤：在衬底上形成栅氧化层; 在所述栅极氧化物层上形成第一多晶硅层; 在所述第一多晶硅层上形成绝缘层，所述绝缘层包括所述第一多晶硅层上的第一氧化物层，所述第一氧化物层上的氮化物层和所述氮化物层上的第二氧化物层; 在所述绝缘层上形成第二多晶硅层; 在所述第二多晶硅层上形成硅化钨层; 蚀刻所述硅化钨层和所述第二多晶硅层的一部分，其中在所述蚀刻部分中，所述第二聚硅的至少约20％未被蚀刻，从而部分地限定至少一个堆叠栅极结构; 蚀刻绝缘层的至少一部分和第二多晶硅层的未蚀刻部分，从而限定至少一个选择栅极晶体管结构; 在选择栅极晶体管结构和衬底上形成层间电介质层; 将穿过所述层间介质层的接触孔蚀刻到所述第一多晶硅层; 并用导电材料填充接触孔，从而形成闪存装置。

公开(公告)号：US06140246A

公开(公告)日：2000-10-31

申请号：US993444

申请日：1997-12-18

申请人： Kent Kuohua Chang ,  Ken Au ,  John Jianshi Wang

发明人： Kent Kuohua Chang ,  Ken Au ,  John Jianshi Wang

IPC分类号： H01L21/20 ,  H01L21/205 ,  H01L21/28 ,  H01L21/306 ,  H01L21/314 ,  H01L21/316 ,  H01L21/302

CPC分类号： H01L21/02126 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02326 ,  H01L21/02337 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02491 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/3144 ,  H01L21/31608 ,  H01L21/3167

摘要： A polysilicon-based floating gate is formed so as to be resistant to oxidation that occurs during multiple thermo-cycles in fabrication. Accordingly, edge erase times in NOR-type memory devices may be minimized. Additionally, manufacture of oxidation resistant floating gates reduces variations in edge erase times among multiple NOR-type memory devices. A layer of amorphous silicon is deposited on a silicon substrate by directing silane, a phosphene and helium gas mixture, and ammonia at the surface of the silicon substrate thereby doping the amorphous silicon in situ. The amorphous silicon layer is then etched so as to overlap slightly with regions that will later correspond to the source and drain regions. Next, a lower oxide layer of an ONO dielectric is deposited and the device is heated. A thermo-cycle is eliminated by heating the amorphous silicon during formation of the oxide layer rather than immediately following its deposition. Later, the nitride and oxide layers of the ONO dielectric, a second polysilicon layer, a tungsten silicide layer, and SiON layers are successively formed.

摘要翻译： 形成基于多晶硅的浮栅，以便在制造中的多个热循环期间耐氧化。 因此，NOR型存储器件中的边沿擦除时间可以最小化。 此外，抗氧化浮动栅极的制造减少了多个NOR型存储器件之间的边缘擦除时间的变化。 通过在硅衬底的表面处引导硅烷，磷化氢和氦气混合物以及氨来沉积在硅衬底上的非晶硅层，从而原位掺杂非晶硅。 然后蚀刻非晶硅层，以便稍后与稍后对应于源极和漏极区的区域重叠。 接下来，沉积ONO电介质的低氧化物层，并加热该器件。 通过在形成氧化物层期间加热非晶硅而不是在其沉积之后立即消除热循环。 随后，依次形成ONO电介质，第二多晶硅层，硅化钨层和SiON层的氮化物层和氧化物层。

公开(公告)号：US6063668A

公开(公告)日：2000-05-16

申请号：US993446

申请日：1997-12-18

申请人： Yuesong He ,  Kent Kuohua Chang ,  John Jianshi Wang

发明人： Yuesong He ,  Kent Kuohua Chang ,  John Jianshi Wang

IPC分类号： H01L21/311 ,  H01L21/8247

CPC分类号： H01L27/11517 ,  H01L21/31116

摘要： A layer of polysilicon is deposited over an oxide layer on top of a silicon substrate, with core field oxide and active regions, and patterned. An oxide mask is then added. Next, the oxide mask and the layer of polysilicon are removed from above the core field oxide regions. Next, a second layer of polysilicon is deposited and etched to form polysilicon spacers. Later, an ONO dielectric, a third polysilicon layer, a tungsten silicide layer, and SiON layers are successively formed and patterned. The polysilicon spacers effectively seal any recesses that may occur in the edges of the first polysilicon layer to prevent harboring of subsequently added polysilicon material. Accordingly, NAND-type flash memory core cells cannot be electrically shorted by polysilicon material, so called "polystringers", present in such recesses.

摘要翻译： 在硅衬底顶部的氧化物层上沉积多晶硅层，其中具有核心场氧化物和有源区域并且被图案化。 然后加入氧化物掩模。 接下来，从核心场氧化物区域的上方去除氧化物掩模和多晶硅层。 接下来，沉积和蚀刻第二层多晶硅以形成多晶硅间隔物。 随后，依次形成和图案化ONO电介质，第三多晶硅层，硅化钨层和SiON层。 多晶硅间隔物有效地密封可能在第一多晶硅层的边缘中发生的任何凹陷，以防止随后添加的多晶硅材料。 因此，NAND型闪速存储器核心单元不能被存在于这种凹槽中的多晶硅材料（即所谓的“超弦波”）电短路。

公开(公告)号：US06380029B1

公开(公告)日：2002-04-30

申请号：US09205899

申请日：1998-12-04

申请人： Kent Kuohua Chang ,  Kenneth Wo-Wai Au ,  John Jianshi Wang

发明人： Kent Kuohua Chang ,  Kenneth Wo-Wai Au ,  John Jianshi Wang

IPC分类号： H01L21330

CPC分类号： H01L29/42324 ,  H01L21/28273

摘要： In one embodiment, the present invention relates to a method of forming a flash memory cell, involving the steps of forming a tunnel oxide on a substrate; forming a first polysilicon layer over the tunnel oxide; forming an insulating layer over the first polysilicon layer, the insulating layer comprising a first oxide layer over the first polysilicon layer, a nitride layer over the first oxide layer, and a second oxide layer over the nitride layer; forming a second polysilicon layer over the insulating layer; forming a tungsten silicide layer over the second polysilicon layer by chemical vapor deposition using WF6 and SiH2Cl2; etching at least the first polysilicon layer, the second polysilicon layer, the insulating layer, and the tungsten silicide layer thereby defining at least one stacked gate structure; and forming a source region and a drain region in the substrate, thereby forming at least one memory cell.

摘要翻译： 在一个实施例中，本发明涉及一种形成闪速存储器单元的方法，包括在衬底上形成隧道氧化物的步骤; 在隧道氧化物上形成第一多晶硅层; 在所述第一多晶硅层上形成绝缘层，所述绝缘层包括所述第一多晶硅层上的第一氧化物层，所述第一氧化物层上的氮化物层和所述氮化物层上的第二氧化物层; 在所述绝缘层上形成第二多晶硅层; 通过使用WF 6和SiH 2 Cl 2的化学气相沉积在第二多晶硅层上形成硅化钨层; 至少蚀刻第一多晶硅层，第二多晶硅层，绝缘层和硅化钨层，从而限定至少一个堆叠栅极结构; 以及在衬底中形成源区和漏区，由此形成至少一个存储单元。

公开(公告)号：US06177312B1

公开(公告)日：2001-01-23

申请号：US09048459

申请日：1998-03-26

申请人： Yuesong He ,  John Jianshi Wang ,  Toru Ishigaki ,  Kent Kuohua Chang ,  Effiong Ibok

发明人： Yuesong He ,  John Jianshi Wang ,  Toru Ishigaki ,  Kent Kuohua Chang ,  Effiong Ibok

IPC分类号： H01L2128

CPC分类号： H01L21/28211 ,  H01L21/31116 ,  H01L21/3185 ,  H01L27/11526 ,  H01L27/11534 ,  H01L27/11536 ,  Y10S438/974

摘要： This invention relates to a method for removing contaminate nitrogen from the peripheral gate region of a non-volatile memory device during production of said device, wherein at least some of the contaminate nitrogen has formed a bond with the surface of the silicon substrate in contact with the gate oxide layer in said gate region, said method comprising: contacting said gate oxide layer and contaminate nitrogen with a gas comprising ozone at a temperature of about 850° C. to about 950° C. for an effective period of time to break said bond; and removing said gate oxide layer and contaminate nitrogen from said surface of said silicon substrate.

摘要翻译： 本发明涉及一种在制造所述装置期间从非易失性存储装置的外围栅极区域去除污染氮的方法，其中至少一些污染氮已经与硅衬底的表面形成了接触， 所述栅极区域中的栅极氧化物层，所述方法包括：使接触所述栅极氧化物层并且在约850℃至约950℃的温度下将含有包含臭氧的气体氮气与有毒时间隔离以破坏所述 键; 以及去除所述栅极氧化物层并从所述硅衬底的所述表面污染氮。

公开(公告)号：US06312991B1

公开(公告)日：2001-11-06

申请号：US09531582

申请日：2000-03-21

申请人： John Jianshi Wang ,  Hao Fang ,  Masaaki Higashitani

发明人： John Jianshi Wang ,  Hao Fang ,  Masaaki Higashitani

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524

摘要： A method (200) of forming a NAND type flash memory device includes the steps of forming an oxide layer (202) over a substrate (102) and forming a first conductive layer (106) over the oxide layer. The first conductive layer (106) is etched to form a gate structure (107) in a select gate transistor region (105) and a floating gate structure (106a, 106b) in a memory cell region (111). A first insulating layer (110) is then formed over the memory cell region (111) and a second conductive layer (112, 118) is formed over the first insulating layer (110). A word line (122) is patterned in the memory cell region (111) to form a control gate region and source and drain regions (130, 132) are formed in the in the substrate (102) in a region adjacent the word line (122) and in a region adjacent the gate structure (107). A second insulating layer (140) is formed over both the select gate transistor region (105) and the memory cell region (111) and first and second contact openings are formed in the second insulating layer (140) down to the gate structure (107) and the control gate region, wherein a depth (X) through the second insulating layer (140) down to the gate structure (107) and down to the control gate region are approximately the same, thereby eliminating a substantial overetch of the gate structure contact opening.

摘要翻译： 形成NAND型快闪存储器件的方法（200）包括以下步骤：在衬底（102）上形成氧化物层（202），并在氧化物层上形成第一导电层（106）。 蚀刻第一导电层（106）以在存储单元区域（111）中的选择栅极晶体管区域（105）和浮动栅极结构（106a，106b）中形成栅极结构（107）。 然后在存储单元区域（111）之上形成第一绝缘层（110），并且在第一绝缘层（110）之上形成第二导电层（112,118）。 在存储单元区域（111）中对字线（122）进行构图以形成控制栅极区域，并且在邻近字线的区域（102,132）中形成在衬底（102）中的源极和漏极区域（130,132） 122）并且在与栅极结构（107）相邻的区域中。 在选择栅极晶体管区域（105）和存储单元区域（111）上形成第二绝缘层（140），并且在第二绝缘层（140）中形成第一和第二接触开口至栅极结构（107） ）和控制栅极区域，其中通过第二绝缘层（140）到达栅极结构（107）并且向下到控制栅极区域的深度（X）大致相同，从而消除了栅极结构的实质上的过蚀刻 接触开口

公开(公告)号：US06211058B1

公开(公告)日：2001-04-03

申请号：US09353781

申请日：1999-07-15

申请人： John Jianshi Wang ,  Hao Fang

发明人： John Jianshi Wang ,  Hao Fang

IPC分类号： H01L214763

CPC分类号： H01L21/76816 ,  H01L23/5226 ,  H01L2924/0002 ,  Y10S438/911 ,  H01L2924/00

摘要： A semiconductor device having multiple layers uses different size contacts at different layer in order in order to simply the manufacturing process and the depth of etching required. Contact sizes are selected based on the responsiveness of the material to the etching process. Where a deep etch is required, a larger contact is used. A shallower etch through similar material uses a smaller contact to slow the etching process. As a result, the etches can complete at about the same time. The technique can be employed to etch any number of contacts. An intermediate size contact can be used where the material to be etched results in a slower etching process. A plurality of contact sizes can be used depending on the depths of etching required and the characteristics material to be etched, so that the etching for all the contacts completes at substantially the same time.

摘要翻译： 具有多层的半导体器件按顺序在不同的层上使用不同尺寸的触点，以便简单地制造工艺和所需的蚀刻深度。 触点尺寸是根据材料对蚀刻工艺的响应性来选择的。 在需要深刻蚀时，使用较大的接触。 通过类似材料的较浅蚀刻使用更小的接触来减缓蚀刻工艺。 因此，蚀刻可以在大约相同的时间完成。 该技术可用于蚀刻任何数量的触点。 可以使用中等尺寸的接触件，其中待蚀刻的材料导致较慢的蚀刻工艺。 可以根据所需的蚀刻深度和要蚀刻的特征材料使用多个接触尺寸，使得所有触点的蚀刻基本上同时完成。