公开(公告)号：US5994239A

公开(公告)日：1999-11-30

申请号：US993343

申请日：1997-12-18

申请人： Kent Kuohua Chang ,  Hao Fang ,  Ken Au ,  David Chi

发明人： Kent Kuohua Chang ,  Hao Fang ,  Ken Au ,  David Chi

IPC分类号： H01L21/762 ,  H01L21/00

CPC分类号： H01L21/28273 ,  H01L21/76202 ,  H01L27/11521

摘要： Polystringers that cause NAND-type memory core cells to malfunction are removed. A SiON layer, tungsten silicide layer, second polysilicon layer, ONO dielectric, and first polysilicon layer are successively removed from between NAND-type flash memory core cells leaving ONO fence that shields some first polysilicon layer material from removal. Next, the device is exposed to oxygen gas in a high temperature environment to oxidize the surface of the device, and in particular to remove the polystringers.

摘要翻译： 导致NAND型存储器核心单元发生故障的聚束器被去除。 从NAND型闪速存储器核心单元之间连续地去除SiON层，硅化钨层，第二多晶硅层，ONO电介质和第一多晶硅层，留下ONO栅栏，屏蔽了一些第一多晶硅层材料的去除。 接下来，该装置在高温环境中暴露于氧气以氧化装置的表面，并且特别是去除多边形。

公开(公告)号：US6162684A

公开(公告)日：2000-12-19

申请号：US266714

申请日：1999-03-11

申请人： Kent Kuohua Chang ,  David Chi ,  Chin-Yang Sun

发明人： Kent Kuohua Chang ,  David Chi ,  Chin-Yang Sun

IPC分类号： H01L21/28 ,  H01L21/314 ,  H01L29/51 ,  H01L21/336

CPC分类号： H01L21/28202 ,  H01L21/28211 ,  H01L21/28273 ,  H01L21/3144 ,  H01L29/511 ,  H01L29/518

摘要： In one embodiment, the present invention relates to a method of forming a flash memory cell, involving the steps of forming a tunnel oxide on a substrate; forming a first polysilicon layer over the tunnel oxide; forming an insulating layer over the first polysilicon layer, the insulating layer comprising an oxide layer made by low pressure chemical vapor deposition at a temperature from about 600.degree. C. to about 850.degree. C. using SiH.sub.4 and N.sub.2 O, annealing in an NH.sub.3 atmosphere at a temperature from about 800.degree. C. to about 900.degree. C., and wet oxidizing using O.sub.2 and H.sub.2 at a temperature from about 820.degree. C. to about 880.degree. C.; forming a second polysilicon layer over the insulating layer; etching at least the first polysilicon layer, the second polysilicon layer and the insulating layer, thereby defining at least one stacked gate structure; and forming a source region and a drain region in the substrate, thereby forming at least one memory cell.

摘要翻译： 在一个实施例中，本发明涉及一种形成闪速存储器单元的方法，包括在衬底上形成隧道氧化物的步骤; 在隧道氧化物上形成第一多晶硅层; 在所述第一多晶硅层上形成绝缘层，所述绝缘层包括通过使用SiH 4和N 2 O在约600℃至约850℃的温度下由低压化学气相沉积制成的氧化物层，在NH 3气氛中退火 温度为约800℃至约900℃，并在约820℃至约880℃的温度下使用O 2和H 2进行湿氧化。 在所述绝缘层上形成第二多晶硅层; 至少蚀刻第一多晶硅层，第二多晶硅层和绝缘层，从而限定至少一个堆叠栅极结构; 以及在衬底中形成源区和漏区，由此形成至少一个存储单元。

公开(公告)号：US6114230A

公开(公告)日：2000-09-05

申请号：US993443

申请日：1997-12-18

申请人： Kent Kuohua Chang ,  Yuesong He ,  David Chi

发明人： Kent Kuohua Chang ,  Yuesong He ,  David Chi

IPC分类号： H01L21/28 ,  H01L29/423 ,  H01L29/51 ,  H01L21/3205 ,  H01L21/44

CPC分类号： H01L21/28273 ,  H01L29/42324 ,  H01L29/511

摘要： A polysilicon-based floating gate is formed so as to be resistant to oxidation that occurs during multiple thermo-cycles in fabrication. Accordingly, edge erase times in NOR-type memory devices may be minimized. Additionally, manufacture of oxidation resistant floating gates reduces variations in edge erase times among multiple NOR-type memory devices. A layer of amorphous silicon is deposited over a silicon substrate by directing a mixture of silane and a phosphene-helium gas mixture at the surface of the silicon substrate. Later, N+ ions are implanted into the amorphous silicon. The amorphous silicon layer is then etched so as to overlap slightly with regions that will later correspond to the source and drain regions. Next, a lower oxide layer of an ONO dielectric is deposited and the device is heated. A thermo-cycle is eliminated by heating the amorphous silicon during formation of the oxide layer rather than immediately following its deposition. Later, the nitride and oxide layers of the ONO dielectric, a second polysilicon layer, a tungsten silicide layer, and SiON layers are successively formed.

摘要翻译： 形成基于多晶硅的浮栅，以便在制造中的多个热循环期间耐氧化。 因此，NOR型存储器件中的边沿擦除时间可以最小化。 此外，抗氧化浮动栅极的制造减少了多个NOR型存储器件之间的边缘擦除时间的变化。 通过在硅衬底的表面处引导硅烷和磷 - 氦气混合物的混合物，在硅衬底上沉积非晶硅层。 之后，将N +离子注入到非晶硅中。 然后蚀刻非晶硅层，以便稍后与稍后对应于源极和漏极区的区域重叠。 接下来，沉积ONO电介质的低氧化物层，并加热该器件。 通过在形成氧化物层期间加热非晶硅而不是在其沉积之后立即消除热循环。 随后，依次形成ONO电介质，第二多晶硅层，硅化钨层和SiON层的氮化物层和氧化物层。

公开(公告)号：US6074917A

公开(公告)日：2000-06-13

申请号：US189227

申请日：1998-11-11

申请人： Kent Kuohua Chang ,  David Chi ,  Chin-Yang Sun

发明人： Kent Kuohua Chang ,  David Chi ,  Chin-Yang Sun

IPC分类号： H01L21/28 ,  H01L21/314 ,  H01L29/423 ,  H01L29/51 ,  H01L21/336 ,  H01L21/31

CPC分类号： H01L21/28273 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/3145 ,  H01L29/42324 ,  H01L29/511 ,  H01L29/518 ,  Y10S438/954

摘要： In one embodiment, the present invention relates to a method of forming a flash memory cell, involving the steps of forming a tunnel oxide on a substrate; forming a first polysilicon layer over the tunnel oxide; forming an insulating layer over the first polysilicon layer, the insulating layer comprising a first oxide layer over the first polysilicon layer, a nitride layer over the first oxide layer, and a second oxide layer over the nitride layer, wherein the second oxide layer is made by forming the second oxide layer by low pressure chemical vapor deposition at a temperature from about 600.degree. C. to about 850.degree. C. using SiH.sub.4 and N.sub.2 O and annealing in an N.sub.2 O atmosphere at a temperature from about 700.degree. C. to about 950.degree. C.; forming a second polysilicon layer over the insulating layer; etching at least the first polysilicon layer, the second polysilicon layer and the insulating layer, thereby defining at least one stacked gate structure; and forming a source region and a drain region in the substrate, thereby forming at least one memory cell.

摘要翻译： 在一个实施例中，本发明涉及一种形成闪速存储器单元的方法，包括在衬底上形成隧道氧化物的步骤; 在隧道氧化物上形成第一多晶硅层; 在所述第一多晶硅层上形成绝缘层，所述绝缘层包括所述第一多晶硅层上的第一氧化物层，所述第一氧化物层上的氮化物层和所述氮化物层上的第二氧化物层，其中所述第二氧化物层被制成 通过使用SiH 4和N 2 O在约600℃至约850℃的温度下通过低压化学气相沉积形成第二氧化物层，并在N2O气氛中在约700℃至约950℃的温度下退火 C。; 在所述绝缘层上形成第二多晶硅层; 至少蚀刻第一多晶硅层，第二多晶硅层和绝缘层，从而限定至少一个堆叠栅极结构; 以及在衬底中形成源区和漏区，由此形成至少一个存储单元。

公开(公告)号：US06309927B1

公开(公告)日：2001-10-30

申请号：US09263983

申请日：1999-03-05

申请人： Kenneth Wo-Wai Au ,  Kent Kuohua Chang ,  David Chi

发明人： Kenneth Wo-Wai Au ,  Kent Kuohua Chang ,  David Chi

IPC分类号： H01L218247

CPC分类号： H01L21/28273

摘要： In one embodiment, the present invention relates to a method of forming a flash memory cell, involving the steps of forming a tunnel oxide on a substrate; forming a first polysilicon layer over the tunnel oxide; forming an insulating layer over the first polysilicon layer, the insulating layer comprising an oxide layer over the first polysilicon layer, and a tantalum pentoxide layer over the oxide layer, wherein the tantalum pentoxide layer is made by chemical vapor deposition at a temperature from about 200° C. to about 650° C. using an organic tantalum compound and an oxygen compound, and heating in an N2O atmosphere at a temperature from about 700° C. to about 875° C.; forming a second polysilicon layer over the insulating layer; etching at least the first polysilicon layer, the second polysilicon layer and the insulating layer, thereby defining at least one stacked gate structure; and forming a source region and a drain region in the substrate, thereby forming at least one memory cell.

摘要翻译： 在一个实施例中，本发明涉及一种形成闪速存储器单元的方法，包括在衬底上形成隧道氧化物的步骤; 在隧道氧化物上形成第一多晶硅层; 在所述第一多晶硅层上形成绝缘层，所述绝缘层包括在所述第一多晶硅层上的氧化物层和在所述氧化物层上的五氧化二钽层，其中所述五氧化二钽层通过化学气相沉积在约200℃ 使用有机钽化合物和氧化合物在约700℃至约875℃的温度下在N 2 O气氛中加热。 在所述绝缘层上形成第二多晶硅层; 至少蚀刻第一多晶硅层，第二多晶硅层和绝缘层，从而限定至少一个堆叠栅极结构; 以及在衬底中形成源区和漏区，由此形成至少一个存储单元。

公开(公告)号：US06221164B1

公开(公告)日：2001-04-24

申请号：US09491213

申请日：2000-01-25

申请人： Fuodoor Gologhlan ,  David Chi ,  Kent Kuohua Chang ,  Hector Serrato

发明人： Fuodoor Gologhlan ,  David Chi ,  Kent Kuohua Chang ,  Hector Serrato

IPC分类号： C23C1600

CPC分类号： C23C16/4412 ,  C23C16/4405 ,  C23C16/4407

摘要： In one embodiment, the present invention relates to a method of cleaning a low pressure chemical vapor deposition apparatus having TEOS material build-up therein involving contacting the low pressure chemical vapor deposition apparatus with a composition containing at least one lower alcohol. In another embodiment, the present invention relates to a system for cleaning a low pressure chemical vapor deposition apparatus having TEOS material build-up therein, containing a supply of a composition comprising at least one lower alcohol; an injection port for introducing the composition comprising at least one lower alcohol into the low pressure chemical vapor deposition apparatus; and a pump/vacuum system for removing crystallized TEOS material build-up from the low pressure chemical vapor deposition apparatus.

摘要翻译： 在一个实施方案中，本发明涉及清洗其中包含TEOS材料的低压化学气相沉积设备的方法，其中包括使低压化学气相沉积设备与含有至少一种低级醇的组合物接触。 在另一个实施方案中，本发明涉及用于清洗其中含有TEOS材料的低压化学气相沉积设备的系统，其中含有至少一种低级醇的组合物; 用于将包含至少一种低级醇的组合物引入低压化学气相沉积设备的注入口; 以及用于从低压化学气相沉积装置中除去结晶的TEOS材料积聚的泵/真空系统。

公开(公告)号：US6063666A

公开(公告)日：2000-05-16

申请号：US098292

申请日：1998-06-16

申请人： Kent Kuohua Chang ,  David Chi

发明人： Kent Kuohua Chang ,  David Chi

IPC分类号： H01L21/28 ,  H01L21/314 ,  H01L29/423 ,  H01L29/51 ,  H01L21/336 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/28202 ,  H01L21/28211 ,  H01L21/28273 ,  H01L21/3145 ,  H01L29/42324 ,  H01L29/511 ,  H01L29/518 ,  Y10S438/954

摘要： In one embodiment, the present invention relates to a method of forming a flash memory cell involving the steps of forming a tunnel oxide on a substrate; forming a first polysilicon layer over the tunnel oxide; forming an insulating layer over the first polysilicon layer, the insulating layer comprising a first oxide layer over the first polysilicon layer, a nitride layer over the first oxide layer, and a second oxide layer over the nitride layer, wherein the second oxide layer is made by forming the second oxide layer by rapid thermal chemical vapor deposition at a temperature from about 780.degree. C. to about 820.degree. C. using SiH.sub.4 and N.sub.2 O and annealing in an N.sub.2 O atmosphere a temperature from about 980.degree. C. to about 1020.degree. C.; forming a second polysilicon layer over the insulating layer; etching at least the first polysilicon layer, the second polysilicon layer and the insulating layer, thereby defining at least one stacked gate structure; and forming a source region and a drain region in the substrate, wherein the source region and the drain region are self-aligned by the stacked gate structure, thereby forming at least one memory cell.

摘要翻译： 在一个实施例中，本发明涉及一种形成闪存单元的方法，该闪存单元包括以下步骤：在衬底上形成隧道氧化物; 在隧道氧化物上形成第一多晶硅层; 在所述第一多晶硅层上形成绝缘层，所述绝缘层包括所述第一多晶硅层上的第一氧化物层，所述第一氧化物层上的氮化物层和所述氮化物层上的第二氧化物层，其中所述第二氧化物层被制成 通过使用SiH 4和N 2 O在约780℃至约820℃的温度下通过快速热化学气相沉积形成第二氧化物层并在N 2 O气氛中退火，温度为约980℃至约1020℃ 。 在所述绝缘层上形成第二多晶硅层; 至少蚀刻第一多晶硅层，第二多晶硅层和绝缘层，从而限定至少一个堆叠的栅极结构; 以及在所述衬底中形成源区和漏区，其中所述源区和所述漏区通过所述堆叠栅结构自对准，从而形成至少一个存储单元。

公开(公告)号：US06498104B1

公开(公告)日：2002-12-24

申请号：US09776308

申请日：2001-02-02

申请人： Fuodoor Gologhlan ,  David Chi ,  Kent Kuohua Chang ,  Hector Serrato

发明人： Fuodoor Gologhlan ,  David Chi ,  Kent Kuohua Chang ,  Hector Serrato

IPC分类号： H01L21311

CPC分类号： C23C16/4412 ,  C23C16/4405 ,  C23C16/4407

摘要： In one embodiment, the present invention relates to a method of cleaning a low pressure chemical vapor deposition apparatus having TEOS material build-up therein involving contacting the low pressure chemical vapor deposition apparatus with a composition containing at least one lower alcohol. In another embodiment, the present invention relates to a system for cleaning a low pressure chemical vapor deposition apparatus having TEOS material build-up therein, containing a supply of a composition comprising at least one lower alcohol; an injection port for introducing the composition including at least one lower alcohol into the low pressure chemical vapor deposition apparatus; and a pump/vacuum system for removing crystallized TEOS material build-up from the low pressure chemical vapor deposition apparatus.

摘要翻译： 在一个实施方案中，本发明涉及清洗其中包含TEOS材料的低压化学气相沉积设备的方法，其中包括使低压化学气相沉积设备与含有至少一种低级醇的组合物接触。 在另一个实施方案中，本发明涉及用于清洗其中含有TEOS材料的低压化学气相沉积设备的系统，其中含有至少一种低级醇的组合物; 用于将包含至少一种低级醇的组合物引入低压化学气相沉积装置的注入口; 以及用于从低压化学气相沉积装置中除去结晶的TEOS材料积聚的泵/真空系统。

公开(公告)号：US06458212B1

公开(公告)日：2002-10-01

申请号：US09539393

申请日：2000-03-31

申请人： Fuodoor Gologhlan ,  David Chi ,  Kent Kuohua Chang ,  Hector Serrato ,  Jayendra Bhakta

发明人： Fuodoor Gologhlan ,  David Chi ,  Kent Kuohua Chang ,  Hector Serrato ,  Jayendra Bhakta

IPC分类号： C23C1600

CPC分类号： C23C16/4412 ,  Y10S55/30

摘要： One aspect of the present invention relates to a tetraethylorthosilicate chemical vapor deposition method, involving the steps of forming a film on a substrate using tetraethylorthosilicate in a chemical vapor deposition chamber; and removing tetraethylorthosilicate byproducts from the chemical vapor deposition chamber via a pump system and an exhaust line connected to the chemical vapor deposition chamber, the exhaust line comprising a mesh filter having a conical shape. Another aspect of the present invention relates to an exhaust system for removing tetraethylorthosilicate byproducts from a chemical vapor deposition chamber, containing an exhaust line connected to the chemical vapor deposition chamber, the exhaust line comprising a mesh filter having a conical shape via a pump system; and a pump system connected to the exhaust line for removing tetraethylorthosilicate byproducts from the processing chamber.

摘要翻译： 本发明的一个方面涉及一种四乙基原硅酸盐化学气相沉积方法，包括以下步骤：在化学气相沉积室中使用原硅酸四乙酯在基底上形成膜; 以及经由泵系统和连接到化学气相沉积室的排气管线从化学气相沉积室除去原硅酸四乙酯副产物，排气管线包括具有圆锥形状的网状过滤器。 本发明的另一方面涉及一种用于从化学气相沉积室除去原硅酸四乙酯副产物的排气系统，该排气系统包含连接到化学气相沉积室的排气管线，该排气管线包括经由泵系统具有锥形形状的网状过滤器; 以及与排气管连接以从处理室除去原硅酸四乙酯副产物的泵系统。

公开(公告)号：US06184084B2

公开(公告)日：2001-02-06

申请号：US09263701

申请日：1999-03-05

申请人： David Chi ,  Kent Kuohua Chang ,  Yuesong He

发明人： David Chi ,  Kent Kuohua Chang ,  Yuesong He

IPC分类号： H01L21336

CPC分类号： H01L29/66825 ,  H01L21/3212

摘要： In one embodiment, the present invention relates to a method of forming a flash memory cell, involving the steps of forming a tunnel oxide on a substrate; forming a first polysilicon layer over the tunnel oxide; forming an insulating layer over the first polysilicon layer; forming a second polysilicon layer over the insulating layer by depositing an second polysilicon layer having a first thickness, and then using chemical mechanical polishing to form a second polysilicon layer having a second thickness, wherein the second thickness is at least about 25% less than the first thickness; forming a tungsten silicide layer over the second polysilicon layer by chemical vapor deposition using WF6 and SiH4; etching at least the first polysilicon layer, the second polysilicon layer, the insulating layer, and the tungsten silicide layer thereby defining at least one stacked gate structure; and forming a source region and a drain region in the substrate, thereby forming at least one memory cell.

摘要翻译： 在一个实施例中，本发明涉及一种形成闪速存储器单元的方法，包括在衬底上形成隧道氧化物的步骤; 在隧道氧化物上形成第一多晶硅层; 在所述第一多晶硅层上形成绝缘层; 通过沉积具有第一厚度的第二多晶硅层，然后使用化学机械抛光形成具有第二厚度的第二多晶硅层，在所述绝缘层上形成第二多晶硅层，其中所述第二厚度比所述第二厚度小至少约25％ 第一厚度 通过使用WF6和SiH4的化学气相沉积在第二多晶硅层上形成硅化钨层; 至少蚀刻第一多晶硅层，第二多晶硅层，绝缘层和硅化钨层，从而限定至少一个堆叠栅极结构; 以及在衬底中形成源区和漏区，由此形成至少一个存储单元。