公开(公告)号：US08635401B2

公开(公告)日：2014-01-21

申请号：US13453328

申请日：2012-04-23

申请人： John S. Dodson ,  Benjiman L. Goodman ,  Hillery C. Hunter ,  Steven Powell ,  Jeffrey A. Stuecheli

发明人： John S. Dodson ,  Benjiman L. Goodman ,  Hillery C. Hunter ,  Steven Powell ,  Jeffrey A. Stuecheli

IPC分类号： G06F13/10

CPC分类号： G11C11/40603

摘要： A method for performing refresh operations is disclosed. In response to a completion of a memory operation, a determination is made whether or not a refresh backlog count is greater than a first predetermined value. In a determination that the refresh backlog count is greater than the first predetermined value, a refresh operation is performed as soon as possible. In a determination that the refresh backlog count is not greater than the first predetermined value, a refresh operation is performed after a delay of an idle count value.

摘要翻译： 公开了一种执行刷新操作的方法。 响应于存储器操作的完成，确定刷新积压计数是否大于第一预定值。 在确定刷新积压计数大于第一预定值的情况下，尽可能快地执行刷新操作。 在确定刷新积压计数不大于第一预定值的情况下，在空闲计数值的延迟之后执行刷新操作。

公开(公告)号：US08489807B2

公开(公告)日：2013-07-16

申请号：US12959637

申请日：2010-12-03

申请人： John S. Dodson ,  Benjiman L. Goodman ,  Hillery C. Hunter ,  Stephen Powell ,  Jeffrey A. Stuecheli

发明人： John S. Dodson ,  Benjiman L. Goodman ,  Hillery C. Hunter ,  Stephen Powell ,  Jeffrey A. Stuecheli

IPC分类号： G06F12/00

CPC分类号： G11C11/40603

摘要： Techniques for performing refresh operations is disclosed. In response to a completion of a memory operation, a determination is made whether or not a refresh backlog count is greater than a first predetermined value. In a determination that the refresh backlog count is greater than the first predetermined value, a refresh operation is performed as soon as possible. In a determination that the refresh backlog count is not greater than the first predetermined value, a refresh operation is performed after a delay of an idle count value.

摘要翻译： 公开了用于执行刷新操作的技术。 响应于存储器操作的完成，确定刷新积压计数是否大于第一预定值。 在确定刷新积压计数大于第一预定值的情况下，尽可能快地执行刷新操作。 在确定刷新积压计数不大于第一预定值的情况下，在空闲计数值的延迟之后执行刷新操作。

公开(公告)号：US20120144105A1

公开(公告)日：2012-06-07

申请号：US12959637

申请日：2010-12-03

申请人： John S. Dodson ,  Benjiman L. Goodman ,  Hillery C. Hunter ,  Stephen Powell ,  Jeffrey A. Stuecheli

发明人： John S. Dodson ,  Benjiman L. Goodman ,  Hillery C. Hunter ,  Stephen Powell ,  Jeffrey A. Stuecheli

IPC分类号： G06F12/00

CPC分类号： G11C11/40603

摘要： A method for performing refresh operations is disclosed. In response to a completion of a memory operation, a determination is made whether or not a refresh backlog count is greater than a first predetermined value. In a determination that the refresh backlog count is greater than the first predetermined value, a refresh operation is performed as soon as possible. In a determination that the refresh backlog count is not greater than the first predetermined value, a refresh operation is performed after a delay of an idle count value.

摘要翻译： 公开了一种执行刷新操作的方法。 响应于存储器操作的完成，确定刷新积压计数是否大于第一预定值。 在确定刷新积压计数大于第一预定值的情况下，尽可能快地执行刷新操作。 在确定刷新积压计数不大于第一预定值的情况下，在空闲计数值的延迟之后执行刷新操作。

公开(公告)号：US08683128B2

公开(公告)日：2014-03-25

申请号：US12775511

申请日：2010-05-07

申请人： David M. Daly ,  Benjiman L. Goodman ,  Hillery C. Hunter ,  William J. Starke ,  Jeffrey A. Stuecheli

发明人： David M. Daly ,  Benjiman L. Goodman ,  Hillery C. Hunter ,  William J. Starke ,  Jeffrey A. Stuecheli

IPC分类号： G06F12/08

CPC分类号： G06F12/0897 ,  G06F12/0888 ,  Y02D10/13

摘要： A data processing system includes a multi-level cache hierarchy including a lowest level cache, a processor core coupled to the multi-level cache hierarchy, and a memory controller coupled to the lowest level cache and to a memory bus of a system memory. The memory controller includes a physical read queue that buffers data read from the system memory via the memory bus and a physical write queue that buffers data to be written to the system memory via the memory bus. The memory controller grants priority to write operations over read operations on the memory bus based upon a number of dirty cachelines in the lowest level cache memory.

公开(公告)号：US08615634B2

公开(公告)日：2013-12-24

申请号：US13447445

申请日：2012-04-16

申请人： David M. Daly ,  Benjiman L. Goodman ,  Hillery C. Hunter ,  William J. Starke ,  Jeffrey A. Stuecheli

发明人： David M. Daly ,  Benjiman L. Goodman ,  Hillery C. Hunter ,  William J. Starke ,  Jeffrey A. Stuecheli

IPC分类号： G06F12/08

CPC分类号： G06F12/0804 ,  G06F12/0817 ,  G06F12/0897 ,  Y02D10/13

摘要： A data processing system includes a processor core and a cache memory hierarchy coupled to the processor core. The cache memory hierarchy includes at least one upper level cache and a lowest level cache. A memory controller is coupled to the lowest level cache and to a system memory and includes a physical write queue from which the memory controller writes data to the system memory. The memory controller initiates accesses to the lowest level cache to place into the physical write queue selected cachelines having spatial locality with data present in the physical write queue.

摘要翻译： 数据处理系统包括处理器核心和耦合到处理器核心的高速缓存存储器层级。 高速缓存存储器层级包括至少一个上级高速缓存和最低级高速缓存。 存储器控制器耦合到最低级缓存和系统存储器，并且包括物理写队列，存储器控制器从该物理写队列将数据写入系统存储器。 存储器控制器启动对最低级高速缓存的访问以放置到物理写入队列中，所选择的高速缓存线具有空间局部性，其中数据存在于物理写入队列中。

公开(公告)号：US08838901B2

公开(公告)日：2014-09-16

申请号：US12775510

申请日：2010-05-07

申请人： David M. Daly ,  Benjiman L. Goodman ,  Hillery C. Hunter ,  William J. Starke ,  Jeffrey A. Stuecheli

发明人： David M. Daly ,  Benjiman L. Goodman ,  Hillery C. Hunter ,  William J. Starke ,  Jeffrey A. Stuecheli

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/0804 ,  G06F12/0817 ,  G06F12/0897 ,  Y02D10/13

摘要： A data processing system includes a processor core and a cache memory hierarchy coupled to the processor core. The cache memory hierarchy includes at least one upper level cache and a lowest level cache. A memory controller is coupled to the lowest level cache and to a system memory and includes a physical write queue from which the memory controller writes data to the system memory. The memory controller initiates accesses to the lowest level cache to place into the physical write queue selected cachelines having spatial locality with data present in the physical write queue.

摘要翻译： 数据处理系统包括处理器核心和耦合到处理器核心的高速缓存存储器层级。 高速缓存存储器层级包括至少一个上级高速缓存和最低级高速缓存。 存储器控制器耦合到最低级缓存和系统存储器，并且包括物理写队列，存储器控制器从该物理写队列将数据写入系统存储器。 存储器控制器启动对最低级高速缓存的访问以放置到物理写入队列中，所选择的高速缓存线具有空间局部性，其中数据存在于物理写入队列中。

公开(公告)号：US08645627B2

公开(公告)日：2014-02-04

申请号：US13447462

申请日：2012-04-16

申请人： David M. Daly ,  Benjiman L. Goodman ,  Hillery C. Hunter ,  William J. Starke ,  Jeffrey A. Stuecheli

发明人： David M. Daly ,  Benjiman L. Goodman ,  Hillery C. Hunter ,  William J. Starke ,  Jeffrey A. Stuecheli

IPC分类号： G06F12/08

CPC分类号： G06F12/0897 ,  G06F12/0888 ,  Y02D10/13

摘要： A data processing system includes a multi-level cache hierarchy including a lowest level cache, a processor core coupled to the multi-level cache hierarchy, and a memory controller coupled to the lowest level cache and to a memory bus of a system memory. The memory controller includes a physical read queue that buffers data read from the system memory via the memory bus and a physical write queue that buffers data to be written to the system memory via the memory bus. The memory controller grants priority to write operations over read operations on the memory bus based upon a number of dirty cachelines in the lowest level cache memory.

摘要翻译： 数据处理系统包括包括最低级高速缓存，耦合到多级高速缓存层级的处理器核心以及耦合到最低级高速缓存和存储器系统存储器的存储器总线的存储器控​​制器的多级高速缓存层级。 存储器控制器包括物理读取队列，其缓冲通过存储器总线从系统存储器读取的数据，以及物理写入队列，其通过存储器总线缓冲要写入系统存储器的数据。 存储器控制器基于最低级高速缓冲存储器中的多个脏高速缓存线，对存储器总线上的读操作授予优先级。

公开(公告)号：US08688915B2

公开(公告)日：2014-04-01

申请号：US13315411

申请日：2011-12-09

申请人： David M. Daly ,  Benjiman L. Goodman ,  Stephen J. Powell ,  Aaron C. Sawdey ,  Jeffrey A. Stuecheli

发明人： David M. Daly ,  Benjiman L. Goodman ,  Stephen J. Powell ,  Aaron C. Sawdey ,  Jeffrey A. Stuecheli

IPC分类号： G06F12/16

CPC分类号： G06F12/122 ,  G06F12/0897 ,  G06F12/121

摘要： A mechanism is provided for weighted history allocation prediction. For each member in a plurality of members in a lower level cache, an associated reference counter is initialized to an initial value based on an operation type that caused data to be allocated to a member location of the member. For each access to the member in the lower level cache, the associated reference counter is incremented. Responsive to a new allocation of data to the lower level cache and responsive to the new allocation of data requiring the victimization of another member in the lower level cache, a member of the lower level cache is identified that has a lowest reference count value in its associated reference counter. The member with the lowest reference count value in its associated reference counter is then evicted.

摘要翻译： 提供了一种用于加权历史分配预测的机制。 对于较低级缓存中的多个成员中的每个成员，相关联的引用计数器基于导致数据被分配给成员的成员位置的操作类型被初始化为初始值。 对于对较低级缓存中的成员的每次访问，相关联的引用计数器递增。 响应于对低级缓存的新数据分配并响应于需要在较低级别高速缓存中另一成员受害的数据的新分配，识别出在其级别缓存中具有最低参考计数值的成员 相关参考计数器。 然后将其相关参考计数器中具有最低参考计数值的成员逐出。

公开(公告)号：US08103791B2

公开(公告)日：2012-01-24

申请号：US12195130

申请日：2008-08-20

申请人： Benjiman L. Goodman ,  Guy L. Guthrie ,  Praveen S. Reddy ,  William J. Starke ,  Jeffrey A. Stuecheli

发明人： Benjiman L. Goodman ,  Guy L. Guthrie ,  Praveen S. Reddy ,  William J. Starke ,  Jeffrey A. Stuecheli

IPC分类号： G06F15/173 ,  G06F12/00 ,  G06F13/14 ,  G06F1/04 ,  G06F1/12

CPC分类号： G06F15/16

摘要： A data processing system includes a plurality of processing units, including at least a local master and a local hub, which are coupled for communication via a communication link. The local master includes a master capable of initiating an operation, a snooper capable of receiving an operation, and interconnect logic coupled to a communication link coupling the local master to the local hub. The interconnect logic includes request logic that synchronizes internal transmission of a request of the master to the snooper with transmission, via the communication link, of the request to the local hub.

摘要翻译： 数据处理系统包括多个处理单元，至少包括本地主站和本地集线器，其经由通信链路进行通信。 本地主机包括能够启动操作的主机，能够接收操作的监听器，以及耦合到将本地主机耦合到本地集线器的通信链路的逻辑互连。 互连逻辑包括请求逻辑，其将主机的请求的内部传输与通过通信链路传送到本地集线器的请求同步到窥探者的请求逻辑。

公开(公告)号：US07818511B2

公开(公告)日：2010-10-19

申请号：US11847941

申请日：2007-08-30

申请人： Benjiman L. Goodman ,  Guy L. Guthrie ,  William J. Starke ,  Jeffrey A. Stuecheli ,  Derek E. Williams

发明人： Benjiman L. Goodman ,  Guy L. Guthrie ,  William J. Starke ,  Jeffrey A. Stuecheli ,  Derek E. Williams

IPC分类号： G06F12/00

CPC分类号： G06F12/0831

摘要： A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. Information, such as the address, of the snoop request is stored in a queue of the stall/reorder unit. The stall/reorder unit forwards the snoop request to a selector which also receives a request from a processor. An arbitration mechanism selects either the snoop request or the request from the processor. If the snoop request is denied by the arbitration mechanism, information, e.g., address, about the snoop request may be maintained in the stall/reorder unit. The request may be later resent to the selector. This process may be repeated up to “n” clock cycles. By providing the snoop request additional opportunities (n clock cycles) to be accepted by the arbitration mechanism, fewer snoop requests may ultimately be denied.

摘要翻译： 用于减少拒绝的窥探请求数量的缓存，系统和方法。 缓存中的“停止/重新排序单元”从互连中接收窥探请求。 窥探请求的诸如地址的信息被存储在失速/重新排序单元的队列中。 停止/重新排序单元将窥探请求转发到也从处理器接收请求的选择器。 仲裁机制选择来自处理器的窥探请求或请求。 如果侦听请求被仲裁机制拒绝，关于窥探请求的信息（例如地址）可以被保留在停止/重新排序单元中。 请求可能会稍后重新发送到选择器。 该过程可以重复直到“n”个时钟周期。 通过提供窥探请求仲裁机制接受的额外机会（n个时钟周期），最终可能会拒绝更少的侦听请求。