公开(公告)号：US08635401B2

公开(公告)日：2014-01-21

申请号：US13453328

申请日：2012-04-23

申请人： John S. Dodson ,  Benjiman L. Goodman ,  Hillery C. Hunter ,  Steven Powell ,  Jeffrey A. Stuecheli

发明人： John S. Dodson ,  Benjiman L. Goodman ,  Hillery C. Hunter ,  Steven Powell ,  Jeffrey A. Stuecheli

IPC分类号： G06F13/10

CPC分类号： G11C11/40603

摘要： A method for performing refresh operations is disclosed. In response to a completion of a memory operation, a determination is made whether or not a refresh backlog count is greater than a first predetermined value. In a determination that the refresh backlog count is greater than the first predetermined value, a refresh operation is performed as soon as possible. In a determination that the refresh backlog count is not greater than the first predetermined value, a refresh operation is performed after a delay of an idle count value.

摘要翻译： 公开了一种执行刷新操作的方法。 响应于存储器操作的完成，确定刷新积压计数是否大于第一预定值。 在确定刷新积压计数大于第一预定值的情况下，尽可能快地执行刷新操作。 在确定刷新积压计数不大于第一预定值的情况下，在空闲计数值的延迟之后执行刷新操作。

公开(公告)号：US08489807B2

公开(公告)日：2013-07-16

申请号：US12959637

申请日：2010-12-03

申请人： John S. Dodson ,  Benjiman L. Goodman ,  Hillery C. Hunter ,  Stephen Powell ,  Jeffrey A. Stuecheli

发明人： John S. Dodson ,  Benjiman L. Goodman ,  Hillery C. Hunter ,  Stephen Powell ,  Jeffrey A. Stuecheli

IPC分类号： G06F12/00

CPC分类号： G11C11/40603

摘要： Techniques for performing refresh operations is disclosed. In response to a completion of a memory operation, a determination is made whether or not a refresh backlog count is greater than a first predetermined value. In a determination that the refresh backlog count is greater than the first predetermined value, a refresh operation is performed as soon as possible. In a determination that the refresh backlog count is not greater than the first predetermined value, a refresh operation is performed after a delay of an idle count value.

摘要翻译： 公开了用于执行刷新操作的技术。 响应于存储器操作的完成，确定刷新积压计数是否大于第一预定值。 在确定刷新积压计数大于第一预定值的情况下，尽可能快地执行刷新操作。 在确定刷新积压计数不大于第一预定值的情况下，在空闲计数值的延迟之后执行刷新操作。

公开(公告)号：US20120144105A1

公开(公告)日：2012-06-07

申请号：US12959637

申请日：2010-12-03

申请人： John S. Dodson ,  Benjiman L. Goodman ,  Hillery C. Hunter ,  Stephen Powell ,  Jeffrey A. Stuecheli

发明人： John S. Dodson ,  Benjiman L. Goodman ,  Hillery C. Hunter ,  Stephen Powell ,  Jeffrey A. Stuecheli

IPC分类号： G06F12/00

CPC分类号： G11C11/40603

摘要： A method for performing refresh operations is disclosed. In response to a completion of a memory operation, a determination is made whether or not a refresh backlog count is greater than a first predetermined value. In a determination that the refresh backlog count is greater than the first predetermined value, a refresh operation is performed as soon as possible. In a determination that the refresh backlog count is not greater than the first predetermined value, a refresh operation is performed after a delay of an idle count value.

摘要翻译： 公开了一种执行刷新操作的方法。 响应于存储器操作的完成，确定刷新积压计数是否大于第一预定值。 在确定刷新积压计数大于第一预定值的情况下，尽可能快地执行刷新操作。 在确定刷新积压计数不大于第一预定值的情况下，在空闲计数值的延迟之后执行刷新操作。

公开(公告)号：US08683128B2

公开(公告)日：2014-03-25

申请号：US12775511

申请日：2010-05-07

申请人： David M. Daly ,  Benjiman L. Goodman ,  Hillery C. Hunter ,  William J. Starke ,  Jeffrey A. Stuecheli

发明人： David M. Daly ,  Benjiman L. Goodman ,  Hillery C. Hunter ,  William J. Starke ,  Jeffrey A. Stuecheli

IPC分类号： G06F12/08

CPC分类号： G06F12/0897 ,  G06F12/0888 ,  Y02D10/13

摘要： A data processing system includes a multi-level cache hierarchy including a lowest level cache, a processor core coupled to the multi-level cache hierarchy, and a memory controller coupled to the lowest level cache and to a memory bus of a system memory. The memory controller includes a physical read queue that buffers data read from the system memory via the memory bus and a physical write queue that buffers data to be written to the system memory via the memory bus. The memory controller grants priority to write operations over read operations on the memory bus based upon a number of dirty cachelines in the lowest level cache memory.

公开(公告)号：US08615634B2

公开(公告)日：2013-12-24

申请号：US13447445

申请日：2012-04-16

申请人： David M. Daly ,  Benjiman L. Goodman ,  Hillery C. Hunter ,  William J. Starke ,  Jeffrey A. Stuecheli

发明人： David M. Daly ,  Benjiman L. Goodman ,  Hillery C. Hunter ,  William J. Starke ,  Jeffrey A. Stuecheli

IPC分类号： G06F12/08

CPC分类号： G06F12/0804 ,  G06F12/0817 ,  G06F12/0897 ,  Y02D10/13

摘要： A data processing system includes a processor core and a cache memory hierarchy coupled to the processor core. The cache memory hierarchy includes at least one upper level cache and a lowest level cache. A memory controller is coupled to the lowest level cache and to a system memory and includes a physical write queue from which the memory controller writes data to the system memory. The memory controller initiates accesses to the lowest level cache to place into the physical write queue selected cachelines having spatial locality with data present in the physical write queue.

摘要翻译： 数据处理系统包括处理器核心和耦合到处理器核心的高速缓存存储器层级。 高速缓存存储器层级包括至少一个上级高速缓存和最低级高速缓存。 存储器控制器耦合到最低级缓存和系统存储器，并且包括物理写队列，存储器控制器从该物理写队列将数据写入系统存储器。 存储器控制器启动对最低级高速缓存的访问以放置到物理写入队列中，所选择的高速缓存线具有空间局部性，其中数据存在于物理写入队列中。

公开(公告)号：US08838901B2

公开(公告)日：2014-09-16

申请号：US12775510

申请日：2010-05-07

申请人： David M. Daly ,  Benjiman L. Goodman ,  Hillery C. Hunter ,  William J. Starke ,  Jeffrey A. Stuecheli

发明人： David M. Daly ,  Benjiman L. Goodman ,  Hillery C. Hunter ,  William J. Starke ,  Jeffrey A. Stuecheli

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/0804 ,  G06F12/0817 ,  G06F12/0897 ,  Y02D10/13

摘要： A data processing system includes a processor core and a cache memory hierarchy coupled to the processor core. The cache memory hierarchy includes at least one upper level cache and a lowest level cache. A memory controller is coupled to the lowest level cache and to a system memory and includes a physical write queue from which the memory controller writes data to the system memory. The memory controller initiates accesses to the lowest level cache to place into the physical write queue selected cachelines having spatial locality with data present in the physical write queue.

摘要翻译： 数据处理系统包括处理器核心和耦合到处理器核心的高速缓存存储器层级。 高速缓存存储器层级包括至少一个上级高速缓存和最低级高速缓存。 存储器控制器耦合到最低级缓存和系统存储器，并且包括物理写队列，存储器控制器从该物理写队列将数据写入系统存储器。 存储器控制器启动对最低级高速缓存的访问以放置到物理写入队列中，所选择的高速缓存线具有空间局部性，其中数据存在于物理写入队列中。

公开(公告)号：US08645627B2

公开(公告)日：2014-02-04

申请号：US13447462

申请日：2012-04-16

申请人： David M. Daly ,  Benjiman L. Goodman ,  Hillery C. Hunter ,  William J. Starke ,  Jeffrey A. Stuecheli

发明人： David M. Daly ,  Benjiman L. Goodman ,  Hillery C. Hunter ,  William J. Starke ,  Jeffrey A. Stuecheli

IPC分类号： G06F12/08

CPC分类号： G06F12/0897 ,  G06F12/0888 ,  Y02D10/13

摘要： A data processing system includes a multi-level cache hierarchy including a lowest level cache, a processor core coupled to the multi-level cache hierarchy, and a memory controller coupled to the lowest level cache and to a memory bus of a system memory. The memory controller includes a physical read queue that buffers data read from the system memory via the memory bus and a physical write queue that buffers data to be written to the system memory via the memory bus. The memory controller grants priority to write operations over read operations on the memory bus based upon a number of dirty cachelines in the lowest level cache memory.

摘要翻译： 数据处理系统包括包括最低级高速缓存，耦合到多级高速缓存层级的处理器核心以及耦合到最低级高速缓存和存储器系统存储器的存储器总线的存储器控​​制器的多级高速缓存层级。 存储器控制器包括物理读取队列，其缓冲通过存储器总线从系统存储器读取的数据，以及物理写入队列，其通过存储器总线缓冲要写入系统存储器的数据。 存储器控制器基于最低级高速缓冲存储器中的多个脏高速缓存线，对存储器总线上的读操作授予优先级。

公开(公告)号：US20130128682A1

公开(公告)日：2013-05-23

申请号：US13298587

申请日：2011-11-17

申请人： Joab D. Henderson ,  Hillery C. Hunter ,  Warren E. Maule ,  Jeffrey A. Stuecheli

发明人： Joab D. Henderson ,  Hillery C. Hunter ,  Warren E. Maule ,  Jeffrey A. Stuecheli

IPC分类号： G11C11/402

CPC分类号： G11C11/40611 ,  G11C2211/4061

摘要： An embodiment provided is a memory system with dynamic refreshing that includes a memory device with memory cells. The system also includes a refresh module in communication with the memory device and with a memory controller, the refresh module configured for receiving a refresh command from the memory controller and for refreshing a number of the memory cells in the memory device in response to receiving the refresh command. The number of memory cells refreshed in response to receiving the refresh command is responsive to at least one of a desired bandwidth characteristic and a desired latency characteristic.

摘要翻译： 提供的实施例是具有动态刷新的存储器系统，其包括具有存储器单元的存储器件。 该系统还包括与存储器设备和存储器控制器通信的刷新模块，该刷新模块被配置用于从存储器控制器接收刷新命令，并且响应于接收到所述存储器控制器来刷新存储器设备中的多个存储器单元 刷新命令。 响应于接收到刷新命令刷新的存储器单元的数量响应期望带宽特性和期望延迟特性中的至少一个。

公开(公告)号：US08705307B2

公开(公告)日：2014-04-22

申请号：US13298587

申请日：2011-11-17

申请人： Joab D. Henderson ,  Hillery C. Hunter ,  Warren E. Maule ,  Jeffrey A. Stuecheli

发明人： Joab D. Henderson ,  Hillery C. Hunter ,  Warren E. Maule ,  Jeffrey A. Stuecheli

IPC分类号： G11C7/00

CPC分类号： G11C11/40611 ,  G11C2211/4061

摘要： An embodiment provided is a memory system with dynamic refreshing that includes a memory device with memory cells. The system also includes a refresh module in communication with the memory device and with a memory controller, the refresh module configured for receiving a refresh command from the memory controller and for refreshing a number of the memory cells in the memory device in response to receiving the refresh command. The number of memory cells refreshed in response to receiving the refresh command is responsive to at least one of a desired bandwidth characteristic and a desired latency characteristic.

摘要翻译： 提供的实施例是具有动态刷新的存储器系统，其包括具有存储器单元的存储器件。 该系统还包括与存储器设备和存储器控制器通信的刷新模块，该刷新模块被配置用于从存储器控制器接收刷新命令，并且响应于接收到所述存储器控制器来刷新存储器设备中的多个存储器单元 刷新命令。 响应于接收到刷新命令刷新的存储器单元的数量响应期望带宽特性和期望延迟特性中的至少一个。

公开(公告)号：US20120300563A1

公开(公告)日：2012-11-29

申请号：US13567353

申请日：2012-08-06

申请人： Kyu-Hyoun Kim ,  George L. Chiu ,  Paul W. Coteus ,  Daniel M. Dreps ,  Kevin C. Gower ,  Hillery C. Hunter ,  Charles A. Kilmer ,  Warren E. Maule

发明人： Kyu-Hyoun Kim ,  George L. Chiu ,  Paul W. Coteus ,  Daniel M. Dreps ,  Kevin C. Gower ,  Hillery C. Hunter ,  Charles A. Kilmer ,  Warren E. Maule

IPC分类号： G11C7/00

CPC分类号： G11C7/1078 ,  G06F11/1028 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/109 ,  G11C7/22 ,  G11C7/222 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40615 ,  G11C11/40626 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

摘要： An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.

摘要翻译： 具有改进性能，降低功耗和增加可靠性的高级内存。 存储器件包括存储器阵列，用于接收命令和相关联的数据的接收器，用于对接收到的命令执行错误控制检查的差错控制编码电路以及用于防止相关联的数据被响应地写入存储器阵列的数据屏蔽电路 对错误控制编码电路检测接收到的命令中的错误。 另一个存储器件包括可编程序序。 另一存储器件包括快速退出自刷新模式。 另一种存储装置包括由特征装置控制的自动刷新功能。 另一存储器件包括由存储器件的特性控制的自动刷新功能。