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公开(公告)号：US06347233B1
公开(公告)日：2002-02-12
申请号：US09569418
申请日：2000-05-12
IPC分类号： H04B138
CPC分类号： H04L27/2017 , H04L27/0008
摘要： A dual mode wireless device in which a coefficient generator (42) generates parameter values for a GSM waveform, based on transmitted sequences of digital data values from a GSM unit (34), using a multiplierless operation, and a waveform generator 44 generating the GSM waveform using the generated parameter values. The coefficient generator includes adder sections (132, 134, 136), each having corresponding adders (142, 144, 146) and multipliers (148, 150, 152), register sections (154, 156, 158), each containing parameters corresponding to a modulator (48), and transmit data registers (TXDATA[5]-TXDATA[0]) sequentially receiving the digital data values from the GSM unit. The coefficient generator generates the parameter values for the GSM waveform by multiplying each of the parameters in the register sections by a one or a negative one, responsive to the digital data values in the transmit data registers, and adding the resulting products to form corresponding coefficient generator output values.
摘要翻译： 一种双模无线装置，其中系数发生器（42）使用无乘法运算从GSM单元（34）发送的数字数据序列生成GSM波形的参数值，以及产生GSM的波形发生器44 波形使用生成的参数值。 系数发生器包括加法器部分（132,134,136），每个加法器部分具有相应的加法器（142,144,146）和乘法器（148,150,152），寄存器部分（154,156,158） 调制器（48），以及从GSM单元顺序地接收数字数据值的发送数据寄存器（TXDATA [5] -TXDATA [0]）。 系数发生器响应于发送数据寄存器中的数字数据值，通过将寄存器部分中的每个参数乘以一个或者负数来生成GSM波形的参数值，并将所得到的乘积相加以形成相应的系数 发电机输出值。
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公开(公告)号：US06239636B1
公开(公告)日：2001-05-29
申请号：US09569417
申请日：2000-05-12
IPC分类号： H03K3017
CPC分类号： H04L27/0008
摘要： A waveform generator for generating a waveform in a dual mode wireless device includes a first waveform generator portion (106) and a second waveform generator portion (108). The first waveform generator portion includes a first register (86) connected in series with a second register (84) and a first feedback selector (88), and the second waveform generator portion includes a third register (102) connected in series with a fourth register (100) and a second feedback selector (104). The first register and the third register, and the second register and the fourth register are set up as accumulators, and a new output data value of the first and third register is obtained by adding a corresponding previous data value of the first register and the third register, respectively, and a corresponding previous data value of the second register and the fourth register, respectively, and a new data output value of the second and fourth register is obtained by adding a corresponding previous data value of the second register and the fourth register, respectively, and a scaled previous output data value of the first and third registers.
摘要翻译： 用于在双模无线装置中生成波形的波形发生器包括第一波形发生器部分（106）和第二波形发生器部分（108）。 第一波形发生器部分包括与第二寄存器（84）串联连接的第一寄存器（86）和第一反馈选择器（88），第二波形发生器部分包括与第四寄存器串联连接的第三寄存器（102） 寄存器（100）和第二反馈选择器（104）。 第一寄存器和第三寄存器以及第二寄存器和第四寄存器被设置为累加器，并且通过将第一寄存器和第三寄存器的第一寄存器和第三寄存器的相应的先前数据值相加来获得第一和第三寄存器的新的输出数据值 分别与第二寄存器和第四寄存器的相应的先前数据值相对应，并且通过将第二寄存器和第四寄存器的对应的先前数据值相加来获得第二和第四寄存器的新数据输出值 和第一和第三寄存器的缩放的先前输出数据值。
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公开(公告)号：US09019011B2
公开(公告)日：2015-04-28
申请号：US13486012
申请日：2012-06-01
CPC分类号： H03F1/32 , H03F1/0222
摘要： A method for power amplifier (PA) calibration for an envelope tracking system of a wireless device is disclosed. The method involves measuring an output power of a PA that is a part under test (PUT) at a predetermined input power. Another step includes calculating a gain equal to the output power of the PA divided by the predetermined input power. A next step involves calculating a gain correction by subtracting the calculated gain from a desired gain. Other steps include determining an expected supply voltage for the PA at the desired gain using the gain correction applied to a nominal curve of gain versus PA supply voltage, and then storing the expected supply voltage for the PA versus input power in memory.
摘要翻译： 公开了一种用于无线设备的包络跟踪系统的功率放大器（PA）校准方法。 该方法包括以预定输入功率测量作为被测部件（PUT）的PA的输出功率。 另一步骤包括计算等于PA的输出功率除以预定输入功率的增益。 下一步涉及通过从期望的增益中减去所计算的增益来计算增益校正。 其他步骤包括使用增益校正应用于增益对PA电源电压的增益校正来确定期望增益的PA的预期电源电压，然后将PA的预期电源电压与输入功率存储在存储器中。
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公开(公告)号：US08774065B2
公开(公告)日：2014-07-08
申请号：US13460861
申请日：2012-05-01
IPC分类号： H04B7/00
CPC分类号： H04B1/0067 , H03F1/02 , H03F1/0227 , H03F3/24 , H03F3/68 , H03F3/72 , H03F2203/7209 , H03F2203/7221 , H04B2001/045 , H04L5/001
摘要： A front end radio architecture (FERA) with power management is disclosed. The FERA includes a first power amplifier (PA) block having a first-first PA and a first-second PA, and a second PA block having a second-first PA and a second-second PA. First and second modulated switchers are adapted to selectively supply power to the first-first PA and the second-first PA, and to supply power to the first-second PA and the second-second PA, respectively. The first and second modulated switchers have a modulation bandwidth of at least 20 MHz and are both suitable for envelope tracking modulation. A control system is adapted to selectively enable and disable the first-first PA, first-second PA, the second-first PA, and the second-second PA. First and second switches are responsive to control signals to route carriers and received signals between first and second antennas depending upon a selectable mode of operation such as intra-band or inter-band operation.
摘要翻译： 公开了具有电源管理的前端无线电架构（FERA）。 FERA包括具有第一第一PA和第一秒PA的第一功率放大器（PA）块和具有第二第一PA和第二秒PA的第二PA块。 第一和第二调制切换器适于选择性地向第一优先PA和第二第一PA供电，并分别向第一秒PA和第二秒PA供电。 第一和第二调制切换器具有至少20MHz的调制带宽，并且都适用于包络跟踪调制。 控制系统适于选择性地启用和禁用第一优先PA，第一秒PA，第二优先PA和第二秒PA。 第一和第二开关响应于控制信号以根据诸如带内或频带间操作的可选择的操作模式在第一和第二天线之间路由载波和接收信号。
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公开(公告)号：US07991071B2
公开(公告)日：2011-08-02
申请号：US10147569
申请日：2002-05-16
CPC分类号： H04L27/361
摘要： A transmitter includes a polar modulator that creates phase and amplitude signals which in turn drive a power amplifier. To compensate for AM to PM conversion of the amplitude signal into the amplified signal, a compensation signal is generated from the amplitude signal and combined with the phase signal such that when amplified, the compensation signal cancels the AM to PM conversion. The compensation signal may have an offset term, a linear term, a quadratic term, and a cubic term. A second embodiment comprises a technique by which AM to AM conversion may concurrently be addressed using a second compensation signal.
摘要翻译： 发射机包括极化调制器，其产生相位和幅度信号，其又驱动功率放大器。 为了补偿振幅信号的AM到PM转换为放大信号，从幅度信号产生补偿信号并与相位信号组合，使得当放大时，补偿信号取消AM到PM转换。 补偿信号可以具有偏移项，线性项，二次项和三次项。 第二实施例包括一种可以使用第二补偿信号并行地寻址AM到AM转换的技术。
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6.发明授权公开(公告)号：US07962109B1
公开(公告)日：2011-06-14
申请号：US11679201
申请日：2007-02-27
IPC分类号： H04B17/00
CPC分类号： H03G3/3047
摘要： A system and method for detecting and correcting over-current and/or over-voltage conditions in power amplifier circuitry in a transmit chain of a mobile terminal are provided. In general, over-current detection and correction circuitry combines a current detection signal indicative of a current provided to or drained by the power amplifier circuitry during ramp-up for a transmit burst and a substantially inverse current ramping profile to provide a first constant value. The first constant value is compared to a current threshold or limit value to determine whether an over-current condition exists. If an over-current condition exists, the over-current detection and correction circuitry operates to reduce the output power of the power amplifier circuitry during ramp-up for the transmit burst to correct for the over-current condition. In a similar manner, over-voltage detection circuitry operates to detect and correct over-voltage conditions during ramp-up for the transmit burst.
摘要翻译： 提供了一种用于在移动终端的发射链中的功率放大器电路中检测和校正过电流和/或过电压条件的系统和方法。 通常，过电流检测和校正电路组合指示在斜波上升期间功率放大器电路提供给发射脉冲串的电流的电流检测信号和用于发射脉冲串的基本上反向电流斜坡分布以提供第一恒定值。 将第一常数值与当前阈值或限制值进行比较，以确定是否存在过电流条件。 如果存在过电流状况，则过流检测和校正电路用于在发射突发的斜坡上降低功率放大器电路的输出功率，以校正过电流状况。 以类似的方式，过电压检测电路用于在发射突发的斜坡上升期间检测和校正过电压状况。
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7.发明授权System and method for transitioning from one PLL feedback source to another 有权从一个PLL反馈源转换到另一个PLL反馈源的系统和方法公开(公告)号：US07412215B1
公开(公告)日：2008-08-12
申请号：US11144119
申请日：2005-06-03
IPC分类号： H04B1/04
CPC分类号： H04B1/0475 , H03L7/081 , H03L7/087 , H03L7/16 , H03L2207/12
摘要： A system and method are provided for switching from one phase-locked loop feedback source to another in a radio frequency (RF) transmitter. The RF transmitter includes a phase-locked loop (PLL) that provides a phase-modulated RF input signal and power amplifier circuitry that amplifies the RF input signal to provide an RF output signal. The PLL includes switching circuitry that couples a feedback path of the PLL to an output of the PLL for open loop operation and couples the feedback path of the PLL to an output of the power amplifier circuitry for closed loop operation. Prior to switching the feedback path from the output of the PLL to the output of the power amplifier circuitry, time alignment circuitry operates to time-align feedback signals from the outputs of the PLL and the power amplifier circuitry such that switching from open loop operation to closed loop operation causes minimal phase disturbance.
摘要翻译： 提供了一种用于在射频（RF）发射机中从一个锁相环反馈源切换到另一个的系统和方法。 RF发射器包括提供相位调制RF输入信号的锁相环（PLL）和放大RF输入信号以提供RF输出信号的功率放大器电路。 PLL包括将PLL的反馈路径耦合到PLL的输出以用于开环操作的开关电路，并将PLL的反馈路径耦合到用于闭环操作的功率放大器电路的输出。 在将反馈路径从PLL的输出切换到功率放大器电路的输出之前，时间对准电路用于对来自PLL和功率放大器电路的输出的反馈信号进行时间对准，使得从开环操作切换到 闭环运行导致最小的相位扰动。
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公开(公告)号：US07313376B1
公开(公告)日：2007-12-25
申请号：US10987883
申请日：2004-11-12
IPC分类号： H04B1/06
CPC分类号： H04B1/30
摘要： A system and method for performing DC offset correction in a wireless communication receiver during “dead time” are provided. The receiver includes amplifier circuitry that amplifies a received radio frequency (RF) signal, downconversion circuitry that downconverts the received RF signal to provide a downconverted signal, digitization circuitry that digitizes the downconverted signal to provide a digital signal, and digital DC offset correction circuitry enabled during the dead time when there should be no DC content in the downconverted signal. In operation, the digital DC offset correction circuitry detects a DC offset of the digital signal and subtracts the DC offset from the digital signal.
摘要翻译： 提供了在“死区时间”期间在无线通信接收机中进行DC偏移校正的系统和方法。 接收器包括放大接收的射频（RF）信号的放大器电路，降频所接收的RF信号以提供下变频信号的下变频电路，使下变频信号数字化以提供数字信号的数字化电路和启用的数字DC偏移校正电路 在死区时间内，在下变频信号中不应有直流含量。 在操作中，数字DC偏移校正电路检测数字信号的DC偏移，并从数字信号中减去DC偏移。
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9.发明授权Pre-distortion system for a synthesizer having modulation applied in the reference path 有权具有在参考路径中应用的调制的合成器的预失真系统公开(公告)号：US07288999B1
公开(公告)日：2007-10-30
申请号：US11347956
申请日：2006-02-06
CPC分类号： H03L7/1976 , H03C3/0966 , H03L7/23 , H03L2207/12
摘要： A system providing a phase or frequency modulated signal is provided. In general, the system includes a phase locked loop (PLL) having a fractional-N divider in a reference path of the PLL operating to divide a reference frequency based on a pre-distorted modulation signal. Pre-distortion circuitry operates to provide the pre-distorted modulation signal by pre-distorting a modulation signal such that a convolution, or cascade, of the pre-distortion and a transfer function of the PLL results in a substantially flat frequency response for a range of modulation rates greater than a bandwidth of the PLL.
摘要翻译： 提供了提供相位或频率调制信号的系统。 通常，该系统包括在PLL的参考路径中具有分数N分频器的锁相环（PLL），其操作以基于预失真调制信号来划分参考频率。 预失真电路通过对调制信号进行预失真来提供预失真调制信号，使得预失真和PLL的传递函数的卷积或级联导致范围内的基本平坦的频率响应 的调制率大于PLL的带宽。
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公开(公告)号：US20060170505A1
公开(公告)日：2006-08-03
申请号：US11047258
申请日：2005-01-31
IPC分类号： H03L7/00
CPC分类号： H03L7/1976 , H03C3/0966 , H03L7/23 , H03L2207/12
摘要： A fractional-N offset phase locked loop (FN-OPLL) is provided. The FN-OPLL includes a fractional divider, a phase detector, a loop filter, a voltage controlled oscillator (VCO), and feedback circuitry. Combiner circuitry combines an initial fractional divide value and a modulation signal to provide a combined fractional divide value. Based on the combined fractional divide value, the fractional-N divider divides a reference frequency and provides a divided reference frequency to the phase detector. The phase detector compares a phase of the divided reference frequency to a phase of a feedback signal to provide a comparison signal. The comparison signal is filtered by the loop filter to provide a control signal to the VCO, where the control signal controls a frequency of an output signal of the VCO. The output signal is processed by the feedback circuitry to provide the feedback signal to the phase detector.
摘要翻译： 提供了一个分数N偏移锁相环（FN-OPLL）。 FN-OPLL包括分数分频器，相位检测器，环路滤波器，压控振荡器（VCO）和反馈电路。 组合器电路组合初始分数除法值和调制信号以提供组合分数除数值。 基于组合分数除法，分数N分频器划分参考频率，并向相位检测器提供分频参考频率。 相位检测器将分频参考频率的相位与反馈信号的相位进行比较，以提供比较信号。 比较信号由环路滤波器滤波，以向VCO提供控制信号，其中控制信号控制VCO的输出信号的频率。 输出信号由反馈电路处理，以将反馈信号提供给相位检测器。
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