公开(公告)号：US5687328A

公开(公告)日：1997-11-11

申请号：US442551

申请日：1995-05-16

申请人： Johnny Chuang-Li Lee

发明人： Johnny Chuang-Li Lee

IPC分类号： G06F13/40 ,  G06F12/00 ,  G06F13/00

CPC分类号： G06F13/4013

摘要： A data alignment logic cell properly aligns the individual data units (e.g., bytes) in a block of data that is transferred in a multiple bit bus such that the data units in the block are transferred to desired lanes of the bus. The data alignment logic cell includes a gathering unit, which aligns the data units into a fixed, justified arrangement in the bus, and a scattering unit, which receives the data units from the gathering unit and realigns them to the desired lanes. Both the gathering and scattering units contain registers for temporarily storing certain of the data units and multiplexers for transferring the data units between the lanes of the bus, the state of the multiplexers being determined by signals from control units.

摘要翻译： 数据对准逻辑单元使在多位总线中传送的数据块中的各个数据单元（例如，字节）正确对齐，使得块中的数据单元被传送到总线的期望通道。 数据对准逻辑单元包括收集单元，其将数据单元对准到总线中的固定的对齐布置，以及散射单元，其从收集单元接收数据单元并将其重新对准到期望的通道。 收集和散射单元都包含用于临时存储用于在总线的通道之间传送数据单元的某些数据单元和多路复用器的寄存器，多路复用器的状态由来自控制单元的信号确定。

公开(公告)号：US07986255B2

公开(公告)日：2011-07-26

申请号：US12625351

申请日：2009-11-24

申请人： Kevin Mahooti ,  He Bo ,  Meng Hao ,  Johnny Chuang-Li Lee ,  Rui Yang ,  Tian Jie Feng

发明人： Kevin Mahooti ,  He Bo ,  Meng Hao ,  Johnny Chuang-Li Lee ,  Rui Yang ,  Tian Jie Feng

IPC分类号： H03M1/66

CPC分类号： H03M1/069 ,  H03M1/0617 ,  H03M1/687

摘要： A controller receives an M-bit input and generates, in response, an S-bit upper range binary data feeding S-bit high range DAC and an R-bit lower range data feeding an R-bit low range DAC. The controller detects transition points in the M-bit input and in response, adds a transition data to the S-bit data equal to at least one least significant bit of the S-bit data and subtracts a value from the R-bit data equal to the transition data. The transition points and the transition data are detected and added at points avoiding such transitions at a full scale value of the R-bit data.

摘要翻译： 一个控制器接收一个M位输入，并作为响应产生一个S位上限二进制数据馈送S位高范围DAC和一个R位低范围数据，供给R位低范围DAC。 控制器检测M位输入中的转换点，并作为响应，将转换数据添加到等于S位数据的至少一个最低有效位的S位数据，并从R位数据中减去一个值 到转换数据。 在R位数据的满量程值处避免这种转换的点处检测和添加转换点和转换数据。

公开(公告)号：US5929661A

公开(公告)日：1999-07-27

申请号：US771327

申请日：1996-12-16

申请人： Johnny Chuang-Li Lee

发明人： Johnny Chuang-Li Lee

IPC分类号： H03K5/24 ,  H03K5/153 ,  H03K5/08

CPC分类号： H03K5/2481

摘要： A voltage comparator for comparing a first input voltage to a second input voltage includes a first transistor having a gate to which the first input voltage is applied and a second transistor having a gate to which the second input voltage is applied. Third and fourth transistors, coupled to the first and second transistors respectively, each conduct a first current in response to a first reference voltage being applied to a gate of each transistor. A fifth transistor is coupled to the first and second transistors and has a gate to which a second reference voltage is applied to maintain a sum of currents conducted by the first and second transistors equal to a second current. A reference generation circuit is coupled to the third, fourth and fifth transistors and is configured to generate the first and second reference voltages having magnitudes which set the second current equal to twice the first current. A first current difference amplifier has an input coupled to the first and third transistors and is configured to generate one of a first, second and third output voltage levels in response to a sourcing, zero or sinking current, respectively, being received at its input.

摘要翻译： 用于将第一输入电压与第二输入电压进行比较的电压比较器包括具有施加了第一输入电压的栅极的第一晶体管和施加有第二输入电压的栅极的第二晶体管。 响应于施加到每个晶体管的栅极的第一参考电压，分别耦合到第一和第二晶体管的第三和第四晶体管分别传导第一电流。 第五晶体管耦合到第一和第二晶体管，并且具有施加第二参考电压的栅极以保持由第一和第二晶体管传导的电流之和等于第二电流。 参考产生电路耦合到第三，第四和第五晶体管，并且被配置为产生具有将第二电流设置为等于第一电流的两倍的幅度的第一和第二参考电压。 第一电流差分放大器具有耦合到第一和第三晶体管的输入，并且被配置为响应于在其输入处接收的源，零或吸收电流而产生第一，第二和第三输出电压电平中的一个。

公开(公告)号：US5708383A

公开(公告)日：1998-01-13

申请号：US638553

申请日：1996-04-26

申请人： Johnny Chuang-Li Lee

发明人： Johnny Chuang-Li Lee

IPC分类号： H03C3/09 ,  H03D7/14 ,  H03L7/099 ,  G06F7/163 ,  H03L71/099

CPC分类号： H03C3/0983 ,  H03D7/1441 ,  H03D7/1458 ,  H03L7/0995 ,  H03D2200/0033 ,  H03D2200/0043 ,  H03D2200/0084 ,  H03D7/14

摘要： A circuit for modulating an N-phase first waveform having a frequency F.sub.O with an N-phase second waveform having a frequency F.sub.M. The circuit includes N number of limited swing driver circuits. Each limited swing driver circuit has generator means for generating one phase of a third waveform in response to one phase of the first waveform so that the third waveform has a frequency F.sub.O and a voltage swing that is less than a voltage swing of the first waveform. The circuit also includes N number of multiplier circuits. Each multiplier circuit is coupled to one of the limited swing driver circuits and has multiply means for multiplying one phase of the third waveform with one phase of the second waveform and for generating first and second currents having a difference which is proportional to a product of the one phase of the third waveform and the one phase of the second waveform. A load circuit is coupled to the multiplier circuits and has a first node into which the first currents generated by each of the multiplier circuits are summed together to form a first summation current and a second node into which the second currents generated by each of the multiplier circuits are summed together to form a second summation current. The load circuit has a comparing stage for comparing which of the first and second summation currents is larger and for generating a first clock signal having a frequency approximately equal to a frequency of a change in magnitude of the first and second summation currents. A method of modulating an N-phase first waveform having a frequency F.sub.O with an N-phase second waveform having a frequency F.sub.M is also disclosed.

摘要翻译： 一种用于调制具有频率为F的N相第一波形的电路，具有具有频率FM的N相第二波形。 该电路包括N个限制摆动驱动器电路。 每个有限的摆动驱动器电路具有用于响应于第一波形的一相产生第三波形的一相的发生器装置，使得第三波形具有小于第一波形的电压摆幅的频率FO和电压摆幅。 该电路还包括N个乘法器电路。 每个乘法器电路耦合到有限的摆动驱动器电路中的一个，并且具有乘法装置，用于将第三波形的一相与第二波形的一相相乘，并且用于产生具有与第二波形的乘积成比例的差的第一和第二电流 第三波形的一相和第二波形的一相。 负载电路耦合到乘法器电路，并且具有第一节点，由每个乘法器电路产生的第一电流相加在一起以形成第一求和电流和第二节点，由乘法器中的每一个产生的第二电流 将电路相加在一起以形成第二求和电流。 负载电路具有用于比较第一和第二求和电流中的哪一个较大的用于产生具有大致等于第一和第二求和电流的幅度变化的频率的频率的第一时钟信号的比较级。 还公开了一种利用具有频率FM的N相第二波形调制具有频率FO的N相第一波形的方法。

公开(公告)号：US20110122008A1

公开(公告)日：2011-05-26

申请号：US12625351

申请日：2009-11-24

申请人： Kevin Mahooti ,  He Bo ,  Meng Hao ,  Johnny Chuang-Li Lee ,  Rui Yang ,  Tian Jie Feng

发明人： Kevin Mahooti ,  He Bo ,  Meng Hao ,  Johnny Chuang-Li Lee ,  Rui Yang ,  Tian Jie Feng

IPC分类号： H03M1/66 ,  H03M1/00

CPC分类号： H03M1/069 ,  H03M1/0617 ,  H03M1/687

摘要： A controller receives an M-bit input and generates, in response, an S-bit upper range binary data feeding S-bit high range DAC and an R-bit lower range data feeding an R-bit low range DAC. The controller detects transition points in the M-bit input and in response, adds a transition data to the S-bit data equal to at least one least significant bit of the S-bit data and subtracts a value from the R-bit data equal to the transition data. The transition points and the transition data are detected and added at points avoiding such transitions at a full scale value of the R-bit data.

摘要翻译： 一个控制器接收一个M位输入，并作为响应产生一个S位上限二进制数据馈送S位高范围DAC和一个R位低范围数据，供给R位低范围DAC。 控制器检测M位输入中的转换点，并作为响应，将转换数据添加到等于S位数据的至少一个最低有效位的S位数据，并从R位数据中减去一个值 到转换数据。 在R位数据的满量程值处避免这种转换的点处检测和添加转换点和转换数据。