-
公开(公告)号：US20130019062A1
公开(公告)日：2013-01-17
申请号：US13546346
申请日：2012-07-11
IPC分类号： G06F12/08
CPC分类号： G06F3/0688 , G06F3/0611 , G06F3/0614 , G06F3/0659 , G06F3/0689
摘要： A memory system and a method for managing the system is described. The system is configured such a plurality of system controllers, which may be RAID controllers, receive requests from the external environment and distribute the requests to a plurality of memory modules such that data may be stored in the memory modules. A global sequence number is assigned to the data of a data stripe so that the operations related to the data stripe are performed in an ordered manner so that the data remains consistent. A plurality of system controllers may comprise a domain and access a plurality of memory controllers and a plurality of domains may include at least one common memory module.
摘要翻译： 描述了用于管理系统的存储器系统和方法。 该系统被配置为这样的多个系统控制器，其可以是RAID控制器，从外部环境接收请求并将请求分发到多个存储器模块，使得可以将数据存储在存储器模块中。 将全局序列号分配给数据条带的数据，使得与数据条带相关的操作以有序的方式执行，使得数据保持一致。 多个系统控制器可以包括域并访问多个存储器控制器，并且多个域可以包括至少一个公共存储器模块。
-
公开(公告)号：US20130042119A1
公开(公告)日：2013-02-14
申请号：US13443324
申请日：2012-04-10
申请人： Jon C.R. Bennett
发明人： Jon C.R. Bennett
IPC分类号： G06F1/00
CPC分类号： G06F13/4027 , G06F13/1684 , G06F13/4243 , G06F13/4247 , H04L49/40 , Y02D10/14 , Y02D10/151
摘要： An interconnection system, apparatus and method is described for arranging elements in a network, which may be a data memory system, computing system or communications system where the data paths are arranged and operated so as to control the power consumption and data skew properties of the system. A configurable switching element may be used to form the interconnections at nodes, where a control signal and other information is used to manage the power status of other aspects of the configurable switching element. Time delay skew of data being transmitted between nodes of the network may be altered by exchanging the logical and physical line assignments of the data at one or more nodes of the network. A method of laying out an interconnecting motherboard is disclosed which reduces the complexity of the trace routing.
摘要翻译： 描述了用于在网络中布置元件的互连系统，装置和方法，网络中的元件可以是数据存储器系统，计算系统或通信系统，其中数据路径被布置和操作，以便控制数据路径的功耗和数据偏移特性 系统。 可以使用可配置的开关元件在节点处形成互连，其中使用控制信号和其他信息来管理可配置开关元件的其他方面的电力状态。 可以通过在网络的一个或多个节点处交换数据的逻辑和物理线路分配来改变在网络节点之间传输的数据的时间延迟偏差。 公开了布置互连主板的方法，其降低了跟踪路由的复杂性。
-
公开(公告)号：US20090070612A1
公开(公告)日：2009-03-12
申请号：US12199386
申请日：2008-08-27
申请人： Maxim Adelman , Jon C.R. Bennett
发明人： Maxim Adelman , Jon C.R. Bennett
CPC分类号： G11C11/4076 , G06F1/3203 , G06F1/3225 , G06F1/3275 , G06F3/0608 , G06F3/064 , G06F3/0652 , G06F3/0688 , G06F3/0689 , G06F2212/7202 , G11C5/04 , G11C11/406 , G11C11/40611 , G11C11/4074 , G11C2211/4067 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： A memory system is described, where a plurality of memory modules is connected to a memory controller. The power status of each of the memory modules is controlled, depending on the functions being performed by the memory module. When no read or write operation is being performed on a particular memory module, at least a portion of the circuitry may be operated in a lower power mode. A memory circuit associated with the memory module may be placed in a low power mode by disabling a clock. The memory circuit data integrity may be secured by issuing refresh commands while when the memory circuit is in the lower power mode, by enabling the clock, issuing the refresh command, and disabling the clock after completion of the refresh operation.
摘要翻译： 描述了存储器系统，其中多个存储器模块连接到存储器控制器。 根据存储器模块执行的功能，控制每个存储器模块的电源状态。 当在特定存储器模块上不执行读取或写入操作时，电路的至少一部分可以在较低功率模式下操作。 与存储器模块相关联的存储器电路可以通过禁止时钟而处于低功率模式。 通过在存储器电路处于较低功率模式时通过发出刷新命令，通过使能时钟，发出刷新命令以及在完成刷新操作之后禁用时钟来保护存储器电路数据完整性。
-
公开(公告)号：US5995511A
公开(公告)日：1999-11-30
申请号：US628206
申请日：1996-04-05
CPC分类号： H04L12/5601 , H04L49/107 , H04Q11/0478 , H04L2012/5679 , H04L2012/5681
摘要： A queue control system is disclosed for use in connection with the transfer of information, in the form of information transfer units, in a digital network. The network provides a plurality of service rate classes, based on, for example transmission rates for the various paths. The information buffer control subsystem includes a information transfer unit receiver, a information transfer unit buffer and a group controller. The information transfer unit receiver receives the information transfer units, and the buffer is provided to buffer the received information transfer units prior to transmission. The group controller controls the buffering of information transfer units received by the information transfer unit receiver in the buffer. In that operation, the group controller aggregates the information transfer units for each path in the buffer according to respective service rate classes, in particular aggregating the information transfer units for each path in a queue and further aggregating the queues for the paths associated with each service rate class in a queue. A transmission scheduler is also disclosed for use in transferring information, in the form of information transfer units, each associated with a path, in a digital network. The network provides a plurality of service rate classes, based on, for example, transmission rates for the various paths. The information transfer units for each path in a path queue, and the path queues for the paths associated with each service rate class are aggregated in a service rate queue. The transmission scheduler includes a information transfer unit selector for selecting from among the service rate queues, one path queue to provide a information transfer unit for transmission, and a information transfer unit transmitter for transmitting the information transfer unit provided by the selected path queue.
-
公开(公告)号：US20120079163A1
公开(公告)日：2012-03-29
申请号：US13305373
申请日：2011-11-28
申请人： Jon C.R. Bennett
发明人： Jon C.R. Bennett
IPC分类号： G06F13/00
CPC分类号： G11C5/06 , G06F13/4243 , H03K19/17736 , H03K19/17764
摘要： An interconnection system is described where data lanes may be exchanged between lines at intervals along a transmission path so that the differential time delay between bits on a plurality of the lines is reduced when determined at a receiving location. The data lanes may be bound to the lines through the operation of a configurable switch, or by a configurable switch in conjunction with predetermined manufactured connections, or a combination of the techniques. The wiring of a connectorized node module, which may include a memory device, may be configured so that the differential time delay between pairs of input lines of a node, as measured at the output of a node, is reduced.
摘要翻译： 描述了一种互连系统，其中数据通道可以沿着传输路径间隔地在线之间交换，使得当在接收位置确定时，多条线路上的位之间的差分时间延迟减小。 数据通道可以通过可配置开关的操作或可配置开关结合预定的制造连接或这些技术的组合而被绑定到线路上。 可以配置可以包括存储器设备的连接器化节点模块的布线，使得在节点的输出处测量的节点对的输入线对之间的差分时间延迟减小。
-
-
-
-
搜索结果
5 条记录 (耗时 0.02 秒)
