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1.发明授权Error propagation limiting encoder/decoder for multilevel decision feedback equalization 失效用于多级判决反馈均衡的误差传播限制编码器/解码器
公开(公告)号：US6141783A
公开(公告)日：2000-10-31
申请号：US58509
申请日：1998-04-10
CPC分类号： H04L1/0041 , G11B20/18 , H03M13/00 , H04L1/0045 , H04L25/03057
摘要： The present invention is an encoder and decoder that eliminate all infinitely propagating error sequences for many sets of taps. The encoder includes an input circuit operable to receive an unencoded data signal and an encoding circuit, coupled to the input circuit, operable to generate the encoded data signal using a code that eliminates infinitely propagating error sequences when the encoded data signal is recovered by a decision feedback equalizer data recovery channel. The decoder includes an input circuit operable to receive an encoded data signal and a decoding table, coupled to the input circuit, operable to generate the decoded data signal using a code that eliminates infinitely propagating error sequences when the encoded data signal is recovered by a decision feedback equalizer data recovery channel.
摘要翻译： 本发明是一种编码器和解码器，其消除了许多抽头集合的所有无限传播的误差序列。 编码器包括可操作以接收未编码数据信号的输入电路和耦合到输入电路的编码电路，其可操作以使用代码消除无编传播的错误序列的编码数据信号，当编码数据信号由判定恢复时 反馈均衡器数据恢复通道。 解码器包括可操作以接收编码数据信号的输入电路和耦合到输入电路的解码表，该编码数据信号和解码表用于当编码数据信号被决定恢复时，使用消除无限传播的错误序列的代码产生解码数据信号 反馈均衡器数据恢复通道。
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公开(公告)号：US6016330A
公开(公告)日：2000-01-18
申请号：US733409
申请日：1996-10-18
CPC分类号： H04L1/0057 , H04L1/0054
摘要： The present invention is an apparatus and method for detecting a codeword from a data stream comprising a series of sequences of samples representing intensities of an analog signal. The data stream may be output from, for example, a holographic storage device. The data stream is encoded using a code which may be represented by a trellis. One embodiment of the present invention uses a block encoded balanced code, one embodiment uses a finite state encoded balanced code and another embodiment uses a finite-state encoded DC free code. Each code defines a set of codewords which meet the constraints of the code. The codewords are detected from a sequence of samples by selecting the codeword having the greatest correlation with the sequence of samples. In a preferred embodiment, the correlation detection is implemented using the Viterbi process to iteratively determine correlations and codewords for each state at each level of the trellis based on the correlations at the preceding level of the trellis.
摘要翻译： 本发明是一种用于从包含模拟信号强度的一系列样本序列的数据流中检测码字的装置和方法。 数据流可以从例如全息存储装置输出。 使用可以由网格表示的代码对数据流进行编码。 本发明的一个实施例使用块编码的平衡码，一个实施例使用有限状态编码的平衡码，另一个实施例使用有限状态编码的DC自由码。 每个代码定义满足代码约束的一组码字。 通过选择与样本序列具有最大相关性的码字，从样本序列检测码字。 在优选实施例中，使用维特比处理来实现相关检测，以基于网格的先前级别的相关性来迭代地确定网格的每个级别处的每个状态的相关性和码字。
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公开(公告)号：US5969649A
公开(公告)日：1999-10-19
申请号：US24991
申请日：1998-02-17
CPC分类号： H03M5/145
摘要： Disclosed are robust Resync patterns for insertion into a run length limited (d,k) encoded channel bit stream, which Resync pattern may be recovered from the RLL (d,k) encoded bit stream without being confused with data. The Resync pattern includes at least one string of consecutive "0"s which exceeds the RLL (k) constraint, and is inserted into the channel bit stream RLL data codewords. The RLL code excludes certain patterns representing a bit shift from the Resync pattern of one or both "1" bits adjacent to the string of "0" bits, shifted to shorten the Resync pattern to within the (k) constraint. Additionally, the Resync pattern may have two different aspects, one of which is the string of "0"s violating the constraints of the RLL code, and another which is specifically excluded from the RLL code, such as an excluded concatenated sequence of a VFO bit pattern of predetermined length or greater.
摘要翻译： 公开了用于插入到游程长度限制（d，k）编码信道比特流中的鲁棒Resync模式，该Resync模式可以从RLL（d，k）编码比特流中恢复而不与数据混淆。 重新同步模式包括至少一个超过RLL（k）约束的连续“0”字符串，并被插入到信道位流RLL数据码字中。 RLL代码排除表示与“0”比特串相邻的“1”位之一或两者的Resync模式的位移的某些模式，移位以将Resync模式缩短到（k）约束内。 另外，重新同步模式可以具有两个不同的方面，其中之一是违反RLL码的约束的“0”字符串，以及从RLL码特别排除的另一个，例如VFO的排除连接序列 预定长度或更大的位图案。
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公开(公告)号：US5907581A
公开(公告)日：1999-05-25
申请号：US722594
申请日：1996-09-27
IPC分类号： G03H1/08 , G11B7/00 , G11B7/0065 , G11B20/14 , G11C13/04 , H03M5/04 , H03M7/30 , H04N7/30 , H04B14/04
CPC分类号： G11B20/14 , H03M5/04 , H03M5/145 , G11B7/0065 , G11C13/042
摘要： A one-dimensional data stream is encoded into a two-dimensional data array with reduced high frequency components, for recording on a two-dimensional recording device, such as a holographic storage device. A two-dimensional data array read from the two-dimensional recording device is decoded into the original one-dimensional data stream. To encode, a one-dimensional data stream is partitioned into a plurality of chunks of data. Each chunk of data is partitioned into a plurality of groups of bits. Each group of bits is encoded into a two dimensional data array according to a predefined constraint. A plurality of two-dimensional data arrays are concatenated into a data strip. A plurality of data strips are then assembled into a complete two-dimensional data block. To decode, a two-dimensional data stream is partitioned into multiple small two-dimensional arrays. Each array is decoded into a multi-bit group. In one embodiment, this decoding is a function of other nearby groups. Multi-bit groups are assembled to form a long chunk. Long chunks are assembled to form a one-dimensional data stream.
摘要翻译： 一维数据流被编码成具有降低的高频分量的二维数据阵列，用于在诸如全息存储设备的二维记录装置上记录。 从二维记录装置读取的二维数据阵列被解码为原始的一维数据流。 为了编码，一维数据流被分割成多个数据块。 每个数据块被划分成多个位组。 根据预定义的约束，每组比特被编码成二维数据阵列。 多个二维数据阵列被连接成数据条。 然后将多个数据条组装成完整的二维数据块。 为了解码，二维数据流被分割成多个小的二维数组。 每个阵列被解码成多位组。 在一个实施例中，该解码是其他附近组的功能。 多位组被组合形成一个长块。 组合长块以形成一维数据流。
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公开(公告)号：US5946354A
公开(公告)日：1999-08-31
申请号：US730862
申请日：1996-10-18
IPC分类号： H04K1/10
摘要： A hard disk drive read circuit for d=1 run length limited (RLL) encoded data which processes multiple consecutive data samples in parallel. The circuit of the present invention receives an analog signal from the read head of the hard disk drive. The circuit comprises a plurality of digital detection channels, coupled to the analog signal, each channel outputting an alternate bit of digital data represented by the analog signal. A timing circuit, coupled to the plurality of digital detection channels, generates a plurality of timing signals controlling the plurality of digital detection channels. The timing circuit derives timing information from one of the digital detection channels. The d=1 RLL code is modified so that there are at most nine consecutive 0's in the digital data output by the digital detection channel from which the timing circuit derives the timing information. An encoder generates the encoded digital data to be recorded on the hard disk drive.
摘要翻译： 用于d = 1游程长度限制（RLL）编码数据的硬盘驱动器读取电路，并行处理多个连续的数据样本。 本发明的电路从硬盘驱动器的读取头接收模拟信号。 电路包括耦合到模拟信号的多个数字检测通道，每个通道输出由模拟信号表示的数字数据的交替位。 耦合到多个数字检测通道的定时电路产生控制多个数字检测通道的多个定时信号。 定时电路从数字检测通道之一获得定时信息。 修改d = 1 RLL码，使数字检测通道输出的数字数据中至少有九个连续的0，定时电路从该数字检测通道得到定时信息。 编码器生成要记录在硬盘驱动器上的编码数字数据。
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6.发明授权Method and apparatus for generating filter tap weights and biases for signal dependent branch metric computation 失效用于产生滤波器抽头权重和偏置的方法和装置，用于信号相关分支度量计算公开(公告)号：US08223827B2
公开(公告)日：2012-07-17
申请号：US10839784
申请日：2004-05-05
申请人： Jonathan James Ashley , Keenan Terrell O'Brien , Richard Rauschmayer , Sumeet Sanghvi , Anne Q. Ye , Kaichi Zhang
发明人： Jonathan James Ashley , Keenan Terrell O'Brien , Richard Rauschmayer , Sumeet Sanghvi , Anne Q. Ye , Kaichi Zhang
IPC分类号： H03K5/159
CPC分类号： H03H17/0294
摘要： A method and apparatus are provided for determining a plurality of filter tap weights or biases (or both) for a noise predictive filter used to generate one or more signal dependent branch metrics. A filter tap weight or filter bias (or both) are adaptively accumulated for each possible data condition. The data conditions may comprise, for example, each possible data pattern for a given data dependency length. The appropriate accumulated filter tap weight or bias to update can be selected based on a data condition associated with the current received data. The filter tap weights associated with a delay 0 tap can be adapted for each filter condition except for a single normalizing condition, whose corresponding delay 0 tap remains fixed.
摘要翻译： 提供了一种用于确定用于生成一个或多个信号相关分支量度的噪声预测滤波器的多个滤波器抽头权重或偏差（或两者）的方法和装置。 对于每个可能的数据条件，自适应地累积滤波器抽头权重或滤波器偏置（或两者）。 数据条件可以包括例如给定数据依赖性长度的每个可能的数据模式。 可以基于与当前接收到的数据相关联的数据条件来选择适当的累积滤波器抽头权重或要更新的偏置。 与延迟0抽头相关联的滤波器抽头权重可以适用于每个滤波器条件，除了单个归一化条件，其相应的延迟0抽头保持固定。
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7.发明授权Read channel operable to calibrate a coefficient of a filter, such as an FIR filter, disposed before an interpolated-timing-recovery circuit, and related integrated circuit, system, and method 有权用于校准布置在内插定时恢复电路之前的诸如FIR滤波器的滤波器的系数的读取通道，以及相关的集成电路，系统和方法公开(公告)号：US09171571B2
公开(公告)日：2015-10-27
申请号：US11711479
申请日：2007-02-26
CPC分类号： G11B20/10009 , G11B20/10027 , G11B20/10046 , G11B20/10222 , G11B20/10296 , G11B20/10481 , G11B20/1876
摘要： An embodiment of a read channel includes a filter, an interpolator, a recovery circuit, an error detector, a reverse interpolator, and a filter calibrator. The filter is operable to receive a raw sample of a signal and a coefficient-correction value, generate a filtered sample from the raw sample and a pre-established coefficient, and change the coefficient in response to the coefficient-correction value. The interpolator is operable to interpolate the filtered sample, and the recovery circuit is operable to generate a data symbol from the interpolated sample. The error detector is operable to generate an ideal sample from the data symbol and to generate a difference between the ideal sample and the interpolated sample, and the reverse interpolator is operable to reverse interpolate the difference. The filter calibrator is operable to receive the raw sample and to generate the coefficient-correction value from the raw sample and the reverse-interpolated difference.
摘要翻译： 读通道的实施例包括滤波器，内插器，恢复电路，误差检测器，反向内插器和滤波器校准器。 滤波器可操作以接收信号的原始样本和系数校正值，从原始样本生成滤波后的样本和预先建立的系数，并响应于系数校正值改变系数。 内插器可操作地内插经滤波的样本，并且恢复电路可操作以从内插样本生成数据符号。 误差检测器可操作以从数据符号产生理想的采样，并产生理想采样与内插采样之间的差值，并且反向内插器可操作以反向内插差值。 过滤器校准器可操作以接收原始样品并从原始样品和反向插值差产生系数校正值。
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8.发明授权Reliability unit for determining a reliability value for at least one bit decision 有权用于确定至少一个位决定的可靠性值的可靠性单元公开(公告)号：US07937649B2
公开(公告)日：2011-05-03
申请号：US12547888
申请日：2009-08-26
IPC分类号： H03M13/03
CPC分类号： H03M13/4192 , H03M13/395 , H03M13/4153
摘要： A reliability unit is provided for determining a reliability value for at least one bit decision. The disclosed reliability unit comprises one or more functional elements, wherein each of the functional elements comprises at least four functional units and at least two registers, wherein each functional unit comprises a comparator and a multiplexer, and wherein an output of the comparator and an equivalence bit control the multiplexer. Generally, the reliability unit determines a reliability value for a bit decision associated with a maximum-likelihood path through a multiple-step trellis.
摘要翻译： 提供了用于确定至少一个位决定的可靠性值的可靠性单元。 所公开的可靠性单元包括一个或多个功能元件，其中每个功能元件包括至少四个功能单元和至少两个寄存器，其中每个功能单元包括比较器和多路复用器，并且其中比较器的输出和等效 位控制多路复用器。 通常，可靠性单元确定与通过多步网格的最大似然路径相关联的位决定的可靠性值。
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公开(公告)号：US07646829B2
公开(公告)日：2010-01-12
申请号：US11021019
申请日：2004-12-23
IPC分类号： H04L27/06
CPC分类号： G11B20/10009 , H04L25/03318 , H04L25/067
摘要： A composite data detector having first and second data detectors. The second detector of the invention starts in a known state and only runs as long as is necessary before being switched off and handing control back over to the smaller detector. Therefore, the composite data detector of the invention consumes less power than the known composite data detector and estimates bits with higher accuracy.
摘要翻译： 一种具有第一和第二数据检测器的复合数据检测器。 本发明的第二检测器以已知状态开始，并且仅在被切断之前必要时运行并且将控制返回到较小检测器。 因此，本发明的复合数据检测器比已知的复合数据检测器消耗更少的功率，并且以更高的精度估计比特。
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10.发明申请Methods and Apparatus for Processing a Received Signal Using a Multiple-Step Trellis and Selection Signals for Multiple Trellis Paths 失效用于使用多步网格处理接收信号的方法和装置以及用于多个网格路径的选择信号公开(公告)号：US20090313531A1
公开(公告)日：2009-12-17
申请号：US12547841
申请日：2009-08-26
CPC分类号： H03M13/4192 , H03M13/395 , H03M13/4153
摘要： Methods and apparatus are provided for performing SOVA detection at higher data rates than achievable with conventional designs. A received signal is processed by (i) determining at least three selection signals that define a plurality of paths through a multiple-step trellis into a given state, wherein a first of the plurality of paths is a winning path for each single-step-trellis period of a multiple-step-trellis cycle, a second path is a winning path for a first single-step-trellis period and is a losing path for a second single-step-trellis period of a multiple-step-trellis cycle and a third path is a losing path for a first single-step-trellis period and is a winning path for a second single-step-trellis period of a multiple-step-trellis cycle; and (ii) determining at least one reliability value (such as a reliability value for a bit decision associated with a maximum-likelihood path through the multiple-step trellis or a plurality of reliability values for each multiple-step-trellis cycle).
摘要翻译： 提供了用于以比常规设计可实现的更高数据速率执行SOVA检测的方法和装置。 接收到的信号通过以下步骤来处理：（i）确定至少三个选择信号，其将通过多步网格的多个路径定义到给定状态，其中多条路径中的第一条路径是用于每个单步路段的获胜路径， 多步骤格雷周期的网格周期，第二路径是第一单步网格周期的获胜路径，并且是多步骤网格周期的第二单步网格周期的丢失路径，并且 第三条路径是第一个单步网格周期的失败之路，是多阶段格雷周期的第二个单步阶段的获胜路径; 和（ii）确定至少一个可靠性值（诸如与通过多步网格的最大似然路径相关联的比特决定的可靠性值或每个多步网格周期的多个可靠性值）。
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