Error propagation limiting encoder/decoder for multilevel decision
feedback equalization
    1.
    发明授权
    Error propagation limiting encoder/decoder for multilevel decision feedback equalization 失效
    用于多级判决反馈均衡的误差传播限制编码器/解码器

    公开(公告)号:US6141783A

    公开(公告)日:2000-10-31

    申请号:US58509

    申请日:1998-04-10

    摘要: The present invention is an encoder and decoder that eliminate all infinitely propagating error sequences for many sets of taps. The encoder includes an input circuit operable to receive an unencoded data signal and an encoding circuit, coupled to the input circuit, operable to generate the encoded data signal using a code that eliminates infinitely propagating error sequences when the encoded data signal is recovered by a decision feedback equalizer data recovery channel. The decoder includes an input circuit operable to receive an encoded data signal and a decoding table, coupled to the input circuit, operable to generate the decoded data signal using a code that eliminates infinitely propagating error sequences when the encoded data signal is recovered by a decision feedback equalizer data recovery channel.

    摘要翻译: 本发明是一种编码器和解码器,其消除了许多抽头集合的所有无限传播的误差序列。 编码器包括可操作以接收未编码数据信号的输入电路和耦合到输入电路的编码电路,其可操作以使用代码消除无编传播的错误序列的编码数据信号,当编码数据信号由判定恢复时 反馈均衡器数据恢复通道。 解码器包括可操作以接收编码数据信号的输入电路和耦合到输入电路的解码表,该编码数据信号和解码表用于当编码数据信号被决定恢复时,使用消除无限传播的错误序列的代码产生解码数据信号 反馈均衡器数据恢复通道。

    Hard disk drive read channel with half speed timing
    4.
    发明授权
    Hard disk drive read channel with half speed timing 失效
    硬盘驱动器读取通道半速时间

    公开(公告)号:US5946354A

    公开(公告)日:1999-08-31

    申请号:US730862

    申请日:1996-10-18

    IPC分类号: H04K1/10

    CPC分类号: G11B20/14 G11B5/09

    摘要: A hard disk drive read circuit for d=1 run length limited (RLL) encoded data which processes multiple consecutive data samples in parallel. The circuit of the present invention receives an analog signal from the read head of the hard disk drive. The circuit comprises a plurality of digital detection channels, coupled to the analog signal, each channel outputting an alternate bit of digital data represented by the analog signal. A timing circuit, coupled to the plurality of digital detection channels, generates a plurality of timing signals controlling the plurality of digital detection channels. The timing circuit derives timing information from one of the digital detection channels. The d=1 RLL code is modified so that there are at most nine consecutive 0's in the digital data output by the digital detection channel from which the timing circuit derives the timing information. An encoder generates the encoded digital data to be recorded on the hard disk drive.

    摘要翻译: 用于d = 1游程长度限制(RLL)编码数据的硬盘驱动器读取电路,并行处理多个连续的数据样本。 本发明的电路从硬盘驱动器的读取头接收模拟信号。 电路包括耦合到模拟信号的多个数字检测通道,每个通道输出由模拟信号表示的数字数据的交替位。 耦合到多个数字检测通道的定时电路产生控制多个数字检测通道的多个定时信号。 定时电路从数字检测通道之一获得定时信息。 修改d = 1 RLL码,使数字检测通道输出的数字数据中至少有九个连续的0,定时电路从该数字检测通道得到定时信息。 编码器生成要记录在硬盘驱动器上的编码数字数据。

    Encoding and detection of balanced codes
    5.
    发明授权
    Encoding and detection of balanced codes 失效
    平衡码的编码和检测

    公开(公告)号:US6016330A

    公开(公告)日:2000-01-18

    申请号:US733409

    申请日:1996-10-18

    CPC分类号: H04L1/0057 H04L1/0054

    摘要: The present invention is an apparatus and method for detecting a codeword from a data stream comprising a series of sequences of samples representing intensities of an analog signal. The data stream may be output from, for example, a holographic storage device. The data stream is encoded using a code which may be represented by a trellis. One embodiment of the present invention uses a block encoded balanced code, one embodiment uses a finite state encoded balanced code and another embodiment uses a finite-state encoded DC free code. Each code defines a set of codewords which meet the constraints of the code. The codewords are detected from a sequence of samples by selecting the codeword having the greatest correlation with the sequence of samples. In a preferred embodiment, the correlation detection is implemented using the Viterbi process to iteratively determine correlations and codewords for each state at each level of the trellis based on the correlations at the preceding level of the trellis.

    摘要翻译: 本发明是一种用于从包含模拟信号强度的一系列样本序列的数据流中检测码字的装置和方法。 数据流可以从例如全息存储装置输出。 使用可以由网格表示的代码对数据流进行编码。 本发明的一个实施例使用块编码的平衡码,一个实施例使用有限状态编码的平衡码,另一个实施例使用有限状态编码的DC自由码。 每个代码定义满足代码约束的一组码字。 通过选择与样本序列具有最大相关性的码字,从样本序列检测码字。 在优选实施例中,使用维特比处理来实现相关检测,以基于网格的先前级别的相关性来迭代地确定网格的每个级别处的每个状态的相关性和码字。

    Run length limited encoding/decoding with robust resync
    6.
    发明授权
    Run length limited encoding/decoding with robust resync 失效
    运行长度有限的编码/解码与强大的再同步

    公开(公告)号:US5969649A

    公开(公告)日:1999-10-19

    申请号:US24991

    申请日:1998-02-17

    CPC分类号: H03M5/145

    摘要: Disclosed are robust Resync patterns for insertion into a run length limited (d,k) encoded channel bit stream, which Resync pattern may be recovered from the RLL (d,k) encoded bit stream without being confused with data. The Resync pattern includes at least one string of consecutive "0"s which exceeds the RLL (k) constraint, and is inserted into the channel bit stream RLL data codewords. The RLL code excludes certain patterns representing a bit shift from the Resync pattern of one or both "1" bits adjacent to the string of "0" bits, shifted to shorten the Resync pattern to within the (k) constraint. Additionally, the Resync pattern may have two different aspects, one of which is the string of "0"s violating the constraints of the RLL code, and another which is specifically excluded from the RLL code, such as an excluded concatenated sequence of a VFO bit pattern of predetermined length or greater.

    摘要翻译: 公开了用于插入到游程长度限制(d,k)编码信道比特流中的鲁棒Resync模式,该Resync模式可以从RLL(d,k)编码比特流中恢复而不与数据混淆。 重新同步模式包括至少一个超过RLL(k)约束的连续“0”字符串,并被插入到信道位流RLL数据码字中。 RLL代码排除表示与“0”比特串相邻的“1”位之一或两者的Resync模式的位移的某些模式,移位以将Resync模式缩短到(k)约束内。 另外,重新同步模式可以具有两个不同的方面,其中之一是违反RLL码的约束的“0”字符串,以及从RLL码特别排除的另一个,例如VFO的排除连接序列 预定长度或更大的位图案。

    Two-dimensional low-pass filtering code apparatus and method
    7.
    发明授权
    Two-dimensional low-pass filtering code apparatus and method 失效
    二维低通滤波码设备及方法

    公开(公告)号:US5907581A

    公开(公告)日:1999-05-25

    申请号:US722594

    申请日:1996-09-27

    摘要: A one-dimensional data stream is encoded into a two-dimensional data array with reduced high frequency components, for recording on a two-dimensional recording device, such as a holographic storage device. A two-dimensional data array read from the two-dimensional recording device is decoded into the original one-dimensional data stream. To encode, a one-dimensional data stream is partitioned into a plurality of chunks of data. Each chunk of data is partitioned into a plurality of groups of bits. Each group of bits is encoded into a two dimensional data array according to a predefined constraint. A plurality of two-dimensional data arrays are concatenated into a data strip. A plurality of data strips are then assembled into a complete two-dimensional data block. To decode, a two-dimensional data stream is partitioned into multiple small two-dimensional arrays. Each array is decoded into a multi-bit group. In one embodiment, this decoding is a function of other nearby groups. Multi-bit groups are assembled to form a long chunk. Long chunks are assembled to form a one-dimensional data stream.

    摘要翻译: 一维数据流被编码成具有降低的高频分量的二维数据阵列,用于在诸如全息存储设备的二维记录装置上记录。 从二维记录装置读取的二维数据阵列被解码为原始的一维数据流。 为了编码,一维数据流被分割成多个数据块。 每个数据块被划分成多个位组。 根据预定义的约束,每组比特被编码成二维数据阵列。 多个二维数据阵列被连接成数据条。 然后将多个数据条组装成完整的二维数据块。 为了解码,二维数据流被分割成多个小的二维数组。 每个阵列被解码成多位组。 在一个实施例中,该解码是其他附近组的功能。 多位组被组合形成一个长块。 组合长块以形成一维数据流。

    Precompensation technique and MTR code for high data rate recording
    8.
    发明授权
    Precompensation technique and MTR code for high data rate recording 失效
    预补偿技术和高数据速率记录的地铁码

    公开(公告)号:US06768603B2

    公开(公告)日:2004-07-27

    申请号:US09799492

    申请日:2001-03-07

    IPC分类号: G11B509

    摘要: A method for write-precompensating a waveform for magnetically recording a waveform on a magnetic medium is disclosed. A user data stream is encoded into an encoded data stream so that the encoded data stream has no tribits and no consecutive dibits. No delay is applied to a first transition of a dibit of the encoded data stream. An isolated transition of the encoded data stream is delayed by a first predetermined amount of time. The second transition of a dibit of the encoded data stream is delayed by a second predetermined amount of time, such that the second predetermined amount of time is substantially twice the first predetermined amount of time. Preferably, the encoded data stream satisfies a predetermined run length limited (RLL) k− constraint of k=13 and a predetermined twins t-constraint of t=15. In one embodiment, the encoded data stream is encoded by a block code at rate 8:10. In another embodiment, the encoded data stream is encoded by a block code at rate 16:19.

    摘要翻译: 公开了一种在磁介质上磁记录波形的波形的预补偿方法。 用户数据流被编码成编码的数据流,使得编码的数据流不具有三位并且没有连续的二进制数。 对于编码数据流的二进制的第一转换,不施加延迟。 编码数据流的隔离转换被延迟第一预定时间量。 编码数据流的二进制的第二次转变被延迟第二预定时间量,使得第二预定时间量基本上是第一预定时间量的两倍。 优选地,编码数据流满足k = 13的预定游程长度限制(RLL)k约束和t = 15的预定双胞胎t约束。 在一个实施例中,编码数据流由速率8:10的块代码编码。 在另一个实施例中,编码数据流由速率16:19的块代码编码。

    System and method for constructing low complexity block coders
    9.
    发明授权
    System and method for constructing low complexity block coders 有权
    用于构建低复杂度块编码器的系统和方法

    公开(公告)号:US06430713B1

    公开(公告)日:2002-08-06

    申请号:US09345579

    申请日:1999-06-30

    IPC分类号: G06F1100

    CPC分类号: H03M5/145 G11B20/1426

    摘要: A method for designing a computer program for finding a low-complexity coder for constrained block codes for application to timing recovery or error control in data recording systems. The method includes (1) decomposing an input set of candidate codewords into simple subsets of codewords, (2) providing, for each simple subset of codewords, a respective subset of datawords, and (3) filling in certain coordinates in the datawords by values of certain coordinates in the codewords.

    摘要翻译: 一种用于设计计算机程序的方法,用于找到用于受限块代码的低复杂度编码器,以应用于数据记录系统中的定时恢复或错误控制。 该方法包括:(1)将候选码字的输入集合分解为码字的简单子集,(2)为码字的每个简单子集提供数据词的相应子集,以及(3)通过数值字填充某些坐标值 在码字中具有某些坐标。