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公开(公告)号：US20120126836A1
公开(公告)日：2012-05-24
申请号：US12951515
申请日：2010-11-22
IPC分类号： G01R27/26
CPC分类号： B81C99/003 , B81B2203/0118
摘要： A MEMS component is monitored to determine its status. Sensors are deployed to sense the MEMS component and produce detection signals that are analyzed to determine the MEMS component state. An indicator device alerts a user of the status, particularly if the MEMS component has failed. Additionally, the MEMS component monitoring system may be practiced as a design structure encoded on computer readable storage media as part of a circuit design system.
摘要翻译： 监测MEMS组件以确定其状态。 部署传感器以感测MEMS组件并产生被分析以检测MEMS组件状态的检测信号。 指示器设备向用户通知状态，特别是如果MEMS组件出现故障。 另外，作为电路设计系统的一部分，可以将MEMS部件监视系统实施为在计算机可读存储介质上编码的设计结构。
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2.发明授权公开(公告)号：US08122165B2
公开(公告)日：2012-02-21
申请号：US11954600
申请日：2007-12-12
申请人： Corey K. Barrows , Kenneth J. Goodnow , Stephen G. Shuma , Peter A. Twombly , Paul S. Zuchowski
发明人： Corey K. Barrows , Kenneth J. Goodnow , Stephen G. Shuma , Peter A. Twombly , Paul S. Zuchowski
CPC分类号： G06F1/26 , Y10T307/911
摘要： A circuit that selectively connects an integrated circuit to elements external to the integrated circuits. The circuit includes an input/output element that selectively connects an input/output pin as a function of a power requirement or a signal bandwidth requirement of the integrated circuit. The input/output element includes one or more switching devices that connect the input/output pin to an external element, such as a power supply or external signal path. The input/output element also includes one or more switching devices that connect the input/output pin to an internal element, such as a power network or internal signal line.
摘要翻译： 将集成电路选择性地连接到集成电路外部的元件的电路。 该电路包括根据功率需求或集成电路的信号带宽需求选择性地连接输入/输出引脚的输入/输出元件。 输入/输出元件包括将输入/输出引脚连接到诸如电源或外部信号路径的外部元件的一个或多个开关器件。 输入/输出元件还包括将输入/输出引脚连接到诸如电力网络或内部信号线的内部元件的一个或多个开关器件。
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公开(公告)号：US20090249091A1
公开(公告)日：2009-10-01
申请号：US12056308
申请日：2008-03-27
IPC分类号： G06F1/00
CPC分类号： G06F1/263
摘要： The invention generally relates to the utilization of electric power, and more particularly to systems and methods for selectively utilizing secondary power sources during peak power times. A method includes receiving a notification of a peak power time, and discontinuing use of a primary power supply and beginning use of a secondary power supply based upon the notification.
摘要翻译： 本发明一般涉及电力的利用，更具体地涉及用于在峰值功率时间期间选择性地利用次级电源的系统和方法。 一种方法包括接收峰值功率时间的通知，以及基于该通知中断主电源的使用并开始使用次级电源。
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4.发明申请公开(公告)号：US20090152594A1
公开(公告)日：2009-06-18
申请号：US11954600
申请日：2007-12-12
申请人： Corey K. Barrows , Kenneth J. Goodnow , Stephen G. Shuma , Peter A. Twombly , Paul S. Zuchowski
发明人： Corey K. Barrows , Kenneth J. Goodnow , Stephen G. Shuma , Peter A. Twombly , Paul S. Zuchowski
IPC分类号： H01L27/10
CPC分类号： G06F1/26 , Y10T307/911
摘要： A circuit that selectively connects an integrated circuit to elements external to the integrated circuits. The circuit includes an input/output element that selectively connects an input/output pin as a function of a power requirement or a signal bandwidth requirement of the integrated circuit. The input/output element includes one or more switching devices that connect the input/output pin to an external element, such as a power supply or external signal path. The input/output element also includes one or more switching devices that connect the input/output pin to an internal element, such as a power network or internal signal line.
摘要翻译： 将集成电路选择性地连接到集成电路外部的元件的电路。 该电路包括根据功率需求或集成电路的信号带宽需求选择性地连接输入/输出引脚的输入/输出元件。 输入/输出元件包括将输入/输出引脚连接到诸如电源或外部信号路径的外部元件的一个或多个开关器件。 输入/输出元件还包括将输入/输出引脚连接到诸如电力网络或内部信号线的内部元件的一个或多个开关器件。
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公开(公告)号：US20090058457A1
公开(公告)日：2009-03-05
申请号：US11848278
申请日：2007-08-31
IPC分类号： H03K19/003 , G06F17/50 , H01L21/66
CPC分类号： G06F17/505
摘要： Method, system, IC and design structure for meeting a performance requirement using redundant critical path circuits, are disclosed. In one embodiment, the IC includes a plurality of redundant critical path circuits, wherein at least one of the plurality of redundant critical path circuits meeting a performance requirement is operational and the others are non-operational.
摘要翻译： 公开了使用冗余关键路径电路满足性能要求的方法，系统，IC和设计结构。 在一个实施例中，IC包括多个冗余关键路径电路，其中满足性能要求的多个冗余关键路径电路中的至少一个是可操作的，而其他冗余关键路径电路是不可操作的。
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公开(公告)号：US20120324255A1
公开(公告)日：2012-12-20
申请号：US13593837
申请日：2012-08-24
CPC分类号： G06F1/263
摘要： Systems and methods for selectively utilizing secondary power sources during peak power times are provided for. The method includes receiving a notification of a peak power time, and discontinuing use of a primary power supply and beginning use of a secondary power supply based upon the notification.
摘要翻译： 提供了用于在峰值功率时间期间选择性地利用次级电源的系统和方法。 该方法包括接收峰值功率时间的通知，以及停止使用主电源并基于该通知开始使用次级电源。
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公开(公告)号：US08301921B2
公开(公告)日：2012-10-30
申请号：US12056308
申请日：2008-03-27
CPC分类号： G06F1/263
摘要： The invention generally relates to the utilization of electric power, and more particularly to systems and methods for selectively utilizing secondary power sources during peak power times. A method includes receiving a notification of a peak power time, and discontinuing use of a primary power supply and beginning use of a secondary power supply based upon the notification.
摘要翻译： 本发明一般涉及电力的利用，更具体地涉及用于在峰值功率时间期间选择性地利用次级电源的系统和方法。 一种方法包括接收峰值功率时间的通知，以及基于该通知中断主电源的使用并开始使用次级电源。
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8.发明申请SWITCH TO PERFORM NON-DESTRUCTIVE AND SECURE DISABLEMENT OF IC FUNCTIONALITY UTILIZING MEMS AND METHOD THEREOF 有权切换实现使用MEMS的IC功能的非破坏性和安全性的失效及其方法公开(公告)号：US20120146684A1
公开(公告)日：2012-06-14
申请号：US12964764
申请日：2010-12-10
IPC分类号： H03K19/00
CPC分类号： G06F21/87
摘要： Structures and methods are provided for performing non-destructive and secure disablement of integrated circuit (IC) functionality. A structure for enabling non-destructive and secure disablement and re-enablement of the IC includes a micro-electrical mechanical structure (MEMS) initially set to a chip enable state. The structure also includes an activation circuit operable to set the MEMS device to an error state based on a detected predetermined condition of the IC. The IC is disabled when the MEMS device is in the error state.
摘要翻译： 提供了用于执行集成电路（IC）功能的非破坏性和安全性的禁用的结构和方法。 用于实现IC的非破坏性和安全的禁用和重新启用的结构包括初始设置为芯片使能状态的微电机械结构（MEMS）。 该结构还包括激活电路，其可操作以基于检测到的IC的预定条件将MEMS器件设置为错误状态。 当MEMS器件处于错误状态时，IC被禁止。
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9.发明授权Mechanism for detection and compensation of NBTI induced threshold degradation 有权NBTI诱发阈值降解的检测和补偿机制公开(公告)号：US07849426B2
公开(公告)日：2010-12-07
申请号：US11931144
申请日：2007-10-31
申请人： Kenneth J. Goodnow , Douglas W. Kemerer , Stephen G. Shuma , Oscar C. Strohacker , Mark S. Styduhar , Peter A. Twombly , Paul S. Zuchowski
发明人： Kenneth J. Goodnow , Douglas W. Kemerer , Stephen G. Shuma , Oscar C. Strohacker , Mark S. Styduhar , Peter A. Twombly , Paul S. Zuchowski
CPC分类号： G06F17/5063
摘要： The embodiments of the invention provide a design structure for detection and compensation of negative bias temperature instability (NBTI) induced threshold degradation. A semiconductor device is provided comprising at least one stress device having a voltage applied to its gate node and at least one reference device having a zero gate-to-source voltage. A controller is also provided to configure node voltages of the device and/or the reference device to reflect different regions of device operations found in digital and analog circuit applications. Moreover, the controller measures a difference in current between the stress device and the reference device to determine whether NBTI induced threshold degradation has occurred in the stress device. The controller also adjusts an output power supply voltage of the stress device until a performance of the stress device matches a performance of the reference device to account for the NBTI induced threshold degradation.
摘要翻译： 本发明的实施例提供了用于检测和补偿负偏压温度不稳定性（NBTI）诱导的阈值劣化的设计结构。 提供一种半导体器件，其包括至少一个应力器件，其具有施加到其栅极节点的电压和至少一个具有零栅极至源极电压的参考器件。 还提供控制器来配置设备和/或参考设备的节点电压以反映在数字和模拟电路应用中发现的设备操作的不同区域。 此外，控制器测量应力装置和参考装置之间的电流差，以确定在应力装置中是否发生了NBTI诱导的阈值劣化。 控制器还调整应力装置的输出电源电压，直到应力装置的性能与参考装置的性能匹配以解决NBTI诱发的阈值劣化。
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公开(公告)号：US07716615B2
公开(公告)日：2010-05-11
申请号：US11848278
申请日：2007-08-31
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Method, system, IC and design structure for meeting a performance requirement using redundant critical path circuits, are disclosed. In one embodiment, the IC includes a plurality of redundant critical path circuits, wherein at least one of the plurality of redundant critical path circuits meeting a performance requirement is operational and the others are non-operational.
摘要翻译： 公开了使用冗余关键路径电路满足性能要求的方法，系统，IC和设计结构。 在一个实施例中，IC包括多个冗余关键路径电路，其中满足性能要求的多个冗余关键路径电路中的至少一个是可操作的，而其他冗余关键路径电路是不可操作的。
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