公开(公告)号：US20090200652A1

公开(公告)日：2009-08-13

申请号：US12028542

申请日：2008-02-08

申请人： Jong Hoon Oh ,  Klaus Hummler ,  Oliver Kiehl ,  Josef Schnell ,  Wayne Frederick Ellis ,  Jung Pil Kim ,  Lee Ward Collins ,  Octavian Beldiman

发明人： Jong Hoon Oh ,  Klaus Hummler ,  Oliver Kiehl ,  Josef Schnell ,  Wayne Frederick Ellis ,  Jung Pil Kim ,  Lee Ward Collins ,  Octavian Beldiman

IPC分类号： H01L23/498 ,  H01L21/58

CPC分类号： H01L25/0657 ,  H01L25/03 ,  H01L25/18 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2224/05599

摘要： A multi-chip package is provided that has at least a first, second and third chip, each comprising a top and bottom surface. The multi-chip package also has a package substrate for interfacing with a printed circuit board (PCB). The chips and the package substrate are housed within an encapsulation material. The bottom surface of the first chip is attached to the package substrate. The top surface of the first chip has a first plurality of landing pads, which serve as a mechanical and electrical interface between the first and second chip. The bottom surface of the second chip has a second plurality of landing pads that serve as a mechanical and electrical interface between the second and first chip. Additionally, the top surface of the second chip has a third plurality of landing pads that serve as a mechanical and electrical interface between the second and third chip.

摘要翻译： 提供了具有至少第一，第二和第三芯片的多芯片封装，每个芯片包括顶部和底部表面。 多芯片封装还具有用于与印刷电路板（PCB）连接的封装基板。 芯片和封装衬底容纳在封装材料内。 第一芯片的底表面附接到封装衬底。 第一芯片的顶表面具有第一多个着陆焊盘，其用作第一和第二芯片之间的机械和电接口。 第二芯片的底表面具有用作第二芯片和第一芯片之间的机械和电接口的第二多个着陆焊盘。 此外，第二芯片的顶表面具有用作第二和第三芯片之间的机械和电接口的第三多个着陆焊盘。

公开(公告)号：US08138610B2

公开(公告)日：2012-03-20

申请号：US12028542

申请日：2008-02-08

申请人： Jong Hoon Oh ,  Klaus Hummler ,  Oliver Kiehl ,  Josef Schnell ,  Wayne Frederick Ellis ,  Jung Pil Kim ,  Lee Ward Collins ,  Octavian Beldiman

发明人： Jong Hoon Oh ,  Klaus Hummler ,  Oliver Kiehl ,  Josef Schnell ,  Wayne Frederick Ellis ,  Jung Pil Kim ,  Lee Ward Collins ,  Octavian Beldiman

IPC分类号： H01L23/48

CPC分类号： H01L25/0657 ,  H01L25/03 ,  H01L25/18 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2224/05599

摘要： A multi-chip package is provided that has at least a first, second and third chip, each comprising a top and bottom surface. The multi-chip package also has a package substrate for interfacing with a printed circuit board (PCB). The chips and the package substrate are housed within an encapsulation material. The bottom surface of the first chip is attached to the package substrate. The top surface of the first chip has a first plurality of landing pads, which serve as a mechanical and electrical interface between the first and second chip. The bottom surface of the second chip has a second plurality of landing pads that serve as a mechanical and electrical interface between the second and first chip. Additionally, the top surface of the second chip has a third plurality of landing pads that serve as a mechanical and electrical interface between the second and third chip.

摘要翻译： 提供了具有至少第一，第二和第三芯片的多芯片封装，每个芯片包括顶部和底部表面。 多芯片封装还具有用于与印刷电路板（PCB）连接的封装基板。 芯片和封装衬底容纳在封装材料内。 第一芯片的底表面附接到封装衬底。 第一芯片的顶表面具有第一多个着陆焊盘，其用作第一和第二芯片之间的机械和电接口。 第二芯片的底表面具有用作第二芯片和第一芯片之间的机械和电接口的第二多个着陆焊盘。 此外，第二芯片的顶表面具有用作第二和第三芯片之间的机械和电接口的第三多个着陆焊盘。

公开(公告)号：US5767583A

公开(公告)日：1998-06-16

申请号：US906005

申请日：1997-08-04

申请人： Jae Jin Lee ,  Jung Pil Kim

发明人： Jae Jin Lee ,  Jung Pil Kim

IPC分类号： G11C5/00 ,  G11C5/14 ,  H01L23/50 ,  H01L23/48

CPC分类号： H01L23/50 ,  H01L24/06 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/30105

摘要： A semiconductor device including outer pins including power pins adapted to supply a source voltage or a ground voltage, data pins adapted to input and output data and classified into a plurality of data pin groups having the same number of data pins, and output voltage pins adapted to supply output voltages of data pins of the data pin groups respectively associated therewith, wherein each of the output voltage pins is arranged between a pair of sub-groups constituting one of the data pin groups associated therewith, thereby capable of minimizing a resistance generated between each output voltage pin and each of data pins driven by the output voltage pin and achieving an improvement in data output characteristic.

摘要翻译： 一种半导体器件，包括外部引脚，其包括适于提供源极电压或接地电压的电源引脚，适于输入和输出数据并分类为具有相同数量引脚数量的多个数据引脚组的数据引脚和适配的输出电压引脚 以提供与其分别相关联的数据引脚组的数据引脚的输出电压，其中每个输出电压引脚布置在构成与其相关联的数据引脚组之一的一对子组之间，从而能够最小化在 每个输出电压引脚和每个数据引脚由输出电压引脚驱动，并实现数据输出特性的提高。