公开(公告)号：US20100162074A1

公开(公告)日：2010-06-24

申请号：US12642463

申请日：2009-12-18

申请人： Jong-Ee OH ,  Minho CHEONG ,  Yu-Ro LEE ,  Sok-Kyu LEE ,  Yongho LEE

发明人： Jong-Ee OH ,  Minho CHEONG ,  Yu-Ro LEE ,  Sok-Kyu LEE ,  Yongho LEE

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： H03M13/116 ,  H03M13/6527 ,  H03M13/6544 ,  H04L1/0041 ,  H04L1/0057

摘要： A high-speed quasi-cyclic low density parity check (QC-LDPC) coding apparatus for coding inputted information into a generator matrix having a dual diagonal matrix format includes: a parity bit generation unit configured to generate an arbitrary parity bit; a temporary parity bit generation unit configured to constitute the inputted information with circulants, and shift and combine the respective circulants at each row to generate a temporary parity bit; a corrected bit generation unit configured to generate corrected bits of parity bits by using an output of the temporary parity bit generation unit; and a parity bit correction unit configured to correct the temporary parity bit by reflecting an output of the corrected bit generation unit to the output of the temporary parity bit generation unit.

摘要翻译： 用于将输入的信息编码成具有双对角矩阵格式的生成矩阵的高速准循环低密度奇偶校验（QC-LDPC）编码装置包括：奇偶校验位生成单元，被配置为生成任意奇偶校验位; 临时奇偶校验位生成单元，被配置为构成具有循环的输入信息，并且移位并组合各行的各个循环以产生临时奇偶校验位; 校正位生成单元，其通过使用所述临时奇偶校验位生成单元的输出来生成校正位的校验位; 以及奇偶校验位校正单元，被配置为通过将校正的位生成单元的输出反映到临时奇偶校验位产生单元的输出来校正临时奇偶校验位。

公开(公告)号：US20090154604A1

公开(公告)日：2009-06-18

申请号：US12178150

申请日：2008-07-23

申请人： Yu-Ro LEE ,  Jong-Ee OH ,  Minho CHEONG ,  Sok-Kyu LEE

发明人： Yu-Ro LEE ,  Jong-Ee OH ,  Minho CHEONG ,  Sok-Kyu LEE

IPC分类号： H04L27/06

CPC分类号： H04L27/2647 ,  H04B7/0413 ,  H04L25/061 ,  H04L25/067

摘要： Provided are a multi-dimensional detector for a receiver of an MIMO system and a method thereof. The multi-dimensional detector includes a first symbol detecting unit for calculating symbol distance values using an upper triangular matrix (R) obtained from QR decomposition to detect an mth symbol; a symbol deciding unit for deciding a symbol having a minimum distance value among the calculated symbol distance values from the first symbol detecting unit; and a second symbol detecting unit for calculating symbol distance values using an updated received signal y and the upper triangular matrix R to detect a (m−1)th symbol.

摘要翻译： 提供了一种用于MIMO系统的接收机的多维检测器及其方法。 多维检测器包括：第一符号检测单元，用于使用从QR分解获得的上三角矩阵（R）来计算符号距离值以检测第m个符号; 符号判定单元，用于从所述第一符号检测单元确定所计算的符号距离值中具有最小距离值的符号; 以及第二符号检测单元，用于使用更新的接收信号y和上三角矩阵R来计算符号距离值以检测第（m-1）个符号。

公开(公告)号：US20090154587A1

公开(公告)日：2009-06-18

申请号：US12238082

申请日：2008-09-25

申请人： Minho CHEONG ,  Yu-Ro LEE ,  Jong -Ee OH ,  Sok-Kyu LEE

发明人： Minho CHEONG ,  Yu-Ro LEE ,  Jong -Ee OH ,  Sok-Kyu LEE

IPC分类号： H04L1/02 ,  H04B7/02 ,  H04B1/10

CPC分类号： H04B7/0417 ,  H04L1/0631

摘要： Provided is a reception apparatus and method of a Multiple Input Multiple Output (MIMO) system that receives a plurality of different data streams in a multiple cell environment. The reception apparatus for receiving a plurality of different data streams in a multiple input multiple output (MIMO) antenna system includes a data stream detector for detecting each data stream by removing interference between the different data streams while maintaining channel information; and a cochannel interference (CCI) remover for removing cochannel interference from each data stream detected in the data stream detector. The present invention can remove cochannel interference and increase channel capacity to thereby acquire both diversity gain and multiplexing gain.

摘要翻译： 提供了一种在多小区环境中接收多个不同数据流的多输入多输出（MIMO）系统的接收装置和方法。 用于在多输入多输出（MIMO）天线系统中接收多个不同数据流的接收装置包括：数据流检测器，用于通过在保持信道信息的同时消除不同数据流之间的干扰来检测每个数据流; 以及用于从数据流检测器中检测到的每个数据流去除同信道干扰的同信道干扰（CCI）去除器。 本发明可以消除同信道干扰并增加信道容量，从而获得分集增益和复用增益。

公开(公告)号：US20090158112A1

公开(公告)日：2009-06-18

申请号：US12113638

申请日：2008-05-01

申请人： Jong-Ee OH ,  Chanho YOON ,  Minho CHEONG ,  Sok-Kyu LEE

发明人： Jong-Ee OH ,  Chanho YOON ,  Minho CHEONG ,  Sok-Kyu LEE

IPC分类号： H03M13/11 ,  G06F11/10

CPC分类号： H03M13/116 ,  H03M13/1185 ,  H03M13/611

摘要： Provided are a method for producing a parity check matrix for low complexity and high speed decoding, and an apparatus and method for coding a Low Density Parity Check (LDPC) code using the same. The method includes: calculating a cyclic shift value of a subblock to a matrix; and when the calculated cyclic shift values of the subblock are arrayed in the matrix, producing a parity check matrix by arraying the cyclic shift values of the subblock except ‘0 matrix’ without duplication to any one column.

摘要翻译： 提供了一种用于产生用于低复杂度和高速解码的奇偶校验矩阵的方法，以及用于使用其编码低密度奇偶校验（LDPC）码的装置和方法。 该方法包括：将子块的循环移位值计算到矩阵; 并且当将所计算的子块的循环移位值排列在矩阵中时，通过将除“0矩阵”之外的子块的循环移位值排列成任何一列，从而产生奇偶校验矩阵。

公开(公告)号：US20090164540A1

公开(公告)日：2009-06-25

申请号：US12146195

申请日：2008-06-25

申请人： Jong-Ee OH ,  Minho CHEONG ,  Il-Gu LEE ,  Sok-Kyu LEE

发明人： Jong-Ee OH ,  Minho CHEONG ,  Il-Gu LEE ,  Sok-Kyu LEE

IPC分类号： G06F7/38

CPC分类号： H03M13/1134 ,  H03M13/112 ,  H03M13/1122 ,  H03M13/618 ,  H03M13/6362 ,  H03M13/658 ,  H03M13/6583

摘要： Provided is an apparatus and method for updating a check node of a LDPC code at a high speed. The apparatus includes: a minimum value calculating unit for calculating a first minimum value of an input bit by sequentially calculating each bit of the first minimum value, and calculating a second minimum value using the calculated first minimum value; a node minimum value calculating unit for performing row splitting the calculated first and second minimum values by a check node and calculating a first minimum value and a second minimum value of each of the row-split nodes; and a minimum value deciding unit for deciding one of the calculated first and second minimum values of each of the row-split nodes as a minimum value corresponding to each degree of the input bit.

摘要翻译： 提供了一种用于以高速更新LDPC码的校验节点的装置和方法。 该装置包括：最小值计算单元，用于通过顺序地计算第一最小值的每个位，并使用所计算的第一最小值来计算第二最小值来计算输入比特的第一最小值; 节点最小值计算单元，用于通过校验节点执行行分解所计算的第一和第二最小值，并计算每个行分割节点的第一最小值和第二最小值; 以及最小值确定单元，用于将每个行分割节点的所计算的第一和第二最小值中的一个确定为与每个输入比特的度相对应的最小值。

公开(公告)号：US20110206156A1

公开(公告)日：2011-08-25

申请号：US13033202

申请日：2011-02-23

申请人： Il-Gu LEE ,  In-Kyeong CHOI ,  Yu-Ro LEE ,  Jong-Ee OH ,  Eun-Young CHOI ,  Sok-Kyu LEE

发明人： Il-Gu LEE ,  In-Kyeong CHOI ,  Yu-Ro LEE ,  Jong-Ee OH ,  Eun-Young CHOI ,  Sok-Kyu LEE

IPC分类号： H04L27/18

CPC分类号： H04L27/18 ,  H04L27/0008

摘要： A method for transmitting, by a transmitting terminal, data to a receiving terminal in a wireless communication system includes: generating a first detection field including symbols modulated by using a BPSK data tone; generating a second detection field including symbols modulated such that an even numbered subcarrier and an odd numbered subcarrier have a phase difference of 90 degrees; generating a data packet including the first detection field, the second detection field, and the data; and transmitting the data packet.

摘要翻译： 一种在无线通信系统中由发送终端向接收终端发送数据的方法包括：生成包括通过使用BPSK数据音调调制的符号的第一检测字段; 产生包括被调制的符号的第二检测场，使得偶数副载波和奇数副载波具有90度的相位差; 生成包括第一检测区域，第二检测区域和数据的数据分组; 并发送数据包。

公开(公告)号：US20090161808A1

公开(公告)日：2009-06-25

申请号：US12274056

申请日：2008-11-19

申请人： Minho CHEONG ,  Yu-Ro LEE ,  Sok-Kyu LEE ,  Il-Gu LEE

发明人： Minho CHEONG ,  Yu-Ro LEE ,  Sok-Kyu LEE ,  Il-Gu LEE

IPC分类号： H04L7/00

CPC分类号： H04W56/0035 ,  H04L7/042

摘要： Provided is an apparatus and method for detecting reception signal symbol synchronization in a wireless communication system. The method, includes: calculating a channel power value in each of multiple antennas; selecting and averaging at least 2 channel power values; compensating carrier frequency offset for an average value; and determining a symbol boundary of a reception signal according to the size of the average value compensating the carrier frequency offset.

摘要翻译： 提供一种用于在无线通信系统中检测接收信号符号同步的装置和方法。 该方法包括：计算多个天线中每个天线的信道功率值; 选择和平均至少2个通道功率值; 补偿平均值的载波频率偏移; 以及根据补偿载波频率偏移的平均值的大小来确定接收信号的符号边界。

公开(公告)号：US20090154579A1

公开(公告)日：2009-06-18

申请号：US12139904

申请日：2008-06-16

申请人： Yu-Ro LEE ,  Jung-Bo SON ,  Minho CHEONG ,  Sok-Kyu LEE

发明人： Yu-Ro LEE ,  Jung-Bo SON ,  Minho CHEONG ,  Sok-Kyu LEE

IPC分类号： H04L27/28 ,  G06F17/16

CPC分类号： H04B7/0413 ,  H04B7/0854 ,  H04L27/2601

摘要： Provided is a QR decomposition apparatus and method that can reduce the number of computers by sharing hardware in an MIMO system employing OFDM technology to simplify a structure of hardware. The QR decomposition apparatus includes a norm multiplier for calculating a norm; a Q column multiplier for calculating a column value of a unitary Q matrix to thereby produce a Q matrix vector; a first storage for storing the Q matrix vector calculated in the Q column multiplier; an R row multiplier for calculating a value of an upper triangular R matrix by multiplying the Q matrix vector by a reception signal vector; and a Q update multiplier for receiving the reception signal vector and an output of the R row multiplier, calculating an Q update value through an accumulation operation, and providing the Q update value to the Q column multiplier to calculate a next Q matrix vector.

摘要翻译： 提供了一种QR分解装置和方法，其可以通过在采用OFDM技术的MIMO系统中共享硬件来减少计算机的数量，以简化硬件的结构。 QR分解装置包括用于计算范数的标准倍数; Q列乘法器，用于计算酉矩阵的列值，从而产生Q矩阵向量; 用于存储在Q列乘法器中计算出的Q矩阵向量的第一存储器; R行乘法器，用于通过将Q矩阵向量乘以接收信号向量来计算上三角形R矩阵的值; 以及Q更新乘法器，用于接收接收信号矢量和R行乘法器的输出，通过累加操作计算Q更新值，并将Q更新值提供给Q列乘法器以计算下一个Q矩阵向量。

公开(公告)号：US20090154334A1

公开(公告)日：2009-06-18

申请号：US12131617

申请日：2008-06-02

申请人： Yu-Ro LEE ,  Byung-Chan KIM ,  Minho CHEONG ,  Chanho YOON ,  Je-Hun LEE ,  Kwhang-Hyun RYU ,  Cheol-Jung KIM ,  Tae-Hyun JEON ,  Sok-Kyu LEE

发明人： Yu-Ro LEE ,  Byung-Chan KIM ,  Minho CHEONG ,  Chanho YOON ,  Je-Hun LEE ,  Kwhang-Hyun RYU ,  Cheol-Jung KIM ,  Tae-Hyun JEON ,  Sok-Kyu LEE

IPC分类号： H04J11/00

CPC分类号： H04L25/0246 ,  H04L25/03006 ,  H04L2025/03414 ,  H04L2025/03426

摘要： Provided are a QR decomposition apparatus and method for a MIMO system. The QR decomposition apparatus includes: a norm calculator for calculating a vector size norm for a channel input; a Q column calculator for calculating a column value of a unitary matrix Q by multiplying a delayed channel input with √{square root over (norm)}; an R row calculator for receiving the delayed channel input, the output of the Q column calculator, and 1/√{square root over (norm)}, and calculating a row value of an upper triangular matrix R; a Q update calculator for receiving the delayed channel input, the output of the R row calculator, and a delayed output of the Q column calculator, and calculating a Q update matrix value; and a norm update calculator for receiving a delayed output of the norm calculator and an output of the R row calculator, and outputting a norm update matrix value.

摘要翻译： 提供了一种用于MIMO系统的QR分解装置和方法。 QR分解装置包括：用于计算信道输入的矢量大小范数的范数计算器; Q列计算器，用于通过将延迟的信道输入与{平方根超过（norm）}相乘来计算酉矩阵Q的列值; 用于接收延迟信道输入的R行计算器，Q列计算器的输出和1 /√{平方根超过（norm）}，并计算上三角矩阵R的行值; 用于接收延迟信道输入，R行计算器的输出和Q列计算器的延迟输出的Q更新计算器，并计算Q更新矩阵值; 以及范数更新计算器，用于接收范数计算器的延迟输出和R行计算器的输出，并输出范数更新矩阵值。

公开(公告)号：US20090158121A1

公开(公告)日：2009-06-18

申请号：US12166866

申请日：2008-07-02

申请人： Jong-Ee OH ,  Chanho YOON ,  Cheol-Hui RYU ,  Eun-Young CHOI ,  Sok-Kyu LEE

发明人： Jong-Ee OH ,  Chanho YOON ,  Cheol-Hui RYU ,  Eun-Young CHOI ,  Sok-Kyu LEE

IPC分类号： H03M13/05 ,  G06F11/07

CPC分类号： H03M13/116 ,  H03M13/1137 ,  H03M13/1185 ,  H03M13/1188 ,  H03M13/6516

摘要： Provided is an apparatus and method for decoding a Low Density Parity Check (LDPC) code based on prototype parity check matrixes. The apparatus, includes: a parity check matrix selecting means for determining multiple prototype parity check matrixes according to a sub-matrix size and a parallelization figure for processing the parity check matrix; a bit input means for receiving a log likelihood probability value for input bit according to the sub-matrix size and the parallelization figure; a check matrix process means for sequentially performing a partial parallel process on the parity check matrix based on the received log likelihood probability value and the determined multiple prototype parity check matrixes; and a bit process means for determining a bit level based on the partial-parallel processed parity check matrix value and recovering the input bit according to the sub-matrix size and the parallelization figure.

摘要翻译： 提供了一种基于原型奇偶校验矩阵对低密度奇偶校验（LDPC）码进行解码的装置和方法。 该装置包括：奇偶校验矩阵选择装置，用于根据子矩阵大小确定多个原型奇偶校验矩阵;以及用于处理奇偶校验矩阵的并行化图; 用于根据子矩阵大小和并行化图形接收输入比特的对数似然概率值的位输入装置; 校验矩阵处理装置，用于基于所接收的对数似然概率值和所确定的多原型奇偶校验矩阵，顺序对奇偶校验矩阵执行部分并行处理; 以及位处理装置，用于基于部分并行处理的奇偶校验矩阵值确定位电平，并根据子矩阵大小和并行化图形恢复输入位。