公开(公告)号：US09378672B2

公开(公告)日：2016-06-28

申请号：US13732659

申请日：2013-01-02

申请人： Jong-Ho Chong ,  Seung-Bae Lee ,  Hun-Jung Lee ,  Su-Young Kim ,  Hye-Ryoung Park

发明人： Jong-Ho Chong ,  Seung-Bae Lee ,  Hun-Jung Lee ,  Su-Young Kim ,  Hye-Ryoung Park

IPC分类号： G09G5/00 ,  G09G3/32 ,  G09G3/00

CPC分类号： G09G3/3208 ,  G09G3/003 ,  G09G3/3233 ,  G09G2310/061

摘要： An organic light emitting display device includes pixels at intersection regions of scan and data lines, a scan driver configured to supply a scan signal to the scan lines, a data driver configured to supply a data signal to the data lines, and a timing controller configured to receive from outside frame data including left and right image data, and to insert first blank periods into initial and latter periods of a same frame, the left and right image data being between the initial and latter periods of the same frame.

摘要翻译： 有机发光显示装置包括扫描线和数据线的交叉区域的像素，被配置为向扫描线提供扫描信号的扫描驱动器，被配置为向数据线提供数据信号的数据驱动器，以及定时控制器， 从包括左图像数据和右图像数据的外部帧数据接收，并且将第一空白周期插入同一帧的初始和后一周期，左和右图像数据在相同帧的初始和后期周期之间。

公开(公告)号：US08345039B2

公开(公告)日：2013-01-01

申请号：US12585966

申请日：2009-09-29

申请人： Sang-Moo Choi ,  Hun-Jung Lee ,  Su-Young Kim ,  Dong-Wook Choi

发明人： Sang-Moo Choi ,  Hun-Jung Lee ,  Su-Young Kim ,  Dong-Wook Choi

IPC分类号： G09G5/00 ,  G09G3/30

CPC分类号： G09G3/3233 ,  G09G2300/0819 ,  G09G2300/0852 ,  G09G2300/0861 ,  G09G2320/043

摘要： An organic light emitting display device capable of driving transistor threshold voltage compensation, including: pixels positioned in the intersections of scan lines and data lines, wherein each pixel comprises: a first transistor and a fourth transistor, connected at a common node, disposed between an anode of an OLED and a first power supply; a cathode of the OLED connected to a second power supply; a second transistor connected between a gate of the first transistor and a data line, and turned on when a scan signal is supplied to a scan line; a third transistor connected between the common node and the data line, and turned on when a scan signal is supplied to the scan line; a first capacitor connected between the gate of the first transistor and the anode of the OLED; and a second capacitor connected between the anode of the OLED and a predetermined voltage source.

摘要翻译： 一种能够驱动晶体管阈值电压补偿的有机发光显示装置，包括：位于扫描线和数据线的交点中的像素，其中每个像素包括：第一晶体管和第四晶体管，连接在公共节点处， OLED的阳极和第一电源; 连接到第二电源的OLED的阴极; 连接在第一晶体管的栅极和数据线之间的第二晶体管，当扫描信号被提供给扫描线时导通; 连接在公共节点和数据线之间的第三晶体管，当扫描信号被提供给扫描线时导通; 连接在第一晶体管的栅极和OLED的阳极之间的第一电容器; 以及连接在OLED的阳极和预定电压源之间的第二电容器。

公开(公告)号：US20100141645A1

公开(公告)日：2010-06-10

申请号：US12585966

申请日：2009-09-29

申请人： Sang-Moo Choi ,  Hun-Jung Lee ,  Su-Young Kim ,  Dong-Wook Choi

发明人： Sang-Moo Choi ,  Hun-Jung Lee ,  Su-Young Kim ,  Dong-Wook Choi

IPC分类号： G09G5/00 ,  G09G3/30

CPC分类号： G09G3/3233 ,  G09G2300/0819 ,  G09G2300/0852 ,  G09G2300/0861 ,  G09G2320/043

摘要： An organic light emitting display device capable of driving transistor threshold voltage compensation, including: pixels positioned in the intersections of scan lines and data lines, wherein each pixel comprises: a first transistor and a fourth transistor, connected at a common node, disposed between an anode of an OLED and a first power supply; a cathode of the OLED connected to a second power supply; a second transistor connected between a gate of the first transistor and a data line, and turned on when a scan signal is supplied to a scan line; a third transistor connected between the common node and the data line, and turned on when a scan signal is supplied to the scan line; a first capacitor connected between the gate of the first transistor and the anode of the OLED; and a second capacitor connected between the anode of the OLED and a predetermined voltage source.

摘要翻译： 一种能够驱动晶体管阈值电压补偿的有机发光显示装置，包括：位于扫描线和数据线的交点中的像素，其中每个像素包括：第一晶体管和第四晶体管，连接在公共节点处， OLED的阳极和第一电源; 连接到第二电源的OLED的阴极; 连接在第一晶体管的栅极和数据线之间的第二晶体管，当扫描信号被提供给扫描线时导通; 连接在公共节点和数据线之间的第三晶体管，当扫描信号被提供给扫描线时导通; 连接在第一晶体管的栅极和OLED的阳极之间的第一电容器; 以及连接在OLED的阳极和预定电压源之间的第二电容器。

公开(公告)号：US08728887B2

公开(公告)日：2014-05-20

申请号：US13468319

申请日：2012-05-10

申请人： Jeong-Yeop Lee ,  Hyung-Soon Park ,  Young-Bang Lee ,  Su-Young Kim

发明人： Jeong-Yeop Lee ,  Hyung-Soon Park ,  Young-Bang Lee ,  Su-Young Kim

IPC分类号： H01L21/8242

CPC分类号： H01L28/90 ,  H01L27/10852

摘要： A method for fabricating a capacitor of a semiconductor device includes sequentially forming an etch-stop layer and a mold layer over a substrate, sequentially forming a support layer and a hard mask pattern over the mold layer, forming a storage node hole by etching the support layer and the mold layer using the hard mask pattern as an etch barrier, forming a barrier layer on the sidewall of the mold layer inside the storage node hole, etching the etch-stop layer under the storage node hole, forming a storage node inside the storage node hole, and removing the hard mask pattern, the mold layer, and the barrier layer.

摘要翻译： 一种用于制造半导体器件的电容器的方法包括在衬底上顺序地形成蚀刻停止层和模具层，在模具层上依次形成支撑层和硬掩模图案，通过蚀刻支撑体形成存储节点孔 层和模具层，使用硬掩模图案作为蚀刻阻挡层，在存储节点孔内部的模具层的侧壁上形成阻挡层，蚀刻存储节点孔下方的蚀刻停止层，在其内部形成存储节点 存储节点孔，以及去除硬掩模图案，模具层和阻挡层。

公开(公告)号：US08344450B2

公开(公告)日：2013-01-01

申请号：US13541213

申请日：2012-07-03

申请人： Su-Young Kim

发明人： Su-Young Kim

IPC分类号： H01L29/94

CPC分类号： H01L21/823487 ,  H01L27/10823 ,  H01L27/10885 ,  H01L27/10894 ,  H01L29/41741 ,  H01L29/66666 ,  H01L29/7827

摘要： A semiconductor device includes: a semiconductor substrate configured to include a plurality of trenches therein; a plurality of buried bit lines each configured to fill a portion of each trench; a plurality of active pillars each formed in an upper portion of each buried bit line; a plurality of vertical gates each configured to surround each active pillar; and a plurality of word lines configured to couple neighboring vertical gates with each other.

摘要翻译： 半导体器件包括：半导体衬底，被配置为在其中包括多个沟槽; 多个掩埋位线，每个被配置为填充每个沟槽的一部分; 多个有源柱，各自形成在每个掩埋位线的上部; 多个垂直门，每个被配置为围绕每个有源支柱; 以及配置成将相邻垂直门彼此耦合的多个字线。

公开(公告)号：US08106345B2

公开(公告)日：2012-01-31

申请号：US12340359

申请日：2008-12-19

申请人： Do-Youb Kim ,  Su-Young Kim ,  Eun-Jung Lee ,  Dong-Wook Choi

发明人： Do-Youb Kim ,  Su-Young Kim ,  Eun-Jung Lee ,  Dong-Wook Choi

IPC分类号： H01L27/14 ,  H01L29/78 ,  H01L33/00

CPC分类号： G09G3/3233 ,  G09G2310/0291 ,  G09G2360/144 ,  G09G2360/145

摘要： A photo sensor in a flat panel display includes a first transistor having first, second, and gate electrodes respectively coupled to first, second, and third nodes; a second transistor having first, second, and gate electrodes, respectively coupled to a fourth node, the first node, and a first control signal line; a third transistor having first, second, and gate electrodes, respectively coupled to the second node, the third node, and the first control signal line; a fourth transistor having first, second, and gate electrodes, respectively coupled to a reset power line, the third node, and a reset signal line; a fifth transistor having first, second, and gate electrodes, respectively coupled to a first power source, the first node, and a second control signal line; a sixth transistor having first, second, and gate electrodes, respectively coupled to the second node, output line, and the second control signal line; and a seventh transistor.

摘要翻译： 平板显示器中的光传感器包括：第一晶体管，其具有分别耦合到第一，第二和第三节点的第一，第二和第二栅极; 第二晶体管，其具有分别耦合到第四节点，第一节点和第一控制信号线的第一，第二和第二栅极电极; 第三晶体管，具有分别耦合到第二节点，第三节点和第一控制信号线的第一，第二和第二栅极电极; 第四晶体管，其具有分别耦合到复位电力线，第三节点和复位信号线的第一，第二和第二栅电极; 第五晶体管，具有分别耦合到第一电源，第一节点和第二控制信号线的第一，第二和第二栅电极; 第六晶体管，具有分别耦合到第二节点，输出线和第二控制信号线的第一，第二和第二栅电极; 和第七晶体管。

公开(公告)号：US20130328196A1

公开(公告)日：2013-12-12

申请号：US13607293

申请日：2012-09-07

申请人： Jun-Hyeub Sun ,  Sang-Oh Lee ,  Su-Young Kim

发明人： Jun-Hyeub Sun ,  Sang-Oh Lee ,  Su-Young Kim

IPC分类号： H01L21/768 ,  H01L23/48

CPC分类号： H01L27/10894 ,  H01L27/10852 ,  H01L28/92

摘要： A method for fabricating a semiconductor device includes forming a first dielectric structure over a second region of a substrate to expose a first region of the substrate, forming a barrier layer over an entire surface including the first dielectric structure, forming a second dielectric structure over the barrier layer in the first region, forming first open parts and second open parts in the first region and the second region, respectively, by etching the second dielectric structure, the barrier layer and the first dielectric structure, forming first conductive patterns filled in the first open parts and second conductive patterns filled in the second open parts, forming a protective layer to cover the second region, and removing the second dielectric structure.

摘要翻译： 一种用于制造半导体器件的方法包括在衬底的第二区域上形成第一电介质结构以暴露衬底的第一区域，在包括第一电介质结构的整个表面上形成阻挡层，在第 通过蚀刻第二介电结构，阻挡层和第一介电结构，分别在第一区域和第二区域中形成第一开口部分和第二开口部分，形成填充在第一区域中的第一导电图案 开放部分和第二导电图案填充在第二开口部分中，形成保护层以覆盖第二区域，以及去除第二介电结构。

公开(公告)号：US20090206378A1

公开(公告)日：2009-08-20

申请号：US12340359

申请日：2008-12-19

申请人： Do-Youb Kim ,  Su-Young Kim ,  Eun-Jung Lee ,  Dong-Wook Choi

发明人： Do-Youb Kim ,  Su-Young Kim ,  Eun-Jung Lee ,  Dong-Wook Choi

IPC分类号： H01L29/78 ,  H01L33/00

CPC分类号： G09G3/3233 ,  G09G2310/0291 ,  G09G2360/144 ,  G09G2360/145

摘要： A photo sensor in a flat panel display includes a first transistor having first, second, and gate electrodes respectively coupled to first, second, and third nodes; a second transistor having first, second, and gate electrodes, respectively coupled to a fourth node, the first node, and a first control signal line; a third transistor having first, second, and gate electrodes, respectively coupled to the second node, the third node, and the first control signal line; a fourth transistor having first, second, and gate electrodes, respectively coupled to a reset power line, the third node, and a reset signal line; a fifth transistor having first, second, and gate electrodes, respectively coupled to a first power source, the first node, and a second control signal line; a sixth transistor having first, second, and gate electrodes, respectively coupled to the second node, output line, and the second control signal line; and a seventh transistor.

摘要翻译： 平板显示器中的光传感器包括：第一晶体管，其具有分别耦合到第一，第二和第三节点的第一，第二和第二栅极; 第二晶体管，其具有分别耦合到第四节点，第一节点和第一控制信号线的第一，第二和第二栅极电极; 第三晶体管，具有分别耦合到第二节点，第三节点和第一控制信号线的第一，第二和第二栅极电极; 第四晶体管，其具有分别耦合到复位电力线，第三节点和复位信号线的第一，第二和第二栅电极; 第五晶体管，具有分别耦合到第一电源，第一节点和第二控制信号线的第一，第二和第二栅电极; 第六晶体管，具有分别耦合到第二节点，输出线和第二控制信号线的第一，第二和第二栅电极; 和第七晶体管。

公开(公告)号：US08728898B2

公开(公告)日：2014-05-20

申请号：US13339747

申请日：2011-12-29

申请人： Su-Young Kim

发明人： Su-Young Kim

IPC分类号： H01L21/00 ,  H01L49/02

CPC分类号： H01L28/91 ,  H01L28/60

摘要： A method for fabricating a semiconductor device includes forming a mold layer over a substrate, wherein the mold layer includes a first sacrificial layer and a second sacrificial layer that are stacked, forming an insulation layer pattern that has an etch selectivity to the first sacrificial layer and the second sacrificial layer on the mold layer, etching the mold layer using the insulation layer pattern as an etch barrier to form storage node holes, forming a storage node conductive layer over a substrate structure including the insulation layer pattern and the mold layer that has been etched, performing a storage node isolation process that simultaneously forms storage nodes and forming the insulation layer pattern to a first thickness, and removing the first sacrificial layer and the second sacrificial layer.

摘要翻译： 一种用于制造半导体器件的方法包括在衬底上形成模具层，其中模具层包括堆叠的第一牺牲层和第二牺牲层，形成对第一牺牲层具有蚀刻选择性的绝缘层图案，以及 在模具层上的第二牺牲层，使用绝缘层图案蚀刻模具层作为蚀刻阻挡层以形成存储节点孔，在包括绝缘层图案和模制层的衬底结构之上形成存储节点导电层 蚀刻，执行存储节点隔离过程，其同时形成存储节点并将绝缘层图案形成为第一厚度，以及去除第一牺牲层和第二牺牲层。

公开(公告)号：US20130164903A1

公开(公告)日：2013-06-27

申请号：US13468319

申请日：2012-05-10

申请人： Jeong-Yeop Lee ,  Hyung-Soon Park ,  Young-Bang Lee ,  Su-Young Kim

发明人： Jeong-Yeop Lee ,  Hyung-Soon Park ,  Young-Bang Lee ,  Su-Young Kim

IPC分类号： H01L21/02

CPC分类号： H01L28/90 ,  H01L27/10852

摘要： A method for fabricating a capacitor of a semiconductor device includes sequentially forming an etch-stop layer and a mold layer over a substrate, sequentially forming a support layer and a hard mask pattern over the mold layer, forming a storage node hole by etching the support layer and the mold layer using the hard mask pattern as an etch barrier, forming a barrier layer on the sidewall of the mold layer inside the storage node hole, etching the etch-stop layer under the storage node hole, forming a storage node inside the storage node hole, and removing the hard mask pattern, the mold layer, and the barrier layer.

摘要翻译： 一种用于制造半导体器件的电容器的方法包括在衬底上顺序地形成蚀刻停止层和模具层，在模具层上依次形成支撑层和硬掩模图案，通过蚀刻支撑体形成存储节点孔 层和模具层，使用硬掩模图案作为蚀刻阻挡层，在存储节点孔内部的模具层的侧壁上形成阻挡层，蚀刻存储节点孔下方的蚀刻停止层，在其内部形成存储节点 存储节点孔，以及去除硬掩模图案，模具层和阻挡层。