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    METHOD FOR FABRICATING CAPACITOR OF SEMICONDUCTOR DEVICE
    1.
    发明申请
    METHOD FOR FABRICATING CAPACITOR OF SEMICONDUCTOR DEVICE 有权
    用于制造半导体器件电容器的方法

    公开(公告)号：US20130164903A1

    公开(公告)日：2013-06-27

    申请号：US13468319

    申请日：2012-05-10

    申请人： Jeong-Yeop Lee ,  Hyung-Soon Park ,  Young-Bang Lee ,  Su-Young Kim

    发明人： Jeong-Yeop Lee ,  Hyung-Soon Park ,  Young-Bang Lee ,  Su-Young Kim

    IPC分类号： H01L21/02

    CPC分类号： H01L28/90 ,  H01L27/10852

    摘要： A method for fabricating a capacitor of a semiconductor device includes sequentially forming an etch-stop layer and a mold layer over a substrate, sequentially forming a support layer and a hard mask pattern over the mold layer, forming a storage node hole by etching the support layer and the mold layer using the hard mask pattern as an etch barrier, forming a barrier layer on the sidewall of the mold layer inside the storage node hole, etching the etch-stop layer under the storage node hole, forming a storage node inside the storage node hole, and removing the hard mask pattern, the mold layer, and the barrier layer.

    摘要翻译： 一种用于制造半导体器件的电容器的方法包括在衬底上顺序地形成蚀刻停止层和模具层，在模具层上依次形成支撑层和硬掩模图案，通过蚀刻支撑体形成存储节点孔 层和模具层，使用硬掩模图案作为蚀刻阻挡层，在存储节点孔内部的模具层的侧壁上形成阻挡层，蚀刻存储节点孔下方的蚀刻停止层，在其内部形成存储节点 存储节点孔，以及去除硬掩模图案，模具层和阻挡层。

    Method for fabricating capacitor of semiconductor device
    2.
    发明授权
    Method for fabricating capacitor of semiconductor device 有权
    制造半导体器件电容器的方法

    公开(公告)号：US08728887B2

    公开(公告)日：2014-05-20

    申请号：US13468319

    申请日：2012-05-10

    申请人： Jeong-Yeop Lee ,  Hyung-Soon Park ,  Young-Bang Lee ,  Su-Young Kim

    发明人： Jeong-Yeop Lee ,  Hyung-Soon Park ,  Young-Bang Lee ,  Su-Young Kim

    IPC分类号： H01L21/8242

    CPC分类号： H01L28/90 ,  H01L27/10852

    摘要： A method for fabricating a capacitor of a semiconductor device includes sequentially forming an etch-stop layer and a mold layer over a substrate, sequentially forming a support layer and a hard mask pattern over the mold layer, forming a storage node hole by etching the support layer and the mold layer using the hard mask pattern as an etch barrier, forming a barrier layer on the sidewall of the mold layer inside the storage node hole, etching the etch-stop layer under the storage node hole, forming a storage node inside the storage node hole, and removing the hard mask pattern, the mold layer, and the barrier layer.

    摘要翻译： 一种用于制造半导体器件的电容器的方法包括在衬底上顺序地形成蚀刻停止层和模具层，在模具层上依次形成支撑层和硬掩模图案，通过蚀刻支撑体形成存储节点孔 层和模具层，使用硬掩模图案作为蚀刻阻挡层，在存储节点孔内部的模具层的侧壁上形成阻挡层，蚀刻存储节点孔下方的蚀刻停止层，在其内部形成存储节点 存储节点孔，以及去除硬掩模图案，模具层和阻挡层。

    SIGNAL AMPLIFICATION TECHNIQUE FOR MASS ANALYSIS
    3.
    发明申请
    SIGNAL AMPLIFICATION TECHNIQUE FOR MASS ANALYSIS 有权
    信号放大技术用于质谱分析

    公开(公告)号：US20110053292A1

    公开(公告)日：2011-03-03

    申请号：US12937139

    申请日：2009-04-10

    申请人： Hyung-Soon Park ,  Sang-Wan So ,  Woon-Seok Yeo ,  Soo-Jae Lee ,  Jung-Rok Lee ,  Ju-Hee Lee ,  Kwang-Pyo Kim

    发明人： Hyung-Soon Park ,  Sang-Wan So ,  Woon-Seok Yeo ,  Soo-Jae Lee ,  Jung-Rok Lee ,  Ju-Hee Lee ,  Kwang-Pyo Kim

    IPC分类号： G01N33/543 ,  C12N9/10 ,  C07K14/435 ,  C07K16/00

    CPC分类号： G01N33/553 ,  G01N33/585 ,  G01N33/6848 ,  G01N2458/15 ,  H01J49/00 ,  Y10T436/24

    摘要： There is provided a novel method for amplifying mass spectrometric signals. More particularly, a novel method for detecting signals of a target molecule includes: i) allowing a test sample, in which it is required to determine whether or not a target molecule is present, to be contact with a gold particle whose surface is modified to selectively bind to the target molecule, ii) allowing a low molecular molecule engrafted to the gold particle to generate mass spectrometric signals after the interaction, such as binding, between the gold particle and the target molecule, and iii) amplifying the mass spectrometric signals by generating a great deal of mass spectrometric signals of the low molecular molecule even in the presence of a trace of the target molecule. Also, the assay system using the method and the gold particle prepared in the method are provided. The method may be useful to specifically amplify signals of the target molecule without any pretreatment of a test sample, which makes it possible to measure the target molecule simply and precisely.

    摘要翻译： 提供了一种扩增质谱信号的新方法。 更具体地，用于检测靶分子的信号的新方法包括：i）允许测试样品，其中需要确定靶分子是否存在，以将其表面修饰的金颗粒与 选择性地结合靶分子，ii）允许移植到金颗粒上的低分子分子在金颗粒和靶分子之间的相互作用之后产生质谱信号，例如结合，以及iii）通过以下步骤扩增质谱信号： 甚至在痕量的靶分子的存在下也产生大量低分子分子的质谱信号。 此外，提供了使用该方法的测定系统和该方法中制备的金颗粒。 该方法可用于特异性扩增靶分子的信号而无需对测试样品进行任何预处理，这使得可以简单且精确地测量目标分子。

    Signal amplification technique for mass analysis
    5.
    发明授权
    Signal amplification technique for mass analysis 有权
    信号放大技术进行质量分析

    公开(公告)号：US08673653B2

    公开(公告)日：2014-03-18

    申请号：US12937139

    申请日：2009-04-10

    申请人： Hyung-Soon Park ,  Sang-Wan So ,  Woon-Seok Yeo ,  Soo-Jae Lee ,  Jung-Rok Lee ,  Ju-Hee o Lee ,  Kwang-Pyo Kim

    发明人： Hyung-Soon Park ,  Sang-Wan So ,  Woon-Seok Yeo ,  Soo-Jae Lee ,  Jung-Rok Lee ,  Ju-Hee o Lee ,  Kwang-Pyo Kim

    IPC分类号： G01N33/553

    CPC分类号： G01N33/553 ,  G01N33/585 ,  G01N33/6848 ,  G01N2458/15 ,  H01J49/00 ,  Y10T436/24

    摘要： Provided is a novel method for amplifying mass spectrometric signals. A novel method for detecting signals of a target molecule includes: allowing a sample, which comprises a target molecule, to contact a gold particle having a surface modified to selectively bind the target molecule, allowing a low molecular weight molecule engrafted to the gold particle generate mass spectrometric signals after the interaction, e.g., binding, between the gold particle and the target molecule, and amplifying the mass spectrometric signals to generate much mass spectrometric signals of the low molecular weight molecule even when trace amounts of the target molecule are present. An assay system using the method and the gold particle prepared in the method are provided. The method amplifies signals of the target molecule without pretreatment of a sample, making it possible to measure the target molecule simply and precisely.

    摘要翻译： 提供了一种扩增质谱信号的新方法。 用于检测靶分子信号的新方法包括：允许包含目标分子的样品接触具有修饰以选择性结合靶分子的表面的金颗粒，允许移植到金颗粒的低分子量分子产生 即使存在痕量的目标分子，即使在金颗粒与靶分子之间的相互作用之后的质谱信号，也可以扩增质谱信号以产生低分子量分子的大量质谱信号。 提供了使用该方法的测定系统和该方法中制备的金颗粒。 该方法在不预处理样品的情况下放大靶分子的信号，使得可以简单且准确地测量目标分子。

    SYSTEM AND METHOD FOR EVALUATING NEUROMUSCULAR AND JOINT PROPERTIES
    6.
    发明申请
    SYSTEM AND METHOD FOR EVALUATING NEUROMUSCULAR AND JOINT PROPERTIES 审中-公开
    用于评估神经细胞和关节特性的系统和方法

    公开(公告)号：US20100106059A1

    公开(公告)日：2010-04-29

    申请号：US12532626

    申请日：2008-03-24

    申请人： Li-Qun Zhang ,  Hyung-Soon Park ,  Yupeng Ren

    发明人： Li-Qun Zhang ,  Hyung-Soon Park ,  Yupeng Ren

    IPC分类号： A61B5/103

    CPC分类号： A61B5/22 ,  A61B5/4519 ,  A61B5/4523 ,  A61B5/4528 ,  A61B9/005

    摘要： A pocket neuromuscular evaluator delivers controlled tendon taps, makes quantitative measures of the taps and the reflex responses invoked, evaluates not only the neurological reflexes but also the muscle-joint properties, analyzes the data, displays the results, and records them to provide quantitative characterizations of the neuromuscular and joint properties.

    摘要翻译： 口袋神经肌肉评估仪提供受控的肌腱抽头，进行抽头和反射反应的定量测量，不仅评估神经反射，而且评估肌肉关节特性，分析数据，显示结果，并记录它们以提供定量表征 的神经肌肉和关节性质。

    Robotic rehabilitation apparatus and method
    7.
    发明授权
    Robotic rehabilitation apparatus and method 有权
    机器人康复设备及方法

    公开(公告)号：US08317730B2

    公开(公告)日：2012-11-27

    申请号：US12527389

    申请日：2008-02-15

    申请人： Li-Qun Zhang ,  Hyung-Soon Park ,  Yupeng Ren

    发明人： Li-Qun Zhang ,  Hyung-Soon Park ,  Yupeng Ren

    IPC分类号： A61B5/103 ,  A61B5/117 ,  A61H1/00 ,  A61H1/02 ,  A61H5/00 ,  A61H7/00 ,  A61H19/00

    CPC分类号： A61F5/0102 ,  A61H1/0237 ,  A61H1/0274 ,  A61H1/0281 ,  A61H1/0285 ,  A61H1/0288 ,  A61H2201/0192 ,  A61H2201/1215 ,  A61H2201/163 ,  A61H2201/1638 ,  A61H2201/1642 ,  A61H2201/1659 ,  A61H2201/1676 ,  A61H2201/5007 ,  A61H2201/5061

    摘要： This patent describes an 8+2 degrees of freedom (DOF) intelligent rehabilitation robot capable of controlling the shoulder, elbow, wrist and fingers individually and allowing functional arm movements with accompanying trunk and scapular motions. The rehabilitation robot uses the following integrated rehabilitation approach: 1) it has unique diagnostic capabilities to determine patient-specific multiple joint and/or multiple DOF biomechanical and neuromuscular changes; 2) it stretches the stiff joints/DOFs under intelligent control to loosen up the specific stiff joints and to reduce excessive cross-coupling torques/movements between the specific joints/DOFs, which can be done based on the above diagnosis for subject-specific treatment; 3) the patients practice voluntary reaching and some functional tasks to regain/improve their motor control capability, which can be done after the stretching loosened up the stiff joints; and 4) the outcome will be evaluated quantitatively at the levels of individual joints, multiple joints/DOFs, and the whole arm.

    摘要翻译： 该专利描述了能够单独控制肩部，肘部，手腕和手指的8 + 2自由度（DOF）智能康复机器人，并且允许具有伴随的躯干和肩胛骨运动的功能性手臂运动。 康复机器人使用以下综合康复方法：1）具有独特的诊断能力，可以确定患者特异性的多关节和/或多个DOF生物力学和神经肌肉变化; 2）它在智能控制下伸展刚性接头/ DOF，松开特定的刚性接头，并减少特定接头/自由度之间过度的交叉耦合扭矩/运动，这可以根据上述对受试者特异性治疗的诊断 ; 3）患者练习自愿到达和一些功能性任务，以恢复/提高其运动控制能力，拉伸松弛后可以完成; 和4）结果将在个体关节，多关节/自由度和整个手臂的水平进行定量评估。

    METHOD FOR FORMING PATTERN IN SEMICONDUCTOR DEVICE
    8.
    发明申请
    METHOD FOR FORMING PATTERN IN SEMICONDUCTOR DEVICE 失效
    在半导体器件中形成图案的方法

    公开(公告)号：US20090117739A1

    公开(公告)日：2009-05-07

    申请号：US11965582

    申请日：2007-12-27

    申请人： Jong-Han Shin ,  Hyung-Soon Park ,  Cheol-Hwi Ryu ,  Jum-Yong Park ,  Sung-Jun Kim

    发明人： Jong-Han Shin ,  Hyung-Soon Park ,  Cheol-Hwi Ryu ,  Jum-Yong Park ,  Sung-Jun Kim

    IPC分类号： H01L21/306

    CPC分类号： H01L21/0337 ,  H01L21/0334 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10894

    摘要： A method for forming a pattern in a semiconductor device includes forming an etch-target layer over a substrate, wherein the substrate includes a first region having a smaller pattern than the first region, forming a sacrificial layer and a passivation layer over the etch-target layer, etching the passivation layer and the sacrificial layer to form stack structures including a sacrificial pattern and a passivation pattern, forming spacers over sidewalls of the stack structures, forming a mask pattern covering the second region, removing a portion of the passivation pattern in the first region exposed by the mask pattern to expose a portion of the sacrificial pattern in the first region, removing the exposed portion of the sacrificial pattern in the first region, and etching the etch-target layer to form an etch-target pattern using the spacers in the first and second regions and the stack structure formed between the spacers in the second region.

    摘要翻译： 在半导体器件中形成图案的方法包括在衬底上形成蚀刻目标层，其中衬底包括具有比第一区域更小的图案的第一区域，在蚀刻靶上形成牺牲层和钝化层 蚀刻钝化层和牺牲层以形成包括牺牲图案和钝化图案的堆叠结构，在堆叠结构的侧壁上形成间隔物，形成覆盖第二区域的掩模图案，从而去除钝化层的一部分 第一区域由掩模图案曝光以暴露第一区域中的牺牲图案的一部分，去除第一区域中的牺牲图案的暴露部分，以及蚀刻蚀刻目标层，以使用间隔物 在第一区域和第二区域中形成叠层结构，并且在第二区域中形成在间隔物之间​​。

    Method for fabricating recessed gate structure
    9.
    发明申请
    Method for fabricating recessed gate structure 审中-公开
    凹陷门结构的制造方法

    公开(公告)号：US20060128130A1

    公开(公告)日：2006-06-15

    申请号：US11003755

    申请日：2004-12-02

    申请人： Se-Aug Jang ,  Heung-Jae Cho ,  Woo-Jin Kim ,  Hyung-Soon Park ,  Seo-Min Kim ,  Tae-Woo Jung

    发明人： Se-Aug Jang ,  Heung-Jae Cho ,  Woo-Jin Kim ,  Hyung-Soon Park ,  Seo-Min Kim ,  Tae-Woo Jung

    IPC分类号： H01L21/4763

    CPC分类号： H01L29/66621 ,  H01L29/4236

    摘要： The present invention relates to a method for fabricating a recessed gate structure. The method includes the steps of: selectively etching a substrate to form a plurality of openings; forming a gate oxide layer on the openings and the substrate; forming a first conductive silicon layer on the gate oxide layer to form a plurality of valleys at a height equal to or greater than a thickness remaining after an intended pattern is formed; planarizing the first conductive silicon layer until the thickness remaining after the intended pattern formation is obtained, so that the valleys are removed; forming a second conductive layer on a planarized first conductive silicon layer; and selectively etching the second conductive layer, the first conductive silicon layer and the gate oxide layer to form a plurality of the recessed gate structures.

    摘要翻译： 本发明涉及一种用于制造凹陷栅极结构的方法。 该方法包括以下步骤：选择性地蚀刻基板以形成多个开口; 在所述开口和所述基板上形成栅氧化层; 在所述栅极氧化层上形成第一导电硅层，以在形成预期图案之后的厚度等于或大于剩余的厚度上形成多个谷; 平面化第一导电硅层，直到获得预期图案形成之后剩余的厚度，从而除去谷; 在平坦化的第一导电硅层上形成第二导电层; 并且选择性地蚀刻第二导电层，第一导电硅层和栅极氧化物层以形成多个凹陷栅极结构。