公开(公告)号：US07544991B2

公开(公告)日：2009-06-09

申请号：US11698067

申请日：2007-01-26

申请人： Jin-Woo Kim ,  Jong-Hyon Ahn ,  Don-Woo Lee

发明人： Jin-Woo Kim ,  Jong-Hyon Ahn ,  Don-Woo Lee

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/42336 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11553 ,  H01L29/7885

摘要： A non-volatile memory device and methods of manufacturing and operating the same are provided. In a method of manufacturing a non-volatile memory device, a substrate having a stepped portion that may include a first horizontal face, a second horizontal face lower than the first horizontal face, and a vertical face connected between the first and second horizontal faces may be prepared. A first impurity region may be formed under the first horizontal face. A tunnel insulation layer may be continuously formed on the vertical face and the second horizontal face. A floating gate electrode having a tip higher than the first horizontal face may be formed on the tunnel insulation layer. A dielectric layer may be formed on the floating gate electrode. The floating gate electrode may be covered with a control gate electrode. A second impurity region horizontally spaced apart from the floating gate electrode may be formed under the second horizontal face.

摘要翻译： 提供了一种非易失性存储器件及其制造和操作方法。 在制造非易失性存储器件的方法中，具有阶梯部分的衬底可以包括第一水平面，比第一水平面低的第二水平面和连接在第一和第二水平面之间的垂直面， 准备好 可以在第一水平面下方形成第一杂质区。 隧道绝缘层可以在垂直面和第二水平面上连续地形成。 具有尖端高于第一水平面的浮栅电极可以形成在隧道绝缘层上。 可以在浮栅电极上形成电介质层。 浮栅电极可以用控制栅电极覆盖。 可以在第二水平面下方形成与浮栅电极水平间隔开的第二杂质区域。

公开(公告)号：US06300233B1

公开(公告)日：2001-10-09

申请号：US09714392

申请日：2000-11-16

申请人： Dong-Hun Lee ,  Jong-Hyon Ahn

发明人： Dong-Hun Lee ,  Jong-Hyon Ahn

IPC分类号： H01L2144

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a fuse of a semiconductor device and a method of forming a fuse of a semiconductor device. The method of the invention includes forming an underlying metal conductor on a semiconductor substrate, forming an insulating film over the underlying metal conductor, and selectively etching regions of the insulating film. One of the regions of the insulating film is etched to form a via contact region exposing the underlying metal conductor. A second region is etched to form a groove in the insulating film for the fuse metal. Metal is buried within the second etched region of the insulating film and the via contact region to respectively form a fuse metal pattern and a via contact metal layer. The fuse metal pattern can be formed from copper and/or tungsten.

摘要翻译： 本发明提供一种半导体器件的熔丝和形成半导体器件的熔丝的方法。 本发明的方法包括在半导体衬底上形成下面的金属导体，在下面的金属导体上形成绝缘膜，并选择性地蚀刻绝缘膜的区域。 蚀刻绝缘膜的一个区域以形成暴露下面的金属导体的通孔接触区域。 蚀刻第二区域以在用于熔丝金属的绝缘膜中形成凹槽。 金属被埋在绝缘膜和通孔接触区域的第二蚀刻区域内，以分别形成熔丝金属图案和通孔接触金属层。 熔丝金属图案可以由铜和/或钨形成。

公开(公告)号：US07361565B2

公开(公告)日：2008-04-22

申请号：US11037506

申请日：2005-01-18

申请人： Jeong-Ho Shin ,  Jong-Hyon Ahn ,  Kong-Soo Cheong ,  Jin-Won Jun

发明人： Jeong-Ho Shin ,  Jong-Hyon Ahn ,  Kong-Soo Cheong ,  Jin-Won Jun

IPC分类号： H01L21/336

CPC分类号： H01L29/66553 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： In a method of forming a metal gate in a semiconductor device, a gate insulation pattern and a dummy gate pattern are formed on a substrate. An insulation interlayer is formed on the dummy gate pattern to cover the dummy gate pattern. The insulation interlayer is polished such that a top surface of the dummy gate pattern is exposed, and the dummy gate pattern is selectively removed to form a trench on the substrate. A gate spacer is formed on an inner sidewall of the trench for determining a gate length of the metal gate. A metal is deposited to a sufficient thickness to fill the trench to form a metal layer. The metal layer is polished to remain in the trench. Accordingly, the gate length of the metal gate may be reduced no more than the resolution limit of the photolithography exposing system.

摘要翻译： 在半导体器件中形成金属栅极的方法中，在衬底上形成栅极绝缘图案和伪栅极图案。 在伪栅极图案上形成绝缘中间层以覆盖伪栅极图案。 抛光绝缘夹层，使得裸露栅极图案的顶表面露出，并且选择性地去除伪栅极图案以在衬底上形成沟槽。 栅极间隔件形成在沟槽的内侧壁上，用于确定金属栅极的栅极长度。 将金属沉积到足够的厚度以填充沟槽以形成金属层。 金属层被抛光以保留在沟槽中。 因此，金属栅极的栅极长度可以减小到不超过光刻曝光系统的分辨率极限。

公开(公告)号：US07008835B2

公开(公告)日：2006-03-07

申请号：US10985246

申请日：2004-11-10

申请人： You-Seung Jin ,  Jong-Hyon Ahn ,  Hyuk-Ju Ryu

发明人： You-Seung Jin ,  Jong-Hyon Ahn ,  Hyuk-Ju Ryu

IPC分类号： H01L21/336

CPC分类号： H01L29/4925 ,  H01L21/28035 ,  H01L21/28044 ,  H01L21/28052 ,  H01L21/28114 ,  H01L21/823425 ,  H01L21/823437 ,  H01L21/823443 ,  H01L21/823468 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/78 ,  H01L29/7833

摘要： In a method of manufacturing a semiconductor device, a gate insulation layer and a gate electrode are sequentially formed on a substrate on which an active region is defined. A planarized layer is formed on the substrate including the gate electrode. The planarized layer partially removed, and an upper portion of the gate electrode is exposed. A silicon epitaxial layer is selectively formed only on the exposed gate electrode, and the planarized layer is completely removed. A gate spacer is formed along side surfaces of the gate electrode and the silicon epitaxial layer. A source/drain region is formed on a surface portion of the active region corresponding to the gate electrode. Since the silicon epitaxial layer is formed only on the gate region except the source/drain region, the gate resistance is stabilized and the parasitic capacitance between the gate electrode and the source/drain region is reduce.

摘要翻译： 在制造半导体器件的方法中，栅极绝缘层和栅电极依次形成在其上限定有源区的衬底上。 在包括栅电极的基板上形成平坦化层。 平坦化层被部分去除，并且栅电极的上部被暴露。 硅外延层仅选择性地形成在暴露的栅电极上，并且平坦化层被完全去除。 栅极间隔物沿着栅电极和硅外延层的侧表面形成。 源极/漏极区域形成在与栅电极对应的有源区的表面部分上。 由于仅在除源极/漏极区域之外的栅极区域上形成硅外延层，所以栅极电阻稳定，并且栅极电极和源极/漏极区域之间的寄生电容减小。

公开(公告)号：US20050112834A1

公开(公告)日：2005-05-26

申请号：US10985246

申请日：2004-11-10

申请人： You-Seung Jin ,  Jong-Hyon Ahn ,  Hyuk-Ju Ryu

发明人： You-Seung Jin ,  Jong-Hyon Ahn ,  Hyuk-Ju Ryu

IPC分类号： H01L21/00 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L29/4925 ,  H01L21/28035 ,  H01L21/28044 ,  H01L21/28052 ,  H01L21/28114 ,  H01L21/823425 ,  H01L21/823437 ,  H01L21/823443 ,  H01L21/823468 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/78 ,  H01L29/7833

摘要： In a method of manufacturing a semiconductor device, a gate insulation layer and a gate electrode are sequentially formed on a substrate on which an active region is defined. A planarized layer is formed on the substrate including the gate electrode. The planarized layer partially removed, and an upper portion of the gate electrode is exposed. A silicon epitaxial layer is selectively formed only on the exposed gate electrode, and the planarized layer is completely removed. A gate spacer is formed along side surfaces of the gate electrode and the silicon epitaxial layer. A source/drain region is formed on a surface portion of the active region corresponding to the gate electrode. Since the silicon epitaxial layer is formed only on the gate region except the source/drain region, the gate resistance is stabilized and the parasitic capacitance between the gate electrode and the source/drain region is reduce.

摘要翻译： 在制造半导体器件的方法中，栅极绝缘层和栅电极依次形成在其上限定有源区的衬底上。 在包括栅电极的基板上形成平坦化层。 平坦化层被部分去除，并且栅电极的上部被暴露。 硅外延层仅选择性地形成在暴露的栅电极上，并且平坦化层被完全去除。 栅极间隔物沿着栅电极和硅外延层的侧表面形成。 源极/漏极区域形成在与栅电极对应的有源区的表面部分上。 由于仅在除源极/漏极区域之外的栅极区域上形成硅外延层，所以栅极电阻稳定，并且栅极电极和源极/漏极区域之间的寄生电容减小。

公开(公告)号：US5612246A

公开(公告)日：1997-03-18

申请号：US549441

申请日：1995-10-27

申请人： Jong-Hyon Ahn

发明人： Jong-Hyon Ahn

IPC分类号： H01L21/8238 ,  H01L21/20 ,  H01L21/762 ,  H01L21/84 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L21/76

CPC分类号： H01L21/76202 ,  H01L21/7624 ,  H01L21/84 ,  Y10S438/911

摘要： A method for manufacturing a semiconductor substrate structure wherein a comprising the steps of defining bulk transistor and SOI transistor areas, the bulk transistor area disposed on a lower single crystalline silicon layer, and the SOI transistor area diposed on an upper single crystalline silicon layer. The method characterized in that a spacer is formed on a portion of the bulk transistor area which covers a sidewall of the SOI transistor area, a first conductive well is formed in the lower single crystalline silicon layer and a well oxide layer is formed over the first conductive well region, a second conductive well is formed in the lower single crystalline silicon layer between the SOI transistor layer and the first conductive well, and the first conductive well is rediffused.

摘要翻译： 一种用于制造半导体衬底结构的方法，其中包括以下步骤：定义体晶体管和SOI晶体管区域，所述体晶体管区域设置在下单晶硅层上，并且所述SOI晶体管区域被放置在上单晶硅层上。 该方法的特征在于，在覆盖SOI晶体管区域的侧壁的体晶体管区域的一部分上形成间隔物，第一导电阱形成在下单晶硅层中，并且在第一 在SOI晶体管层和第一导电阱之间的下单晶硅层中形成第二导电阱，并且第一导电阱被再扩散。

公开(公告)号：US20080093649A1

公开(公告)日：2008-04-24

申请号：US11698067

申请日：2007-01-26

申请人： Jin-Woo Kim ,  Jong-Hyon Ahn ,  Don-Woo Lee

发明人： Jin-Woo Kim ,  Jong-Hyon Ahn ,  Don-Woo Lee

IPC分类号： H01L29/788

CPC分类号： H01L29/42336 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11553 ,  H01L29/7885

摘要： A non-volatile memory device and methods of manufacturing and operating the same are provided. In a method of manufacturing a non-volatile memory device, a substrate having a stepped portion that may include a first horizontal face, a second horizontal face lower than the first horizontal face, and a vertical face connected between the first and second horizontal faces may be prepared. A first impurity region may be formed under the first horizontal face. A tunnel insulation layer may be continuously formed on the vertical face and the second horizontal face. A floating gate electrode having a tip higher than the first horizontal face may be formed on the tunnel insulation layer. A dielectric layer may be formed on the floating gate electrode. The floating gate electrode may be covered with a control gate electrode. A second impurity region horizontally spaced apart from the floating gate electrode may be formed under the second horizontal face.

摘要翻译： 提供了一种非易失性存储器件及其制造和操作方法。 在制造非易失性存储器件的方法中，具有阶梯部分的衬底可以包括第一水平面，比第一水平面低的第二水平面和连接在第一和第二水平面之间的垂直面， 准备好 可以在第一水平面下方形成第一杂质区。 隧道绝缘层可以在垂直面和第二水平面上连续地形成。 具有尖端高于第一水平面的浮栅电极可以形成在隧道绝缘层上。 可以在浮栅电极上形成电介质层。 浮栅电极可以用控制栅电极覆盖。 可以在第二水平面下方形成与浮栅电极水平间隔开的第二杂质区域。

公开(公告)号：US20050158935A1

公开(公告)日：2005-07-21

申请号：US11037506

申请日：2005-01-18

申请人： Jeong-Ho Shin ,  Jong-Hyon Ahn ,  Kong-Soo Cheong ,  Jin-Won Jun

发明人： Jeong-Ho Shin ,  Jong-Hyon Ahn ,  Kong-Soo Cheong ,  Jin-Won Jun

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/66553 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： In a method of forming a metal gate in a semiconductor device, a gate insulation pattern and a dummy gate pattern are formed on a substrate. An insulation interlayer is formed on the dummy gate pattern to cover the dummy gate pattern. The insulation interlayer is polished such that a top surface of the dummy gate pattern is exposed, and the dummy gate pattern is selectively removed to form a trench on the substrate. A gate spacer is formed on an inner sidewall of the trench for determining a gate length of the metal gate. A metal is deposited to a sufficient thickness to fill the trench to form a metal layer. The metal layer is polished to remain in the trench. Accordingly, the gate length of the metal gate may be reduced no more than the resolution limit of the photolithography exposing system.

摘要翻译： 在半导体器件中形成金属栅极的方法中，在衬底上形成栅极绝缘图案和伪栅极图案。 在伪栅极图案上形成绝缘中间层以覆盖伪栅极图案。 抛光绝缘夹层，使得裸露栅极图案的顶表面露出，并且选择性地去除伪栅极图案以在衬底上形成沟槽。 栅极间隔件形成在沟槽的内侧壁上，用于确定金属栅极的栅极长度。 将金属沉积到足够的厚度以填充沟槽以形成金属层。 金属层被抛光以保留在沟槽中。 因此，金属栅极的栅极长度可以减小到不超过光刻曝光系统的分辨率极限。

公开(公告)号：US20050110012A1

公开(公告)日：2005-05-26

申请号：US10997441

申请日：2004-11-23

申请人： Dong-Hun Lee ,  Jong-Hyon Ahn ,  Do-Yul Yoo ,  Sung-Gun Kang

发明人： Dong-Hun Lee ,  Jong-Hyon Ahn ,  Do-Yul Yoo ,  Sung-Gun Kang

IPC分类号： H01L21/027 ,  G03F7/20 ,  H01L23/544 ,  H01L29/10

CPC分类号： G03F7/70633 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54453 ,  H01L2223/54466 ,  H01L2924/0002 ,  H01L2924/00

摘要： An overlay mark includes at least one hole array formed on a semiconductor substrate and at least one linear trench adjacent to the hole array. The hole array may be formed adjacent to the linear trench along a predetermined direction. When alignment errors among patterns formed at predetermined portion of the semiconductor substrate are detected, the overlay mark may provide a contrast of light with a desired width and a high level so that alignment errors of patterns formed on the semiconductor substrate may be accurately detected and corrected using the overlay mark.

摘要翻译： 覆盖标记包括形成在半导体衬底上的至少一个孔阵列和与孔阵列相邻的至少一个线性沟槽。 孔阵列可以沿着预定方向形成为与线性沟槽相邻。 当检测到在半导体衬底的预定部分形成的图形之间的对准误差时，重叠标记可以提供具有所需宽度和高电平的光的对比度，从而可以精确地检测和校正形成在半导体衬底上的图案的对准误差 使用重叠标记。

公开(公告)号：US06765255B2

公开(公告)日：2004-07-20

申请号：US10396762

申请日：2003-03-25

申请人： You-Seung Jin ,  Jong-Hyon Ahn

发明人： You-Seung Jin ,  Jong-Hyon Ahn

IPC分类号： H01L27108

CPC分类号： H01L23/5223 ,  H01L21/76807 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device having a capacitor of an MIM structure and a method of forming the same are described. The semiconductor device includes a semiconductor substrate; a first bottom interconnection formed over the semiconductor substrate; an intermetal dielectric layer formed over the semiconductor substrate; a plurality of openings exposing the first bottom interconnection through the intermetal dielectric layer; a bottom electrode conformally formed on the inside wall of the openings, on the exposed surface of the first bottom interconnection and on the intermetal dielectric layer between the openings; a dielectric layer and an upper electrode sequentially stacked on the bottom electrode; and a first upper interconnection disposed on the upper electrode. According to the present invention, an effective surface area per a unit planar area of a capacitor with an MIM structure is enlarged to increase capacitance thereof.

摘要翻译： 描述了具有MIM结构的电容器的半导体器件及其形成方法。 半导体器件包括半导体衬底; 形成在所述半导体衬底上的第一底部互连; 形成在半导体衬底上的金属间电介质层; 多个开口，通过所述金属间电介质层暴露所述第一底部互连; 在所述开口的内壁上，在所述第一底部互连的暴露的表面上以及所述开口之间的金属间电介质层上共形形成的底部电极; 依次层叠在所述底部电极上的电介质层和上部电极; 以及设置在上电极上的第一上互连。 根据本发明，扩大了具有MIM结构的电容器的单位平面区域的有效表面积，以增加其电容。