公开(公告)号：US06872258B2

公开(公告)日：2005-03-29

申请号：US10178757

申请日：2002-06-25

申请人： Jong-chul Park ,  Dong-hyun Kim ,  O-ik Kwon ,  Hye-jin Jo

发明人： Jong-chul Park ,  Dong-hyun Kim ,  O-ik Kwon ,  Hye-jin Jo

IPC分类号： H01L21/3065 ,  C23C16/44 ,  C23C16/455 ,  H01L21/00 ,  C23C16/00 ,  C23F1/00 ,  H01L21/306

CPC分类号： C23C16/45565 ,  C23C16/45589 ,  H01L21/67017

摘要： A shower head for adjusting distribution of a reactant gas in a process region of a semiconductor manufacturing reaction chamber, wherein a top plate has a gas port for introducing the reactant gas into the reaction chamber; a face plate, having through holes, disposed opposite the process region; a first baffle plate, having through holes, disposed between the top plate and the face plate and capable of moving up or down, wherein the first baffle plate has a top surface that defines a first gap for forming a first lateral flow passage; a second baffle plate, having through holes, disposed between the first baffle plate and the face plate and capable of moving up or down, wherein the second baffle plate has a top surface that defines a second gap for forming a second lateral flow passage; and a gap controller for determining widths of the first and second gaps.

公开(公告)号：US20050145338A1

公开(公告)日：2005-07-07

申请号：US11057752

申请日：2005-02-15

申请人： Jong-chul Park ,  Dong-hyun Kim ,  O-ik Kwon ,  Hye-jin Jo

发明人： Jong-chul Park ,  Dong-hyun Kim ,  O-ik Kwon ,  Hye-jin Jo

IPC分类号： H01L21/3065 ,  C23C16/44 ,  C23C16/455 ,  H01L21/00 ,  C23F1/00

CPC分类号： C23C16/45565 ,  C23C16/45589 ,  H01L21/67017

摘要： A shower head for adjusting distribution of a reactant gas in a process region of a semiconductor manufacturing reaction chamber, wherein a top plate has a gas port for introducing the reactant gas into the reaction chamber; a face plate, having through holes, disposed opposite the process region; a first baffle plate, having through holes, disposed between the top plate and the face plate and capable of moving up or down, wherein the first baffle plate has a top surface that defines a first gap for forming a first lateral flow passage; a second baffle plate, having through holes, disposed between the first baffle plate and the face plate and capable of moving up or down, wherein the second baffle plate has a top surface that defines a second gap for forming a second lateral flow passage; and a gap controller for determining widths of the first and second gaps.

摘要翻译： 一种用于调整半导体制造反应室的处理区域中的反应气体的分布的喷头，其中顶板具有用于将反应气体引入反应室的气体口; 具有与所述处理区域相对设置的通孔的面板; 第一挡板，具有设置在所述顶板和所述面板之间并且能够上下移动的通孔，其中所述第一挡板具有限定用于形成第一侧流通道的第一间隙的顶表面; 第二挡板，具有设置在第一挡板和面板之间并且能够上下移动的通孔，其中第二挡板具有限定用于形成第二侧流通道的第二间隙的顶表面; 以及用于确定第一和第二间隙的宽度的间隙控制器。

公开(公告)号：US20120135579A1

公开(公告)日：2012-05-31

申请号：US13293777

申请日：2011-11-10

申请人： Jong-chul Park ,  Sang-sup Jeong

发明人： Jong-chul Park ,  Sang-sup Jeong

IPC分类号： H01L21/02 ,  H01L21/60 ,  H01L21/762

CPC分类号： H01L27/0207 ,  H01L27/10855 ,  H01L27/10888

摘要： A method uses a line pattern to form a semiconductor device including asymmetrical contact arrays. The method includes forming a plurality of parallel first conductive line layers extending in a first direction on a semiconductor substrate. In this method, the semiconductor substrate may have active regions forming an oblique angle with the first direction. The method may further include forming a first mask layer and a second mask layer and using the first mask layer and the second mask layer to form a trench comprising a line area and a contact area by etching the first conductive line layers using the first mask layer and the second mask layer. The method further includes forming a gap filling layer filling the line area of the trench and forming a spacer of sidewalls of the contact area and forming a second conductive line layer electrically connected to the active region.

摘要翻译： 一种方法使用线图形成包括不对称接触阵列的半导体器件。 该方法包括在半导体衬底上形成沿第一方向延伸的多个平行的第一导电线层。 在该方法中，半导体衬底可以具有与第一方向成倾斜角的有源区域。 该方法还可以包括形成第一掩模层和第二掩模层，并且使用第一掩模层和第二掩模层通过使用第一掩模层蚀刻第一导线层以形成包括线区域和接触区域的沟槽 和第二掩模层。 该方法还包括形成填充沟槽的线区域并形成接触区域的侧壁的间隔物的间隙填充层，并形成电连接到有源区域的第二导线层。

公开(公告)号：US20110104889A1

公开(公告)日：2011-05-05

申请号：US12965091

申请日：2010-12-10

申请人： Doo-young Lee ,  Sang-sup Jeong ,  Sung-gil Chol ,  Jong-chul Park ,  Jin-young Kim ,  Ki-jin Park

发明人： Doo-young Lee ,  Sang-sup Jeong ,  Sung-gil Chol ,  Jong-chul Park ,  Jin-young Kim ,  Ki-jin Park

IPC分类号： H01L21/768

CPC分类号： H01L21/76897 ,  H01L21/76831

摘要： Methods of forming integrated circuit devices include upper sidewall spacers in contact holes to provide enhanced electrical isolation to contact plugs therein while maintaining relatively low contact resistance. These methods include forming an interlayer insulating layer on a semiconductor substrate. The interlayer insulating layer includes at least a first electrically insulating layer of a first material on the semiconductor substrate and a second electrically insulating layer of a second material on the first electrically insulating layer. A contact hole is formed that extends through the interlayer insulating layer and exposes a primary surface of the semiconductor substrate. This contact hole may be formed by selectively etching the second electrically insulating layer and the first electrically insulating layer in sequence and at a faster etch rate of the first material relative to the second material. This sequential etching of the first material at a faster rate than the second material may yield a contact hole having a recessed sidewall.

摘要翻译： 形成集成电路器件的方法包括接触孔中的上部侧壁间隔物，以在保持相对低的接触电阻的同时对接触插塞提供增强的电隔离。 这些方法包括在半导体衬底上形成层间绝缘层。 层间绝缘层至少包括半导体衬底上的第一材料的第一电绝缘层和第一电绝缘层上的第二材料的第二电绝缘层。 形成延伸穿过层间绝缘层并暴露半导体衬底的主表面的接触孔。 可以通过相对于第二材料依次选择性地蚀刻第二电绝缘层和第一电绝缘层来形成第一材料的蚀刻速率。 以比第二材料更快的速率顺次蚀刻第一材料可能产生具有凹陷侧壁的接触孔。

公开(公告)号：US07875551B2

公开(公告)日：2011-01-25

申请号：US12575682

申请日：2009-10-08

申请人： Doo-young Lee ,  Sang-sup Jeong ,  Sung-gil Choi ,  Jong-chul Park ,  Jin-young Kim ,  Ki-jin Park

发明人： Doo-young Lee ,  Sang-sup Jeong ,  Sung-gil Choi ,  Jong-chul Park ,  Jin-young Kim ,  Ki-jin Park

IPC分类号： H01L23/58

CPC分类号： H01L21/76897 ,  H01L21/76831

摘要： Methods of forming integrated circuit devices include upper sidewall spacers in contact holes to provide enhanced electrical isolation to contact plugs therein while maintaining relatively low contact resistance. These methods include forming an interlayer insulating layer on a semiconductor substrate. The interlayer insulating layer includes at least a first electrically insulating layer of a first material on the semiconductor substrate and a second electrically insulating layer of a second material on the first electrically insulating layer. A contact hole is formed that extends through the interlayer insulating layer and exposes a primary surface of the semiconductor substrate. This contact hole may be formed by selectively etching the second electrically insulating layer and the first electrically insulating layer in sequence and at a faster etch rate of the first material relative to the second material. This sequential etching of the first material at a faster rate than the second material may yield a contact hole having a recessed sidewall.

摘要翻译： 形成集成电路器件的方法包括接触孔中的上部侧壁间隔物，以在保持相对低的接触电阻的同时对接触插塞提供增强的电隔离。 这些方法包括在半导体衬底上形成层间绝缘层。 层间绝缘层至少包括半导体衬底上的第一材料的第一电绝缘层和第一电绝缘层上的第二材料的第二电绝缘层。 形成延伸穿过层间绝缘层并暴露半导体衬底的主表面的接触孔。 该接触孔可以通过相对于第二材料依次选择性地蚀刻第二电绝缘层和第一电绝缘层而形成，并以较快的第一材料的蚀刻速率。 以比第二材料更快的速率顺次蚀刻第一材料可能产生具有凹陷侧壁的接触孔。

公开(公告)号：US07616080B2

公开(公告)日：2009-11-10

申请号：US11515305

申请日：2006-09-01

申请人： Chan-sei Yoo ,  Woo-sung Lee ,  Dongsu Kim ,  Nam-kee Kang ,  Jong-chul Park

发明人： Chan-sei Yoo ,  Woo-sung Lee ,  Dongsu Kim ,  Nam-kee Kang ,  Jong-chul Park

IPC分类号： H01P1/203

CPC分类号： H01P1/20381 ,  H01P1/2039

摘要： A bandpass filter (BPF) configured in 3-D structures for filtering signals of ultra wide bands is disclosed, the BPF comprising sequentially stacked first to fourth dielectric substrates, wherein the first dielectric substrate is formed at a bottom surface thereof with a first ground pattern, the second dielectric substrate is formed at an upper surface thereof with a second ground pattern, and a stripline pattern is formed between the first and second dielectric substrates. The fourth dielectric substrate is formed thereon with a filter pattern and input/output coupled line patterns.

摘要翻译： 公开了一种用于滤波超宽带信号的3-D结构的带通滤波器（BPF），BPF包括顺序堆叠的第一至第四电介质基板，其中第一电介质基板在其底表面处形成有第一接地图案 第二电介质基板在其上表面形成有第二接地图案，并且在第一和第二电介质基板之间形成带状线图形。 第四电介质基板在其上形成有滤波器图案和输入/输出耦合线图案。

公开(公告)号：US08551888B2

公开(公告)日：2013-10-08

申请号：US13238945

申请日：2011-09-21

申请人： Yun-seung Kang ,  Jong-chul Park ,  Kwang-yong Yang ,  Sang-sup Jeong ,  Seok-hyun Lim

发明人： Yun-seung Kang ,  Jong-chul Park ,  Kwang-yong Yang ,  Sang-sup Jeong ,  Seok-hyun Lim

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/3086 ,  H01L21/0337 ,  H01L21/32139 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11568

摘要： A method of forming patterns for a semiconductor device. The method includes: forming a first hard mask layer on a layer which is to be etched; forming a second hard mask layer on the first hard mask layer, wherein the second hard mask layer includes a first portion and a second portion formed underneath the first portion, wherein the first portion and second portion are composed of the same material; etching the first portion to form first patterns; forming spacers covering sidewalls of the first patterns; etching the second portion using the spacers as etch masks to form second patterns; etching the first hard mask layer and the spacers using the second patterns disposed underneath the spacers as etch masks to form third patterns; and etching the layer to be etched, using the third patterns.

摘要翻译： 一种形成半导体器件的图案的方法。 该方法包括：在要蚀刻的层上形成第一硬掩模层; 在所述第一硬掩模层上形成第二硬掩模层，其中所述第二硬掩模层包括形成在所述第一部分下面的第一部分和第二部分，其中所述第一部分和第二部分由相同的材料构成; 蚀刻第一部分以形成第一图案; 形成覆盖所述第一图案的侧壁的间隔物; 使用间隔物蚀刻第二部分作为蚀刻掩模以形成第二图案; 使用设置在间隔物下方的第二图案作为蚀刻掩模来蚀刻第一硬掩模层和间隔物以形成第三图案; 并使用第三图案蚀刻待蚀刻的层。

公开(公告)号：US20120129349A1

公开(公告)日：2012-05-24

申请号：US13238945

申请日：2011-09-21

申请人： Yun-seung Kang ,  Jong-chul Park ,  Kwang-yong Yang ,  Sang-sup Jeong ,  Seok-hyun Lim

发明人： Yun-seung Kang ,  Jong-chul Park ,  Kwang-yong Yang ,  Sang-sup Jeong ,  Seok-hyun Lim

IPC分类号： H01L21/308

CPC分类号： H01L21/3086 ,  H01L21/0337 ,  H01L21/32139 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11568

摘要： A method of forming patterns for a semiconductor device. The method includes: forming a first hard mask layer on a layer which is to be etched; forming a second hard mask layer on the first hard mask layer, wherein the second hard mask layer includes a first portion and a second portion formed underneath the first portion, wherein the first portion and second portion are composed of the same material; etching the first portion to form first patterns; forming spacers covering sidewalls of the first patterns; etching the second portion using the spacers as etch masks to form second patterns; etching the first hard mask layer and the spacers using the second patterns disposed underneath the spacers as etch masks to form third patterns; and etching the layer to be etched, using the third patterns.

摘要翻译： 一种形成半导体器件的图案的方法。 该方法包括：在要蚀刻的层上形成第一硬掩模层; 在所述第一硬掩模层上形成第二硬掩模层，其中所述第二硬掩模层包括形成在所述第一部分下面的第一部分和第二部分，其中所述第一部分和第二部分由相同的材料构成; 蚀刻第一部分以形成第一图案; 形成覆盖所述第一图案的侧壁的间隔物; 使用间隔物蚀刻第二部分作为蚀刻掩模以形成第二图案; 使用设置在间隔物下方的第二图案作为蚀刻掩模来蚀刻第一硬掩模层和间隔物以形成第三图案; 并使用第三图案蚀刻待蚀刻的层。

公开(公告)号：US08053358B2

公开(公告)日：2011-11-08

申请号：US12965091

申请日：2010-12-10

申请人： Doo-young Lee ,  Sang-sup Jeong ,  Sung-gil Choi ,  Jong-chul Park ,  Jin-young Kim ,  Ki-jin Park

发明人： Doo-young Lee ,  Sang-sup Jeong ,  Sung-gil Choi ,  Jong-chul Park ,  Jin-young Kim ,  Ki-jin Park

IPC分类号： H01L23/58

CPC分类号： H01L21/76897 ,  H01L21/76831

摘要： Methods of forming integrated circuit devices include upper sidewall spacers in contact holes to provide enhanced electrical isolation to contact plugs therein while maintaining relatively low contact resistance. These methods include forming an interlayer insulating layer on a semiconductor substrate. The interlayer insulating layer includes at least a first electrically insulating layer of a first material on the semiconductor substrate and a second electrically insulating layer of a second material on the first electrically insulating layer. A contact hole is formed that extends through the interlayer insulating layer and exposes a primary surface of the semiconductor substrate. This contact hole may be formed by selectively etching the second electrically insulating layer and the first electrically insulating layer in sequence and at a faster etch rate of the first material relative to the second material. This sequential etching of the first material at a faster rate than the second material may yield a contact hole having a recessed sidewall.

公开(公告)号：US08916447B2

公开(公告)日：2014-12-23

申请号：US13293777

申请日：2011-11-10

申请人： Jong-chul Park ,  Sang-sup Jeong

发明人： Jong-chul Park ,  Sang-sup Jeong

IPC分类号： H01L21/02 ,  H01L21/60 ,  H01L21/762 ,  H01L27/108 ,  H01L27/02

CPC分类号： H01L27/0207 ,  H01L27/10855 ,  H01L27/10888

摘要： A method uses a line pattern to form a semiconductor device including asymmetrical contact arrays. The method includes forming a plurality of parallel first conductive line layers extending in a first direction on a semiconductor substrate. In this method, the semiconductor substrate may have active regions forming an oblique angle with the first direction. The method may further include forming a first mask layer and a second mask layer and using the first mask layer and the second mask layer to form a trench comprising a line area and a contact area by etching the first conductive line layers using the first mask layer and the second mask layer. The method further includes forming a gap filling layer filling the line area of the trench and forming a spacer of sidewalls of the contact area and forming a second conductive line layer electrically connected to the active region.

摘要翻译： 一种方法使用线图形成包括不对称接触阵列的半导体器件。 该方法包括在半导体衬底上形成沿第一方向延伸的多个平行的第一导电线层。 在该方法中，半导体衬底可以具有与第一方向成倾斜角的有源区域。 该方法还可以包括形成第一掩模层和第二掩模层，并且使用第一掩模层和第二掩模层通过使用第一掩模层蚀刻第一导线层以形成包括线区域和接触区域的沟槽 和第二掩模层。 该方法还包括形成填充沟槽的线区域并形成接触区域的侧壁的间隔物的间隙填充层，并形成电连接到有源区域的第二导线层。