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    Method for fabricating semiconductor device
    6.
    发明授权
    Method for fabricating semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US07998862B2

    公开(公告)日：2011-08-16

    申请号：US12689344

    申请日：2010-01-19

    申请人： Kunsik Park ,  Kyu-Ha Baek ,  Lee-Mi Do ,  Dong-Pyo Kim ,  Ji Man Park

    发明人： Kunsik Park ,  Kyu-Ha Baek ,  Lee-Mi Do ,  Dong-Pyo Kim ,  Ji Man Park

    IPC分类号： H01L21/4763 ,  H01L21/44

    CPC分类号： H01L21/76898 ,  H01L21/2885

    摘要： A method of fabricating a semiconductor device includes forming a via hole in a semiconductor substrate, forming an isolation layer on an inner side of the via hole, forming a diffusion barrier layer over an upper portion of the semiconductor substrate and the inner side of the via hole where the isolation layer is formed, arranging a solvent, which contains electrically charged metal particles, on the semiconductor substrate where the diffusion barrier layer is formed, and filling the via hole with the metal particles by moving the metal particles using applied external force. The applied external force said includes a voltage causing an electric current to flow between the semiconductor substrate and the solvent, an electrical field applied between the semiconductor substrate and the solvent, or a magnetic field applied between the semiconductor substrate and the solvent.

    摘要翻译： 一种制造半导体器件的方法包括在半导体衬底中形成通孔，在通孔的内侧形成隔离层，在半导体衬底的上部和通孔的内侧形成扩散阻挡层 形成隔离层的孔，在形成有扩散阻挡层的半导体衬底上布置含有带电荷的金属颗粒的溶剂，并通过使用外力移动金属颗粒来填充通孔。 所施加的外力包括导致电流在半导体衬底和溶剂之间流动的电压，施加在半导体衬底和溶剂之间的电场或施加在半导体衬底和溶剂之间的磁场。

    TEMPLATES USED FOR NANOIMPRINT LITHOGRAPHY AND METHODS FOR FABRICATING THE SAME
    7.
    发明申请
    TEMPLATES USED FOR NANOIMPRINT LITHOGRAPHY AND METHODS FOR FABRICATING THE SAME 审中-公开
    用于纳米压印的模板及其制作方法

    公开(公告)号：US20110104322A1

    公开(公告)日：2011-05-05

    申请号：US12763380

    申请日：2010-04-20

    申请人： Kunsik PARK ,  Dong-Pyo Kim ,  Ji Man Park ,  Kyu-Ha Baek ,  Lee-Mi Do

    发明人： Kunsik PARK ,  Dong-Pyo Kim ,  Ji Man Park ,  Kyu-Ha Baek ,  Lee-Mi Do

    IPC分类号： B28B11/08 ,  B05D3/10

    CPC分类号： G03F7/0002 ,  B82Y10/00 ,  B82Y40/00

    摘要： Provided are a template used for nanoimprint lithography and a method for fabricating the same. A raised first deposition layer pattern including at least one downwardly sloped side surface is formed on a substrate. A second deposition layer pattern covering the side surface of the raised first deposition layer pattern and progressively decreasing in width downward along the side surface of the raised first deposition layer pattern is formed. A third deposition layer is formed on the entire surface of a structure on which the second deposition layer pattern. A second deposition layer nano pattern between the raised first deposition layer pattern and a planarized third deposition layer is formed by planarizing the third deposition layer to expose upper surfaces of the raised first deposition layer pattern and the second deposition layer pattern. An intaglio nano pattern defined by side surfaces sloped downward from upper surfaces of the raised first deposition layer pattern and the planarized third deposition layer to the surface of the substrate is formed by removing the second deposition layer nano pattern.

    摘要翻译： 提供了用于纳米压印光刻的模板及其制造方法。 在衬底上形成包括至少一个向下倾斜的侧表面的升高的第一沉积层图案。 形成覆盖凸起的第一沉积层图案的侧表面并且沿着凸起的第一沉积层图案的侧表面沿着宽度逐渐减小的第二沉积层图案。 第三沉积层形成在其上具有第二沉积层图案的结构的整个表面上。 在凸起的第一沉积层图案和平坦化的第三沉积层之间的第二沉积层纳米图案通过平坦化第三沉积层以暴露升高的第一沉积层图案和第二沉积层图案的上表面而形成。 通过去除第二沉积层纳米图案，形成由从凸起的第一沉积层图案的上表面向下倾斜的侧表面和平坦化的第三沉积层到基板的表面限定的凹版纳米图案。

    METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
    8.
    发明申请
    METHOD FOR FABRICATING SEMICONDUCTOR DEVICE 失效
    制造半导体器件的方法

    公开(公告)号：US20110136338A1

    公开(公告)日：2011-06-09

    申请号：US12689344

    申请日：2010-01-19

    申请人： Kunsik Park ,  Kyu-Ha Baek ,  Lee-Mi Do ,  Dong-Pyo Kim ,  Ji Man Park

    发明人： Kunsik Park ,  Kyu-Ha Baek ,  Lee-Mi Do ,  Dong-Pyo Kim ,  Ji Man Park

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76898 ,  H01L21/2885

    摘要： A method of fabricating a semiconductor device includes forming a via hole in a semiconductor substrate, forming an isolation layer on an inner side of the via hole, forming a diffusion barrier layer over an upper portion of the semiconductor substrate and the inner side of the via hole where the isolation layer is formed, arranging a solvent, which contains electrically charged metal particles, on the semiconductor substrate where the diffusion barrier layer is formed, and filling the via hole with the metal particles by moving the metal particles using applied external force. The applied external force said includes a voltage causing an electric current to flow between the semiconductor substrate and the solvent, an electrical field applied between the semiconductor substrate and the solvent, or a magnetic field applied between the semiconductor substrate and the solvent.

    摘要翻译： 一种制造半导体器件的方法包括在半导体衬底中形成通孔，在通孔的内侧形成隔离层，在半导体衬底的上部和通孔的内侧形成扩散阻挡层 形成隔离层的孔，在形成有扩散阻挡层的半导体衬底上布置含有带电荷的金属颗粒的溶剂，并通过使用外力移动金属颗粒来填充通孔。 所施加的外力包括导致电流在半导体衬底和溶剂之间流动的电压，施加在半导体衬底和溶剂之间的电场或施加在半导体衬底和溶剂之间的磁场。

    Self aligned field effect transistor structure
    9.
    发明授权
    Self aligned field effect transistor structure 有权
    自对准场效应晶体管结构

    公开(公告)号：US08143670B2

    公开(公告)日：2012-03-27

    申请号：US12619116

    申请日：2009-11-16

    申请人： Lee-Mi Do ,  Kyu-Ha Baek

    发明人： Lee-Mi Do ,  Kyu-Ha Baek

    IPC分类号： H01L29/76

    CPC分类号： H01L29/66742 ,  H01L29/42384 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66575

    摘要： Provided is a self aligned filed effect transistor structure. The self aligned field effect transistor structure includes: an active region on a substrate; a U-shaped gate insulation pattern on the active region; and a gate electrode self-aligned by the gate insulation pattern and disposed in an inner space of the gate insulation pattern.

    摘要翻译： 提供了自对准的场效应晶体管结构。 自对准场效应晶体管结构包括：衬底上的有源区; 活动区域上的U形栅绝缘图案; 以及通过栅极绝缘图案自对准并设置在栅极绝缘图案的内部空间中的栅电极。

    SELF ALIGNED FIELD EFFECT TRANSISTOR STRUCTURE
    10.
    发明申请
    SELF ALIGNED FIELD EFFECT TRANSISTOR STRUCTURE 有权
    自对准场效应晶体管结构

    公开(公告)号：US20100155793A1

    公开(公告)日：2010-06-24

    申请号：US12619116

    申请日：2009-11-16

    申请人： Lee-Mi DO ,  Kyu-Ha Baek

    发明人： Lee-Mi DO ,  Kyu-Ha Baek

    IPC分类号： H01L29/78

    CPC分类号： H01L29/66742 ,  H01L29/42384 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66575

    摘要： Provided is a self aligned filed effect transistor structure. The self aligned field effect transistor structure includes: an active region on a substrate; a U-shaped gate insulation pattern on the active region; and a gate electrode self-aligned by the gate insulation pattern and disposed in an inner space of the gate insulation pattern.

    摘要翻译： 提供了自对准的场效应晶体管结构。 自对准场效应晶体管结构包括：衬底上的有源区; 活动区域上的U形栅绝缘图案; 以及通过栅极绝缘图案自对准并设置在栅极绝缘图案的内部空间中的栅电极。