公开(公告)号：US08173511B2

公开(公告)日：2012-05-08

申请号：US12094303

申请日：2006-10-29

申请人： Joost Melai ,  Erwin Hijzen ,  Philippe Meunier-Beillard ,  Johannes Josephus Theodorus Marinus Donkers

发明人： Joost Melai ,  Erwin Hijzen ,  Philippe Meunier-Beillard ,  Johannes Josephus Theodorus Marinus Donkers

IPC分类号： H01L21/331 ,  H01L21/8222

CPC分类号： H01L29/66242 ,  H01L29/66287

摘要： The invention relates to a method of manufacturing a semiconductor device (10) with a substrate (11) and a semiconductor body (12) which is provided with at least one bipolar transistor having an emitter region (1), a base region (2) and a collector region (3), wherein in the semiconductor body (12) a first semiconductor region (13) is formed that forms one (3) of the collector and emitter regions (1,3) and on the surface of the semiconductor body (12) a stack of layers is formed comprising a first insulating layer (4), a polycrystalline semiconductor layer (5) and a second insulating layer (6) in which stack an opening (7) is formed, after which by non-selective epitaxial growth a further semiconductor layer (22) is deposited of which a monocrystalline horizontal part on the bottom of the opening (7) forms the base region (2) and of which a polycrystalline vertical part (2A) on a side face of the opening (7) is connected to the polycrystalline semiconductor layer (5), after which spacers (S) are formed parallel to the side face of the opening (7) and a second semiconductor region (31) is formed between said spacers (S) forming the other one (1) of the emitter and collector regions (1,3). According to the invention the above method is characterized in that before the further semiconductor layer (22) is deposited, the second insulating layer (6) is provided with an end portion (6A) that viewed in projection overhangs an end portion (5A) of the underlying semiconductor layer (5). In this way bipolar transistor devices can be obtained with good high frequency properties in a cost effective manner.

摘要翻译： 本发明涉及一种制造半导体器件（10）的方法，所述半导体器件（10）具有衬底（11）和半导体本体（12），所述半导体器件（12）具有至少一个具有发射极区域（1），基极区域（2） 和集电极区域（3），其中在所述半导体本体（12）中形成第一半导体区域（13），所述第一半导体区域形成所述集电极和发射极区域（1,3）中的一个（3）并且在所述半导体主体 （12）形成一叠层，其包括形成有开口（7）的第一绝缘层（4），多晶半导体层（5）和第二绝缘层（6），之后通过非选择性 外延生长沉积另外的半导体层（22），其中开口（7）的底部上的单晶水平部分形成基部区域（2），并且在该开口的侧面上具有多晶垂直部分（2A） （7）连接到多晶半导体层（5），之后是间隔 （S）形成为平行于开口（7）的侧面，并且在形成发射极和集电极区域（1,3）的另一个（1）的所述间隔物（S）之间形成第二半导体区域（31） ）。 根据本发明，上述方法的特征在于，在沉积另外的半导体层（22）之前，第二绝缘层（6）设置有端部（6A），其从突出部分观察到突出部分 底层半导体层（5）。 以这种方式，可以以成本有效的方式获得具有良好高频特性的双极晶体管器件。

公开(公告)号：US20120168908A1

公开(公告)日：2012-07-05

申请号：US13076290

申请日：2011-03-30

申请人： Tony Vanhoucke ,  Johannes Josephus Theodorus Marinus Donkers ,  Hans Mertens ,  Philippe Meunier-Beillard

发明人： Tony Vanhoucke ,  Johannes Josephus Theodorus Marinus Donkers ,  Hans Mertens ,  Philippe Meunier-Beillard

IPC分类号： H01L29/70 ,  H01L21/328

CPC分类号： H01L29/66318 ,  H01L29/0817 ,  H01L29/66242

摘要： A bipolar transistor is fabricated having a collector (52) in a substrate (1) and a base (57, 58) and an emitter (59) formed over the substrate. The base has a stack region (57) which is laterally separated from the emitter (59) by an electrically insulating spacer (71). The insulating spacer (71) has a width dimension at its top end at least as large as the width dimension at its bottom end and forms a Γ-shape or an oblique shape. The profile reduces the risk of silicide bridging at the top of the spacer in subsequent processing, while maintaining the width of emitter window.

摘要翻译： 制造了在衬底（1）中具有集电体（52）和形成在衬底上的基极（57,58）和发射极（59）的双极晶体管。 底座具有通过电绝缘间隔件（71）与发射器（59）横向分开的堆叠区域（57）。 绝缘间隔件（71）的顶端的宽度尺寸至少与其底端的宽度尺寸一样大，并形成一个“G”形或一个倾斜的形状。 该轮廓降低了后续处理中间隔物顶部的硅化物桥接的风险，同时保持了发射器窗口的宽度。

公开(公告)号：US08704335B2

公开(公告)日：2014-04-22

申请号：US13076290

申请日：2011-03-30

申请人： Tony Vanhoucke ,  Johannes Josephus Theodorus Marinus Donkers ,  Hans Mertens ,  Philippe Meunier-Beillard

发明人： Tony Vanhoucke ,  Johannes Josephus Theodorus Marinus Donkers ,  Hans Mertens ,  Philippe Meunier-Beillard

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L21/331 ,  H01L21/00

CPC分类号： H01L29/66318 ,  H01L29/0817 ,  H01L29/66242

摘要： A bipolar transistor is fabricated having a collector (52) in a substrate (1) and a base (57, 58) and an emitter (59) formed over the substrate. The base has a stack region (57) which is laterally separated from the emitter (59) by an electrically insulating spacer (71). The insulating spacer (71) has a width dimension at its top end at least as large as the width dimension at its bottom end and forms a Γ-shape or an oblique shape. The profile reduces the risk of silicide bridging at the top of the spacer in subsequent processing, while maintaining the width of emitter window.

摘要翻译： 制造了在衬底（1）中具有集电体（52）和形成在衬底上的基极（57,58）和发射极（59）的双极晶体管。 底座具有通过电绝缘间隔件（71）与发射器（59）横向分开的堆叠区域（57）。 绝缘间隔件（71）的顶端的宽度尺寸至少与其底端的宽度尺寸一样大，并形成一个“G”形或一个倾斜的形状。 该轮廓降低了后续处理中间隔物顶部的硅化物桥接的风险，同时保持了发射器窗口的宽度。

公开(公告)号：US08242500B2

公开(公告)日：2012-08-14

申请号：US13005435

申请日：2011-01-12

申请人： Philippe Meunier-Beillard ,  Johannes Josephus Theodorus Marinus Donkers ,  Hans Mertens ,  Tony Vanhoucke

发明人： Philippe Meunier-Beillard ,  Johannes Josephus Theodorus Marinus Donkers ,  Hans Mertens ,  Tony Vanhoucke

IPC分类号： H01L29/04

CPC分类号： H01L29/66242 ,  H01L29/1004 ,  H01L29/7378

摘要： Disclosed is a method of forming a heterojunction bipolar transistor (HBT), comprising depositing a first stack comprising an polysilicon layer (16) and a sacrificial layer (18) on a mono-crystalline silicon substrate surface (10); patterning the first stack to form a trench (22) extending to the substrate; depositing a silicon layer (24) over the resultant structure; depositing a silicon-germanium-carbon layer (26) over the resultant structure; selectively removing the silicon-germanium-carbon layer (26) from the sidewalls of the trench (22); depositing a boron-doped silicon-germanium-carbon layer (28) over the resultant structure; depositing a further silicon-germanium-carbon layer (30) over the resultant structure; depositing a boron-doped further silicon layer (32) over the resultant structure; forming dielectric spacers (34) on the sidewalls of the trench (22); filling the trench (22) with an emitter material (36); exposing polysilicon regions (16) outside the side walls of the trench by selectively removing the sacrificial layer (18) of the first stack; implanting boron impurities into the exposed polysilicon regions (16) to define base implants; and exposing the resultant structure to a thermal budget for annealing the boron impurities. A HBT formed by this method is also disclosed.

摘要翻译： 公开了一种形成异质结双极晶体管（HBT）的方法，包括在单晶硅衬底表面（10）上沉积包括多晶硅层（16）和牺牲层（18）的第一堆叠; 图案化第一堆叠以形成延伸到衬底的沟槽（22）; 在所得结构上沉积硅层（24）; 在所得结构上沉积硅 - 锗 - 碳层（26）; 从所述沟槽（22）的侧壁选择性地去除所述硅 - 锗 - 碳层（26）。 在所得结构上沉积硼掺杂的硅 - 锗 - 碳层（28）; 在所得结构上沉积另外的硅 - 锗 - 碳层（30）; 在所得结构上沉积硼掺杂的另外的硅层（32）; 在所述沟槽（22）的侧壁上形成介电间隔物（34）; 用发射体材料（36）填充沟槽（22）; 通过选择性地去除第一堆叠的牺牲层（18），在沟槽的侧壁外露出多晶硅区域（16）; 将硼杂质注入暴露的多晶硅区域（16）中以限定基底植入物; 并将所得结构暴露于用于退火硼杂质的热预算。 还公开了通过该方法形成的HBT。

公开(公告)号：US08524551B2

公开(公告)日：2013-09-03

申请号：US13547067

申请日：2012-07-12

申请人： Philippe Meunier-Beillard ,  Johannes Josephus Theodorus Marinus Donkers ,  Hans Mertens ,  Tony Vanhoucke

发明人： Philippe Meunier-Beillard ,  Johannes Josephus Theodorus Marinus Donkers ,  Hans Mertens ,  Tony Vanhoucke

IPC分类号： H01L21/337

CPC分类号： H01L29/66242 ,  H01L29/1004 ,  H01L29/7378

摘要： A method of forming a heterojunction bipolar transistor by depositing a first stack comprising an polysilicon layer and a sacrificial layer on a mono-crystalline silicon substrate surface; patterning that stack to form a trench extending to the substrate; depositing a silicon layer over the resultant structure; depositing a silicon-germanium-carbon layer over the resultant structure; selectively removing the silicon-germanium-carbon layer from the sidewalls of the trench; depositing a boron-doped silicon-germanium-carbon layer over the resultant structure; depositing a further silicon-germanium-carbon layer over the resultant structure; depositing a boron-doped further silicon layer over the resultant structure; forming dielectric spacers on the trench sidewalls; filling the trench with emitter material; exposing polysilicon regions outside the trench side walls by selectively removing the sacrificial layer; implanting boron impurities into the exposed polysilicon regions to define base implants; and exposing the resultant structure to a thermal budget for annealing the boron impurities.

摘要翻译： 一种通过在单晶硅衬底表面上沉积包括多晶硅层和牺牲层的第一堆叠来形成异质结双极晶体管的方法; 图案化该叠层以形成延伸到衬底的沟槽; 在所得结构上沉积硅层; 在所得结构上沉积硅 - 锗 - 碳层; 从沟槽的侧壁选择性地去除硅 - 锗 - 碳层; 在所得结构上沉积硼掺杂的硅 - 锗 - 碳层; 在所得结构上沉积另外的硅 - 锗 - 碳层; 在所得结构上沉积硼掺杂的另外的硅层; 在沟槽侧壁上形成电介质间隔物; 用发射体材料填充沟槽; 通过选择性地去除牺牲层来暴露沟槽侧壁外的多晶硅区域; 将硼杂质注入暴露的多晶硅区域以限定基底植入物; 并将所得结构暴露于用于退火硼杂质的热预算。

公开(公告)号：US08872237B2

公开(公告)日：2014-10-28

申请号：US13299755

申请日：2011-11-18

申请人： Tony Vanhoucke ,  Johannes Josephus Theodorus Marinus Donkers ,  Hans Mertens ,  Blandine Duriez ,  Evelyne Gridelet

发明人： Tony Vanhoucke ,  Johannes Josephus Theodorus Marinus Donkers ,  Hans Mertens ,  Blandine Duriez ,  Evelyne Gridelet

IPC分类号： H01L29/66 ,  H01L29/737 ,  H01L29/08

CPC分类号： H01L29/0821 ,  H01L29/66242 ,  H01L29/7378

摘要： Disclosed is a method of manufacturing a heterojunction bipolar transistor comprising a substrate, an upper region of said substrate comprising an active region of the bipolar transistor bordered by shallow trench insulation, said active region comprising a buried collector region extending to a depth beyond the depth of the shallow trench insulation, the method comprising forming a trench in the substrate adjacent to said active region, said trench extending through the shallow trench insulation; at least partially filling said trench with an impurity; and forming a collector sinker in the substrate by developing said impurity to extend into the substrate to a depth beyond the depth of the shallow trench insulation. An IC comprising a heterojunction bipolar transistor manufactured by this method is also disclosed.

摘要翻译： 公开了一种制造包括衬底的异质结双极晶体管的方法，所述衬底的上部区域包括由浅沟槽绝缘体界定的双极晶体管的有源区，所述有源区包括延伸到超过深度 所述浅沟槽绝缘体，所述方法包括在所述衬底中邻近所述有源区形成沟槽，所述沟槽延伸穿过所述浅沟槽绝缘体; 至少部分地用杂质填充所述沟槽; 以及通过使所述杂质显影而在衬底中形成收集器沉降片，以延伸到衬底中深度超过浅沟槽绝缘深度的深度。 还公开了一种包括通过该方法制造的异质结双极晶体管的IC。

公开(公告)号：US08803156B2

公开(公告)日：2014-08-12

申请号：US13205932

申请日：2011-08-09

申请人： Tony Vanhoucke ,  Johannes Josephus Theodorus Marinus Donkers ,  Hans Mertens ,  Blandine Duriez ,  Evelyne Marie Josephe Fabienne Gridelet

发明人： Tony Vanhoucke ,  Johannes Josephus Theodorus Marinus Donkers ,  Hans Mertens ,  Blandine Duriez ,  Evelyne Marie Josephe Fabienne Gridelet

IPC分类号： H01L29/00 ,  H01L31/036

CPC分类号： H01L29/7378 ,  H01L29/1004 ,  H01L29/66242

摘要： A method of manufacturing a heterojunction bipolar transistor, including providing a substrate comprising an active region bordered by shallow trench insulation regions; depositing a stack of a dielectric layer and a polysilicon layer over the substrate; forming a base window in the stack, the base window extending over the active region and part of the shallow trench insulation regions, the base window having a trench extending vertically between the active region and one of the shallow trench insulation regions; growing an epitaxial base material inside the base window; forming a spacer on the exposed side walls of the base material; and filling the base window with an emitter material. A HBT manufactured in this manner and an IC including such an HBT.

摘要翻译： 一种制造异质结双极晶体管的方法，包括提供包括由浅沟槽绝缘区域界定的有源区的衬底; 在衬底上沉积介电层和多晶硅层的堆叠; 在所述堆叠中形成基窗，所述基窗在所述有源区和所述浅沟槽绝缘区的一部分上延伸，所述基窗具有在所述有源区和所述浅沟绝缘区之间的垂直延伸的沟槽; 在基座窗内生长外延基体材料; 在基材的暴露的侧壁上形成间隔物; 并用发射体材料填充基座窗口。 以这种方式制造的HBT和包括这种HBT的IC。

公开(公告)号：US20120132961A1

公开(公告)日：2012-05-31

申请号：US13299755

申请日：2011-11-18

申请人： Tony Vanhoucke ,  Johannes Josephus Theodorus Marinus Donkers ,  Hans Mertens ,  Blandine Duriez ,  Evelyne Gridelet

发明人： Tony Vanhoucke ,  Johannes Josephus Theodorus Marinus Donkers ,  Hans Mertens ,  Blandine Duriez ,  Evelyne Gridelet

IPC分类号： H01L29/737 ,  H01L21/328

CPC分类号： H01L29/0821 ,  H01L29/66242 ,  H01L29/7378

摘要： Disclosed is a method of manufacturing a heterojunction bipolar transistor comprising a substrate, an upper region of said substrate comprising an active region of the bipolar transistor bordered by shallow trench insulation, said active region comprising a buried collector region extending to a depth beyond the depth of the shallow trench insulation, the method comprising forming a trench in the substrate adjacent to said active region, said trench extending through the shallow trench insulation; at least partially filling said trench with an impurity; and forming a collector sinker in the substrate by developing said impurity to extend into the substrate to a depth beyond the depth of the shallow trench insulation. An IC comprising a heterojunction bipolar transistor manufactured by this method is also disclosed.

摘要翻译： 公开了一种制造包括衬底的异质结双极晶体管的方法，所述衬底的上部区域包括由浅沟槽绝缘体界定的双极晶体管的有源区，所述有源区包括延伸到超过深度 所述浅沟槽绝缘体，所述方法包括在所述衬底中邻近所述有源区形成沟槽，所述沟槽延伸穿过所述浅沟槽绝缘体; 至少部分地用杂质填充所述沟槽; 以及通过使所述杂质显影而在衬底中形成收集器沉降片，以延伸到衬底中深度超过浅沟槽绝缘深度的深度。 还公开了一种包括通过该方法制造的异质结双极晶体管的IC。

公开(公告)号：US08686424B2

公开(公告)日：2014-04-01

申请号：US13616400

申请日：2012-09-14

申请人： Evelyne Gridelet ,  Johannes Josephus Theodorus Marinus Donkers ,  Tony Vanhoucke ,  Petrus Hubertus Cornelis Magnee ,  Hans Mertens ,  Blandine Duriez

发明人： Evelyne Gridelet ,  Johannes Josephus Theodorus Marinus Donkers ,  Tony Vanhoucke ,  Petrus Hubertus Cornelis Magnee ,  Hans Mertens ,  Blandine Duriez

IPC分类号： H01L29/72

CPC分类号： H01L29/732 ,  H01L29/66242 ,  H01L29/7378

摘要： Disclosed is a method of manufacturing a bipolar transistor, comprising providing a substrate (10) comprising a first isolation region (12) separated from a second isolation region by an active region (11) comprising a collector impurity; forming a layer stack over said substrate, said layer stack comprising a base layer (14, 14′), a silicon capping layer (15) over said base layer and a silicon-germanium (SiGe) base contact layer (40) over said silicon capping layer; etching the SiGe base contact layer to form an emitter window (50) over the collector impurity, wherein the silicon emitter cap layer is used as etch stop layer; forming sidewall spacers (22) in the emitter window; and filling the emitter window with an emitter material (24). A bipolar transistor manufactured in accordance with this method and an IC comprising one or more of such bipolar transistors are also disclosed.

摘要翻译： 公开了一种制造双极晶体管的方法，包括提供包括通过包括集电极杂质的有源区（11）与第二隔离区分离的第一隔离区（12）的衬底（10） 在所述衬底上形成层堆叠，所述层堆叠包括基底层（14,14'），所述基底层上的硅覆盖层（15）和位于所述硅上的硅 - 锗（SiGe）基接触层（40） 盖层; 蚀刻SiGe基极接触层以在集电极杂质上形成发射极窗口（50），其中硅发射极盖层用作蚀刻停止层; 在发射器窗口中形成侧壁间隔物（22）; 以及用发射体材料（24）填充发射器窗口。 还公开了根据该方法制造的双极晶体管和包括一个或多个这样的双极晶体管的IC。

公开(公告)号：US20120037914A1

公开(公告)日：2012-02-16

申请号：US13205932

申请日：2011-08-09

申请人： Tony Vanhoucke ,  Johannes Josephus Theodorus Marinus Donkers ,  Hans Mertens ,  Blandine Duriez ,  Evelyne Marie Josephe Fabienne Gridelet

发明人： Tony Vanhoucke ,  Johannes Josephus Theodorus Marinus Donkers ,  Hans Mertens ,  Blandine Duriez ,  Evelyne Marie Josephe Fabienne Gridelet

IPC分类号： H01L29/737 ,  H01L21/331

CPC分类号： H01L29/7378 ,  H01L29/1004 ,  H01L29/66242

摘要： A method of manufacturing a heterojunction bipolar transistor, including providing a substrate comprising an active region bordered by shallow trench insulation regions; depositing a stack of a dielectric layer and a polysilicon layer over the substrate; forming a base window in the stack, the base window extending over the active region and part of the shallow trench insulation regions, the base window having a trench extending vertically between the active region and one of the shallow trench insulation regions; growing an epitaxial base material inside the base window; forming a spacer on the exposed side walls of the base material; and filling the base window with an emitter material. A HBT manufactured in this manner and an IC including such an HBT.

摘要翻译： 一种制造异质结双极晶体管的方法，包括提供包括由浅沟槽绝缘区域界定的有源区的衬底; 在衬底上沉积介电层和多晶硅层的堆叠; 在所述堆叠中形成基窗，所述基窗在所述有源区和所述浅沟槽绝缘区的一部分上延伸，所述基窗具有在所述有源区和所述浅沟绝缘区之间的垂直延伸的沟槽; 在基座窗内生长外延基底材料; 在基材的暴露的侧壁上形成间隔物; 并用发射体材料填充基座窗口。 以这种方式制造的HBT和包括这种HBT的IC。