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    Bipolar transistor manufacturing method, bipolar transistor and integrated circuit
    4.
    发明授权
    Bipolar transistor manufacturing method, bipolar transistor and integrated circuit 有权
    双极晶体管制造方法，双极晶体管和集成电路

    公开(公告)号：US08686424B2

    公开(公告)日：2014-04-01

    申请号：US13616400

    申请日：2012-09-14

    申请人： Evelyne Gridelet ,  Johannes Josephus Theodorus Marinus Donkers ,  Tony Vanhoucke ,  Petrus Hubertus Cornelis Magnee ,  Hans Mertens ,  Blandine Duriez

    发明人： Evelyne Gridelet ,  Johannes Josephus Theodorus Marinus Donkers ,  Tony Vanhoucke ,  Petrus Hubertus Cornelis Magnee ,  Hans Mertens ,  Blandine Duriez

    IPC分类号： H01L29/72

    CPC分类号： H01L29/732 ,  H01L29/66242 ,  H01L29/7378

    摘要： Disclosed is a method of manufacturing a bipolar transistor, comprising providing a substrate (10) comprising a first isolation region (12) separated from a second isolation region by an active region (11) comprising a collector impurity; forming a layer stack over said substrate, said layer stack comprising a base layer (14, 14′), a silicon capping layer (15) over said base layer and a silicon-germanium (SiGe) base contact layer (40) over said silicon capping layer; etching the SiGe base contact layer to form an emitter window (50) over the collector impurity, wherein the silicon emitter cap layer is used as etch stop layer; forming sidewall spacers (22) in the emitter window; and filling the emitter window with an emitter material (24). A bipolar transistor manufactured in accordance with this method and an IC comprising one or more of such bipolar transistors are also disclosed.

    摘要翻译： 公开了一种制造双极晶体管的方法，包括提供包括通过包括集电极杂质的有源区（11）与第二隔离区分离的第一隔离区（12）的衬底（10） 在所述衬底上形成层堆叠，所述层堆叠包括基底层（14,14'），所述基底层上的硅覆盖层（15）和位于所述硅上的硅 - 锗（SiGe）基接触层（40） 盖层; 蚀刻SiGe基极接触层以在集电极杂质上形成发射极窗口（50），其中硅发射极盖层用作蚀刻停止层; 在发射器窗口中形成侧壁间隔物（22）; 以及用发射体材料（24）填充发射器窗口。 还公开了根据该方法制造的双极晶体管和包括一个或多个这样的双极晶体管的IC。

    HETEROJUNCTION BIOPOLAR TRANSISTOR AND MANUFACTURING METHOD
    5.
    发明申请
    HETEROJUNCTION BIOPOLAR TRANSISTOR AND MANUFACTURING METHOD 有权
    异源双极晶体管和制造方法

    公开(公告)号：US20120037914A1

    公开(公告)日：2012-02-16

    申请号：US13205932

    申请日：2011-08-09

    申请人： Tony Vanhoucke ,  Johannes Josephus Theodorus Marinus Donkers ,  Hans Mertens ,  Blandine Duriez ,  Evelyne Marie Josephe Fabienne Gridelet

    发明人： Tony Vanhoucke ,  Johannes Josephus Theodorus Marinus Donkers ,  Hans Mertens ,  Blandine Duriez ,  Evelyne Marie Josephe Fabienne Gridelet

    IPC分类号： H01L29/737 ,  H01L21/331

    CPC分类号： H01L29/7378 ,  H01L29/1004 ,  H01L29/66242

    摘要： A method of manufacturing a heterojunction bipolar transistor, including providing a substrate comprising an active region bordered by shallow trench insulation regions; depositing a stack of a dielectric layer and a polysilicon layer over the substrate; forming a base window in the stack, the base window extending over the active region and part of the shallow trench insulation regions, the base window having a trench extending vertically between the active region and one of the shallow trench insulation regions; growing an epitaxial base material inside the base window; forming a spacer on the exposed side walls of the base material; and filling the base window with an emitter material. A HBT manufactured in this manner and an IC including such an HBT.

    摘要翻译： 一种制造异质结双极晶体管的方法，包括提供包括由浅沟槽绝缘区域界定的有源区的衬底; 在衬底上沉积介电层和多晶硅层的堆叠; 在所述堆叠中形成基窗，所述基窗在所述有源区和所述浅沟槽绝缘区的一部分上延伸，所述基窗具有在所述有源区和所述浅沟绝缘区之间的垂直延伸的沟槽; 在基座窗内生长外延基底材料; 在基材的暴露的侧壁上形成间隔物; 并用发射体材料填充基座窗口。 以这种方式制造的HBT和包括这种HBT的IC。

    MOSFETs with channels on nothing and methods for forming the same
    7.
    发明授权
    MOSFETs with channels on nothing and methods for forming the same 有权
    没有通道的MOSFET和用于形成通道的方法

    公开(公告)号：US08779554B2

    公开(公告)日：2014-07-15

    申请号：US13436322

    申请日：2012-03-30

    申请人： Georgios Vellianitis ,  Mark van Dal ,  Blandine Duriez

    发明人： Georgios Vellianitis ,  Mark van Dal ,  Blandine Duriez

    IPC分类号： H01L29/06 ,  H01L29/778

    CPC分类号： H01L21/76264 ,  H01L21/30604 ,  H01L21/764 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/205 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7853

    摘要： A device includes a semiconductor substrate, and a channel region of a transistor over the semiconductor substrate. The channel region includes a semiconductor material. An air gap is disposed under and aligned to the channel region, with a bottom surface of the channel region exposed to the air gap. Insulation regions are disposed on opposite sides of the air gap, wherein a bottom surface of the channel region is higher than top surfaces of the insulation regions. A gate dielectric of the transistor is disposed on a top surface and sidewalls of the channel region. A gate electrode of the transistor is over the gate dielectric.

    摘要翻译： 一种器件包括半导体衬底和半导体衬底上的晶体管的沟道区域。 沟道区域包括半导体材料。 气隙设置在通道区域的下方并与之对准，通道区域的底表面暴露于气隙。 绝缘区域设置在气隙的相对侧上，其中沟道区域的底表面高于绝缘区域的顶表面。 晶体管的栅极电介质设置在沟道区的顶表面和侧壁上。 晶体管的栅电极在栅极电介质上方。

    BIPOLAR TRANSISTOR MANUFACTURING METHOD, BIPOLAR TRANSISTOR AND INTEGRATED CIRCUIT
    8.
    发明申请
    BIPOLAR TRANSISTOR MANUFACTURING METHOD, BIPOLAR TRANSISTOR AND INTEGRATED CIRCUIT 有权
    双极晶体管制造方法，双极晶体管和集成电路

    公开(公告)号：US20130087799A1

    公开(公告)日：2013-04-11

    申请号：US13616400

    申请日：2012-09-14

    申请人： Evelyne GRIDELET ,  Johannes Josephus Theodorus Marinus DONKERS ,  Tony VANHOUCKE ,  Petrus Hubertus Cornelis MAGNEE ,  Hans MERTENS ,  Blandine DURIEZ

    发明人： Evelyne GRIDELET ,  Johannes Josephus Theodorus Marinus DONKERS ,  Tony VANHOUCKE ,  Petrus Hubertus Cornelis MAGNEE ,  Hans MERTENS ,  Blandine DURIEZ

    IPC分类号： H01L29/739 ,  H01L21/331

    CPC分类号： H01L29/732 ,  H01L29/66242 ,  H01L29/7378

    摘要： Disclosed is a method of manufacturing a bipolar transistor, comprising providing a substrate (10) comprising a first isolation region (12) separated from a second isolation region by an active region (11) comprising a collector impurity; forming a layer stack over said substrate, said layer stack comprising a base layer (14, 14′), a silicon capping layer (15) over said base layer and a silicon-germanium (SiGe) base contact layer (40) over said silicon capping layer; etching the SiGe base contact layer to form an emitter window (50) over the collector impurity, wherein the silicon emitter cap layer is used as etch stop layer; forming sidewall spacers (22) in the emitter window; and filling the emitter window with an emitter material (24). A bipolar transistor manufactured in accordance with this method and an IC comprising one or more of such bipolar transistors are also disclosed.

    摘要翻译： 公开了一种制造双极晶体管的方法，包括提供包括通过包括集电极杂质的有源区（11）与第二隔离区分离的第一隔离区（12）的衬底（10） 在所述衬底上形成层堆叠，所述层堆叠包括在所述基底层上方的基底层（14,14'），硅覆盖层（15）和位于所述硅上的硅 - 锗（SiGe）基底接触层（40） 盖层; 蚀刻SiGe基极接触层以在集电极杂质上形成发射极窗口（50），其中硅发射极盖层用作蚀刻停止层; 在发射器窗口中形成侧壁间隔物（22）; 以及用发射体材料（24）填充发射器窗口。 还公开了根据该方法制造的双极晶体管和包括一个或多个这样的双极晶体管的IC。

    FinFET with a buried semiconductor material between two fins
    10.
    发明授权
    FinFET with a buried semiconductor material between two fins 有权
    FinFET在两个鳍片之间具有埋入的半导体材料

    公开(公告)号：US08987835B2

    公开(公告)日：2015-03-24

    申请号：US13431727

    申请日：2012-03-27

    申请人： Georgios Vellianitis ,  Mark van Dal ,  Blandine Duriez ,  Richard Oxland

    发明人： Georgios Vellianitis ,  Mark van Dal ,  Blandine Duriez ,  Richard Oxland

    IPC分类号： H01L29/06 ,  H01L21/336

    CPC分类号： H01L29/41791 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/36 ,  H01L29/4236 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

    摘要： A fin structure for a fin field effect transistor (FinFET) device is provided. The device includes a substrate, a first semiconductor material disposed on the substrate, a shallow trench isolation (STI) region disposed over the substrate and formed on opposing sides of the first semiconductor material, and a second semiconductor material forming a first fin and a second fin disposed on the STI region, the first fin spaced apart from the second fin by a width of the first semiconductor material. The fin structure may be used to generate the FinFET device by forming a gate layer formed over the first fin, a top surface of the first semiconductor material disposed between the first and second fins, and the second fin.

    摘要翻译： 提供了一种鳍状场效应晶体管（FinFET）器件的鳍结构。 该器件包括衬底，设置在衬底上的第一半导体材料，设置在衬底上并形成在第一半导体材料的相对侧上的浅沟槽隔离（STI）区域，以及形成第一鳍片和第二半导体材料的第二半导体材料 翅片设置在STI区域上，第一鳍片与第二鳍片间隔开第一半导体材料的宽度。 翅片结构可以用于通过形成在第一鳍片上形成的栅极层，设置在第一鳍片和第二鳍片之间的第一半导体材料的顶表面和第二鳍片来形成FinFET器件。